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  Mfg pack D/C Descrpion
R.P (1)  N/A Motorola reserves the right to make changes without further notice to any
R/1 (1) 
R/H (1) 
R/S (1) 
R/W (1) 
R00 (7)  Pulse A A International Airport Industrial Park • Mailing Address: PO Box 1140
R01 (25)  AD SOT25 06+ These BCD-to-decimal decoders drivers consist of eight in- verters and t
R02 (38)  DALE SOP • ID Tagging Insertion/Extraction Supports IP Multicasting through
R03 (17)  2008 A simple op-amp circuit is used to program the output voltage of a typic
R04 (21)  05+ Out (pin 7)  The output pin assumes a logic high state once  
R05 (17)  UTC TO-220F-4 08+ • Any System Requiring RS-232 Communication Ports   - Battery
R06 (5)  ALCATEL 9945 † Full range (MIN or MAX) for LM193 is −55C to 125C, for LM29
R07 (2)  DALE SOP The TELUX™ series is a clear, non diffused LED for high end applic
R08 (6)  Spectrum. The finite Fourier transform (FFT) of the discrete-time-sampled
R09 (11)  EPCOS 05+ The HC40105 and HCT40105 are high-speed silicon-gate CMOS devices that
R0E (4)  0804+ n Internal 254 character OSD ROM usable as either (a)   190 2-color
R0K (32)  The device has low power dissipation with a 40-mA active read for the byt
R0P (8)  TMS 728 PLCC84 Only five small 1-µF ceramic capacitors are required to build a com
R0S (1)  Stores a complete video field (4:1:1) On chip adaptive recursive noise
R0X (2)  The inductor L and Schottky barrier diode SBD should be connected close t
R-1 (24)  N/A Asynchronous signals include output enable (OE), sleep mode input (ZZ),
R10 (139)  6 channel independent Electronic Volume with High Voltage Transistor. (0
R11 (514)  ROCKWELL PLCC-44 07+ Table 3:Truth table Abbreviations: L = logic LOW; H = logic HIGH; X = do
R12 (258)  CONEXANT PLCC The special requirements of a VCXO crystal are best met with a full siz
R13 (19)  DIP The highest count of the various modes is shown in the Extended Counter
R14 (109)  07+ Active low reset output. When the sense threshold has been exceeded, the
R15 (79)  N/A SMD 2000 NOTES: 1. Minimums are guaranteed but not production tested. 2. This pa
R16 (5)  AUK SOT223 07+ 4. Design your application so that the product is used within the ranges
R17 (11)  IBM 2006 The RC5033 is a synchronous mode DC-DC controller IC dedicated to provid
R18 (9)  FUJITSU 95+ 564 This super wide viewing angle at 120 together with the built in reflec
R19 (27)  CONEXANT QFP The H8/3644 Series has a system-on-a-chip architecture that includes such
R1B (4)  TI PLCC84 99+ ANALOG-TO-DIGITAL CONVERTER   Input Voltage Range   Total Unad
R1F (1)  06+ The CD54ACT163 and CD74ACT163 devices are 4-bit binary counters. These
R1L (30)  RENESIS TSSOP PB 04+ The purchaser of this device should be aware that approvals may be requi
R1R (7)  RENESAS TSOP Pb 06+ 3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10
R2- (1)  NEC QFP-64 Operating Temperature: - 55C to + 85C. (To + 125C with voltage derating.
R20 (34)  PGND: Output Stage Ground. To keep output switching noise from critical
R21 (19)  MOT PLCC52 07+ Maximum ratings are those values beyond which device damage can occur. Ma
R22 (22)  The FS612509-02 version provides an auto power-down feature that shuts of
R23 (13)  CONEXANT 99+ BGA Low 1.62V Minimum Input Voltage Guaranteed 500mA Output Current 0.5% Ini
R24 (14)  99 PARAMETER VID Section DAC Output Voltage (Note 1) DAC Output Line Regul
R25 (42)  SOIC-8 LFB Input Bias Current BRT Input Voltage Range BRT Input Bias Current L
R26 (16)  The LMS1487E is a low power differential bus/line trans- ceiver designed
R27 (55)  s+m s+m dc The maximum allowable power dissipation is function of the maximum ambi
R28 (17)  CONEXANT PLCC 2000 Information furnished by HAMAMATSU is believed to be reliable. However, n
R29 (30)  ray ray dc77 The CY25901 clock generator provides a low-electromagnetic interference
R2A (3)  MOSART 04 The device enters the CMOS standby mode when CE# is at VCC 0.3 V. Maxim
R2C (2)  TOKO DIP-5 07+/08+ Inclusion of TI products in such applications is understood to be fully a
R2E (1)  Output clock. This pin is selectable under processor control to be either
R2G (1)  Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanst
R2J (8)  RENESAS 531   An analog to digital (A/D) conversion can be accomplished with ei
R2K (4)  SK 05+ DIP The HV256 operates on a 300V supply and two low voltage supplies, 8.0V
R2M (1)  The analog input section of this evaluation board accommodates unipolar a
R2P (1)  Parameter Forward Voltage Terminal Capacitance Collector Dark Curren
R2R (1)  Remove the external load from the output, insert the jumper JP3 and appl
R2S (35)  RENESAS 2007 Note that this is independent of the sampling rate, so undersampling does
R2U (1)  The GS74116A is a high speed CMOS Static RAM organized as 262,144 words
R2W (2)  NA NA The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve hig
R2Z (2)  EPSON DIP DIP Reset will terminate any operation, e.g., Read, Erase and Program, in prog
R3 (1)  The R3 is a 10-W (per channel) efficient, class-D audio amplifier for d
R-3 (1)  NOTE: EP circuits are designed to meet the DC specifications shown in the
R3- (1)  Hualon 05+   tPHZBus disable time0.56   ns   tPLZSEL to A, B0.57
R3/ (1) 
R30 (41)  爱立信 QFN The read transaction shows a request packet at clock edge T0 containing
R31 (428)  SOT343 RICOH 03+ During power on, RESET is asserted when the supply voltage (VDD or VBAT)
R32 (48)  ZILOG SOP 01+ RS is perhaps the easiest to measure accurately. The V-I curve is measur
R33 (40)  BI DIP-14 07+/08+ Internal registers include available capacity, temperature, scaled avail-
R34 (20)  ZILOG SOP 01+   Freescale Semiconductor has developed a low cost, high volume, min
R35 (37)  ATI 06+ BGA The R1 and R2 resistances must be set so as to maintain the Hall amplif
R36 (38)  ATI An active LOW Write Enable signal (WE) controls the writing/ reading oper
R37 (17)  POWER TO-92 9924 NOTES: (1) If clock is stopped between input of 18-bit data words, latch
R38 (18)  RADIS The LP358 and LP2904 are dual low-power operational amplifiers especially
R39 (17)  QFP44 This block arbitrates a PCI access to the internal memory. When the data
R3A (1)  HY57V653220B is offering fully synchronous operation referenced to a posit
R3B (5)  SHARP DIP7 08+ In multi-drop scan systems, a scan tester can select indi- vidual STA111
R3C (6)  TI 07+ Picture Structure Improvement including Color Transition Improvement, L
R3H (1)  Electrostatic discharge can cause damage ranging from perfor- mance degr
R3S (2)  P.I.C 02+ VCORE+ VCORE Output Sense. Differential sensing of the output voltage. Us
R3Y (1)  As long as the LOCK register is not set, the output characteristic can
R4- (5)  0 0
R40 (67)  arco arco dc00 served When the S input is LOW a CP HIGH-LOW tran- sition transfers data
R41 (50)  MITSUMI SMD 2005 Small number of external components: inductor, diode and capacitor. Ult
R42 (31)  LITTELFUSE 5X7保险管 Parameter Relay Portion (Pins 15,16)   Output Characteristics @ 25
R43 (23)  Stresses above those listed under Absolute Maximum Ratings may cause perm
R44 (3)  00 Low power   1.3 mA supply current/amplifier High speed   125
R45 (161)  LITTELFUSE 1808-4A 05+ *CPU: Socket 370 for Intel Celeron/Coppermine/Tualatin  800MHz~1.2GH
R46 (60)  LITTELFUSE 2512-2A 05+   SGS-THOMSON Microelectronics GROUP OF COMPANIES  Australia -
R47 (24)  RTC SMD N/A Extremely Wide Operating Voltage   1.5 to 3.6 Volts Extended Tempe
R48 (11)  INTERSIL SOP-20 01+ The processor features a full set of program control, logical, and integer
R49 (12)  LITTELFUSE 1808-500MA 05+ Output current rating may be restricted to a value determined by system
R4E (1)  Hynix HYMD264646A(L)8J-J series is unbuffered 184-pin double data rate Syn
R4K (1)  SAMPLE CLOCKS   DATACLK, SHP, SHD Clock Period   DATACLK High/
R4S (1)  SSMD 00+ The FM811/FM812 is a low cost microprocessor supervisory circuit that as
R4X (1)  In AC coupling the circuit can be oper- ated at modulation currents above
R-5 (1)    The MOSFET output stage of this power operational ampli- fier has
R5- (2)  RENESAS SMD 2000+ Operation in -40C - 125C Environment TTL/DTL/CMOS Compatible Inputs NAND
R5. (1)  JST N/A 2002 When active, the transmitter is configured to be operational, other
R50 (64)  ZIL PLCC44 While Atmel provides four options for implementing a gate array design,
R51 (36)  T PLCC • TOSHIBA is continually working to improve the quality and reliabil
R52 (17)  RICOH 2003 SMD also be used independent of the HALT or IDLE modes Each I O pin has soft
R53 (123)  OKI 03+ SSOP PFKC03 series required a minimum 10% loading on the output to maintain s
R54 (75)  RICOH ? 08+? Virtex FPGAs are SRAM-based, and are customized by loading configuration
R55 (87)  RICOH 05+ Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem
R56 (18)  RET 06+ 500 The MAX4364/MAX4365 are bridged audio power amplifiers intended for porta
R57 (6)  Programmable options include the length of pipeline (Read latency of 1,2
R58 (7)  JRC PLCC 97+ The MAX3275/MAX3277 are transimpedance amplifiers designed for up to 2.12
R59 (5)  LITTELFUSE 05+ Two Fully Independent Diodes Ceramic Fully Insulated Package (VISOL = 25
R5A (1)   Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-S
R5C (83)  RICOH STK 2004+ Furthermore, this circuit block compares the input signal to a threshold,
R5D (2)  Input Specifications Voltage range Filter Isolation Specifications Rat
R5E (2)   C 512 Kbytes on-chip flash memory single   voltage with erase/
R5F (233)  renes renes dc02 In addition to performing basic instruction execution, the CPU32+ also pr
R5J (1)  ZILOG PLCC 4 Transmit queues with optional priority levels 4K VCCs maximum ** AAL5
R5R (1)  PCI command and byte enable bus: shared PCI command byte enable bus, dur
R5S (6)  RENESAS QFP 0639+ Packaged in the SOD523 package this addition to the Zetex Schottky diode
R5X (1)  Application of power to the R5XH/R5XH activates a Power On Reset Circui
R60 (83)  N/A 1.500 (38.10mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC
R61 (7)  TI 2008 LITERATURE FULFILLMENT:N. American Technical Support: 800−282−
R62 (12)  TEXAS DIP-40 N/A ‡ Stresses beyond those listed under absolute maximum ratings may c
R63 (8)  RICOH QFP48 9413 2. Latching relay In order to assure proper operating re- gardless of
R64 (4)  n SDTV/HDTV serial digital video standard compliant n Supports 270 Mbps
R65 (331)  DIP N/A NOTES: (a) For a dual device surface mounted on 25mm x 25mm FR4 PCB with
R66 (276)  Power supply input pin for VCC1. When using an external current boost tran
R67 (316)    The SY88713V low-power limiting post amplifier operates from a si
R68 (37)  CONEXANT QFP This device uses a two-step flash architecture to maintain low power co
R69 (7)  AMI PLCC dualoct received from the DQA/DQB data pins of the Channel to be loaded
R6K (1)  RESLSTORS Dual Speed CSMA/CD Engine (10 Mbps and 100 Mbps) Compliant with IEEE 802
R6V (1)  ST 05 The customer¢s voice sources are recorded sec- tion by section into
R-7 (6)  DIP DIP The AD1833A is a complete, high performance, single-chip, multichannel,
R70 (20)  HARRIS SOP-20P 05+ LOW QUIESCENT CURRENT: 300µA DESIGNED FOR RS-485 INTERFACE APPLI
R71 (41)  CONEXANT BGA The UCC3888 controller is optimized for use as an off-line, low power, lo
R72 (5)  EPSON QFP64 05+ Enables the associated DDR2 SDRAM command decoder when low and disables th
R73 (29)  EPSON SOP-24 04+ † NOTICE: Stresses above those listed under Absolute Maximum Rating
R74 (4)  PHILIPS DIP16 93 The load can see a voltage spike of up to 1 µs, the amount of time
R75 (19)  ST DIP 00+ Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
R76 (18)  05+ 8 SSOP-32   Please be aware that an important notice concerning availability,
R77 (4)  IOR QFN 05+ The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Rec
R78 (3)  ZILOG PLCC 1 For normal continuous operation. A higher Tj is allowed as an overload
R79 (5)  ALTERA The Fairchild Switch FSLV3245 provides 8-bits of high- speed CMOS bus s
R7L (1)  Connective units, called repeaters, spaced every eight cells, divide ea
R7W (1)  BOURNS 04+ Skyworks CX65105 Evaluation Board is used to test the performance of the
R-8 (1)  EPSON 06+ SOP The internal architecture is shown in Figure 1 Data paths are illustrate
R80 (111)  INT PGA 5. CPD is defined as the value of the internal equivalent capacitance whi
R81 (6)  IWASHIMA SMD20 94+ NOTES: 1. These parameters are determined by device characterization, bu
R82 (130)  arcotronics arcotronics dc02 of a program or erase operation can be detected and any error condition
R83 (2)  PHILIPS QFP 03/05+ The thermal path between the plastic package and the die is not as good a
R84 (18)  arco arco dc97 Reset Output. RESET is an active LOW, open drain output which goes active
R85 (42)  EPSON SOJ 03+/04   Motorola's R8563 series sensor integrates on-chip, bipolar op amp
R86 (6)  SEI 01+ NOTE: Absolute maximum ratings are limiting values, to be applied individ
R87 (10)  INT WLCC44 Write Control (WC). This input signal is useful for protecting the entir
R88 (24)  RDC QFP QFP Instructions, addresses and write data are clocked into the DI pin on t
R89 (14)  VB: Supplies power to all circuits of the regulator except the output pow
R8A (15)  • An RF signal generator capable of delivering -10dBm   of out
R8J (14)  BGA Exilim 05+
R8M (1)  ATMEL PLCC Notes: (1) ISR-will operate down to no load with reduced specifications.
R8T (2)  RESLSTORS  Over voltage recovery (1) Ideal input span, does not include gain
R9- (1)    The R9-22A/FW/FT is a high-performance CMOS octal D-type flip-flo
R90 (7)  IR 07+ The LP2950 and LP2951 are low power voltage regulators. These devices are
R91 (2)  STM DIP 01+ The information in this sheet has been carefully reviewed and is believed
R92 (17)  N/A   The zener is tested using a pulse method and is designed for trans
R93 (4)  05+ 16 BGA For applications that demand high performance, a low cost micro-controll
R94 (9)  mot mot dc77+ DQP[A:D]. In addition, the address for the subsequent access (Read/Write
R95 (3)  0 0 Notes: 1. Dominant Wavelength, ëd, is derived from the CIE Chromatic
R96 (51)  MEXICO QFP 1993 The FM1233A features a highly accurate voltage reference to which VCC is
R97 (3)  SSOJ This product has been designed to meet the extreme test conditions and env
R98 (9)  RTC SOP 03+/04+ Multi-channel video distribution Video switching and routing High-spee
R99 (10)  ST SMD 05+ MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to t
R9S (1)  SYM=POWMOSN .SUBCKT 501N16A 10 20 30 * TERMINALS: D G S * 500 Volt 16 A
R-A (1)    36V to 72V power supply capable of providing up   to 6A 
RA- (36)  • Instruction set to optimize controller applications   Rich
RA. (1)  9644 40 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY   fmax = 200 MHz Max
RA0 (61)  LGS SOP SOP The DS15433 constantly monitors the battery voltage of the internal batte
RA1 (39)  TO-23 02+ DESCRIPTION The 74AC257 is an advanced high-speed CMOS QUAD 2-CHANNEL
RA2 (31)  N/A N/A N/A DESCRIPTION The HCC40192B, HCC40193B, (extended tem- perature range) an
RA3 (46)  SHARP TQ220 00+ 32 Mbit Am29DL32x devices had a larger SecSi Sector. Factory locked parts
RA4 (37)  TAKAMISA RELAY 06+ The Infineon single mode ATM transceiver complies with the ATM Forums Net
RA5 (19)  FAIRCHILD SOP-7.2-24P 6+ The TCMD10.. Series consist of a photodarlington optically coupled to a
RA6 (18)  Computer-Operating Properly (COP) watchdog timer External interrupts vi
RA7 (18)  • Square RBSOA • Low Saturation Voltage • Less Total P
RA8 (33)  NSC 2008 Write Enable (WEN) When VCC is applied to the part it powers up in the W
RA9 (21)  Raytheon 9030 Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is
RAA (5)  HOSONIC SOP 9801 APPLICATION The DS55107 DS75107 dual line circuits are designed spe- ci
RAB (7)  SMT 07+ 5000 HY57V641620HG is offering fully synchronous operation referenced to a posi
RAC (123)  N/A 1206X4
RAD (29)  N/A N/A 04+ • Pin and functionally compatible to ST16C2550,   software comp
RAF (5)  NATIONAL 03+ The bq2060 supports the smart bat- tery data (SBData) commands and charg
RAG (12)  15 RAGE OO Figure 2 shows the basic transmission specification. To begin and end a
RAH (3)  The LM26 is a precision, single digital-output, low-power thermostat co
RAI (4)  PROMISE 0011+ Maximum ratings are those values beyond which device damage can occur. Ma
RAK (1)  These N-Channel enhancement mode power field effect transistors are produ
RAL (25)  92 Test Circuit The circuit shown in Figure 10 is used for 100% RF testing
RAM (27)  MINI 08+ The gm3110 device is an all-in-one image processor targeted on LCD monito
RAN (4)  SG 2008 Bidirectional 3-bit input/output port. Software in- structions determine
RAO (4)  N/A SOP N/A   DigitalClarity™ Image sensor technology   High frame ra
RAP (9)  Switchcraft 0306 An on-chip Peripheral Data Controller (PDC) transfers data between the on
RAR (2)  SOP 00   LIFE SUPPORT POLICY Integrated Device Technology's products are
RAS (14)  MOT 03+ PLCC52 HY5V28C(L)F is offering fully synchronous operation referenced to a positi
RAT (2)  Under normal operation there are four internal frequency sources that may
RAU (1)  KEC SOT-423 † Package drawings, standard packing quantities, thermal data, symb
RAV (14)  OKAYA The CY7B951 provides the necessary clock and data recovery function to
RAW (1)  3极管 07+
RAY (23)  FAIRCHILD 01+ (4) The products and product specifications described in this book are su
RAZ (1) 
RB- (23)  . The Microchip Technology Inc. 93AA46/56/66 are 1K, 2K and 4K low voltag
RB/ (2) 
RB0 (104)  ROHM SOP 06+ NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies
RB1 (105)  ROHM 04+ The maximum AGC (analog gain control) and DGC (digital gain control) gain
RB2 (22)  03+ QFP Hynix HYMD132G725A(L)4-K/H/L series is registered 184-pin double data rate
RB3 (3)  TAIWAN 08+ 15 hp (11 kW) power output 380 - 480V AC; 50/60Hz 3-phase rectifier brid
RB4 (139)  ROHM 98 (1) Stresses in excess of those listed above may result in permanent dama
RB5 (153)  TAIWAN S0D-323 05+ • Solid state potentiometer • 2-wire serial interface •
RB6 (4)  S/PHI CDIP24 —— Note 1: The SOIC package used is thermally enhanced through the use of a
RB7 (104)  ROHM SOT163-D3P PB-FREE 06+ The SPI compatible serial interface also features the ability, using the
RB8 (37)  int int dc22 Bild / Fig. 9 Grenzstrom je Zweig IT(OV)M. Belastung aus Leerlauf, VRM =
RB9 (7)  TO-252 2. Application   PFC circuit(current continuous mode)   This
RBA (63)  KOA 06+ Pulse loading: The capacitors charged which unsinusoidal voltage pulses
RBB (40)  N/A SONY 04+ Parameter POWER REQUIREMENTS   VCC   VDD   VSS  
RBC (4)  KYOCERA 05+ OSD - Muestra en la pantalla el nmero del canal, el modo de sonido (MONO/
RBD (5)  N/A SONY 04+ Upon shipment, pages 0 and 7 are loaded with a unique 32-bit serial num
RBE (8)  The RBE05DHFR microcontroller features a direct connection to off-chip me
RBG (2)  Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATING
RBH (4)  HV 2007 5 V Tolerant Inputs TTL Compatible Outputs High Bandwidth Burst Bus 3
RBL (8)  IR SOT22 01+ Note 13: Skew is defined as the absolute value of the difference between
RBO (9)  STM D2PAK 07 An internal PMOS pass transistor allows the low 135µA supply curren
RBP (6)  LUCENT 00+ BGA3535 The functions for this block are: 1. Decode the internal address bus to
RBR (129)  kelvin kelvin dc73+
RBS (1)  • Selectable watchdog timer • Low VCC detection and reset ass
RBT (12)  SIE DIP-6 Notes: 7. The luminous intensity, I V, is measured at the peak of the sp
RBU (13)  s Programmable MAC Interface supports most   standard 7 signal MAC
RBV (28)  DIP4 07+ With performance of up to 900 million floating-point operations per secon
RBW (1)  LINEAR SOT23-5 05+ These devices are sometimes soldered to a small light- weight heat fin t
RBX (2)  KOA 810 If the auto-increment flag (AI) is set, the four low order bits of the C
RC- (331)  SOP 04+ • International standard package   JEDEC TO-247 AD • H
RC/ (2) 
RC0 (2659)  YAGEO 168630 Small Size Surface Mount DPAK Package Passivated Die for Reliability an
RC1 (1447)  yageo yageo dc02 The RC1206FR07215K and RC1206FR07215K have 150MHz of unity-gain bandwidt
RC2 (1080)  N/A • C compiler optimized architecture:   - Optional extended in
RC3 (330)  yageo yageo dc03 Low ON-State Resistance (10 Ω) Control Inputs Are 5-V Tolerant Low
RC4 (285)  N/A N/A N/A Note 5: Timing specifications are sample tested at +25C to ensure complian
RC5 (196)  RICOH BGA8*8 05+ Data file management software Flash Translation Layer (FTL) provides data
RC6 (62)  Note 3 The HALT mode will stop CKI from oscillatng Test conditions All in
RC7 (84)  03 The serializer outputs (DO) can drive point-to-point connections or limit
RC8 (57)  FAIRCHILD 2007 RC8170 RC8170 RC8170 RC8170 RC8170 RC8170 RC8170 RC8170 RC8170 RC
RC9 (48)  RAYTHEON 1780 Notes:   1. Permanent device damage may occur if the above Absolute
RCA (124)  N/A 0402X4 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFER
RCB (6)  coilmaster coilmaster dc04 These devices can be used as two 8-bit transceivers or one 16-bit transce
RCC (75)  a.b. a.b. dc79+ Notes: 1. For max. or min. conditions, use appropriate value specified u
RCD (36)  ST SSOP/20 01+ Fully compliant with SCSIC1, Fast SCSI and Ultra SCSI Backward compat
RCE (17)  KOA 05+ Figure 4 is the complete schematic diagram of the OTA. The OTA employs
RCF (11)  a.b. a.b. dc78+ FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update
RCG (6)  MuRata 4X4-1K The HY51V(S)16160HG/HGL is the new generation dynamic RAM organized 1,048,
RCH (61)  JAT 5M-270M The driver controls the gate voltage of the power switch. To limit large
RCI (71)  N/A SMDI will provide the detailed layout (AutoCad format) to users wishing t
RCJ (4)  dc04 LOOPBACK Mode Control. TTL/CMOS control input. LOOPBACK is an active HIGH
RCK (4)  INMOS . immunity and stable output. The device is designed to interface directl
RCL (121)  IC SOP • Excellent Appearance • Slim Font Design • Mitered
RCM (33)  SANYO 05+ A device that acknowledges must pull down the SDA line during the ackno
RCN (27)  2008   The MC74HC245A is identical in pinout to the LS245. The device in
RCO (7)  FAIRCHILD 153 TRI-STATE is a registered trademark of National Semiconductor Corporation
RCP (29)  ALPS 1210-10K Description: These diodes are designed for high volume requirements of FM
RCQ (1)  This product is intended for clock generation. It has low output jitter
RCR (613)  ALLEN BRADLEY 9335 The (+)Sense pin allows the regulator to compensate for limited amounts
RCS (13)  N/A Beneficial comments (recommendations, additions, deletions) and any pertin
RCT (105)  N/A Power Dissipation and Thermal Characteristics   Maximum Power Dissi
RCU (6)  K0A SOT   Notes (1) All characteristics of the receiver in this specificatio
RCV (151)  ROCKWELL Control signals for the I/O cell registers are generated using an extra
RCW (37)  N/A
RCX (11)  The Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced
RCY (6)  C Seven 16-KB blocks Auto Erase (chip & block) and Auto Program C
RCZ (2)  SAG LL34 05+ • LDO with Integrated Microcontroller Reset   Monitor Function
RD- (14)  NANA Stresses beyond those listed under "absolute maximum ratings" m
RD0 (24)  三菱 Over recommended operating free-air temperature range at −40C to +8
RD1 (502)  NEC 0805-10V 05+NOPB Stresses beyond those listed under "absolute maximum ratings" m
RD2 (408)  NEC SOT23-20V-201 The GND terminals of the ISL6537A provide the return path for the VTT LDO
RD3 (402)  NEC 89 • HiPerFREDTM diode   - fast reverse recovery   - low op
RD4 (212)  NEC/433/23 04+/05+ For Literature Requests Only: Freescale Semiconductor Literature Distrib
RD5 (211)  NEC 89 design, characterization and correlation with statistical process control
RD6 (151)  NEC The chip-erase mode can be initiated by a six-byte command sequence. After
RD7 (71)  NEC 1W-7.5V 04+ This pin is the system ground for the NCP5008/NCP5009 and carries both th
RD8 (77)  NEC 0603-8.2V A 1% resistor must be connected between this pin and GND (pin 1) to set t
RD9 (69)  NEC 23 The IA21140AF is a "plug-and-play" drop-in replacement for the
RDA (10)  N/A 0603X510P8R The error band which is guaranteed with the AD581 is the maximum deviati
RDB (4)  KOA SSOP/24 00+   The IDT70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Sta
RDC (46)  AD 模块25 The frequency of the on-chip VCXO is adjusted by an external control vo
RDD (37)  LSI SOP 9437 The SO-8 has been modified through a customized leadframe for enhanced
RDE (11)  INTEL BGA 0316+ Low-power, high-speed CMOS EPROM technology Fully static design Wide-o
RDF (18)  making use of a multiple Data Memory buffer technique where input channels
RDG (1)  The SCSI bus DIFSENS signal line is used to identify which types of SCS
RDH (1)  The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Module
RDI (3)  N/A SOT-89 A/D (Y and composite) reference voltage high-level input A/D (Y and com
RDL (1)  Hynix HYMD212G726(L)S4-K/H/L series is registered 184-pin double data rate
RDM (1) 
RDN (7)  ROHM 04+ The DSP56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter
RDP (2)  AMI 03+ RDP101878 uses Pulse Frequency Modulation (PFM) regula- tion. Typical o
RDQ (1)  Writing to the device is accomplished by taking Chip Enable (CE) and Wri
RDR (2)  NINTENDO TSOP 98+ Notes: 1. Stresses above those listed under Absolute Maximum Ratings may
RDS (51)  KOA If the FIFO is configured to have two write enables, when Write Enable (
RDT (1)  PMI DIP 98+ Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
RDU (5)  43 O4 at its data outputs and the voltages tolerated at its data inputs to the
RDV (3)  0 0 Number of channels: 6 (8/16-bit 6 channels) PPG operation of 8-bit or
RDX (3)  ROHM SOP 05+ PAGE WRITE: The page write operation of the AT28C010-12DK allows 1 to 128
RDZ (3)  ROHM 12000 07+ 1. The standby on a PT6700 series regulator must be controlled   wi
R-E (1)  .   The NJU6673 is a 25-common x 100-segment bit map LCD driver to dis
RE- (19)  PULSE 1996 Programmable up to 60 fps Programmable up to 150 fps 10-bit, on-chip 1.
RE0 (22)  schrack schrack dc93 Lead Temperature (1.6mm or 1/16-inch from case for 10s)+260C (1) Stresse
RE1 (40)  N/A QFP 99+ The R-C values are selected by matching the time constants of the R-C c
RE2 (59)  NSICERA All parameters specified at TA = -40C to +85C unless otherwise noted. Th
RE3 (31)  KEC 00+ NOTE 1: Maximum power dissipation is a function of TJ(max), JA, and TA. T
RE4 (21)  RSE DIP16 99+ Programmable versions of the PT6700 and PT6720 series of Excalibur ISRs
RE5 (78)  SOT-89 • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) • Optim
RE6 (9)  The TPS793xx family of low-dropout (LDO) low-power linear voltage regul
RE7 (7)  Receiver Pair Differential data from external transformers RD pair. Tran
RE9 (6)  SCHRACK RELAY 06+   3.4 Interface requirements and physical dimensions. The interface
REA (12)  lelon lelon dc04   Main CLK(Hz)Under 3.58M7.16M10.74M14.3M   Operating Voltage(m
REB (8)  92 Every FRC remote control project contains three separate CAD sections, pro
REC (27)  RECOM 06+ format along with start, stop and optional parity bus. The TPUART will si
RED (43)  HAR 07+/08+ The signal from the OR array can be fed directly to the output pin (combi
REE (6)  Input Frequency Output Clock Rise Time Output Clock Fall Time Output Cl
REF (967)  ADA 0411 Supply Current 1 Supply Current 2 R Output Voltage G Output Voltage B
REG (631)  TI SOT23-5 05+ This block reads/writes configuration data from the host bus to the AC97
REH (3)  The amplifiers can operate on any supply voltage from 4V (2V) to 33V (1
REI (4)  20 SANYO 9926 s 4 channel UART s 5 V, 3.3 V and 2.5 V operation s Pin compatible with
REJ (23)  FSC 05+ DIP-6 There are two alternatives to set the boot block. Either 16K-byte or 64K-b
REK (3)  ST SOP The information herein is given to describe certain components and shall
REL (41)  MITEL 05+▲▲ The HAL 805 is a recent member of the Micronas fam- ily of programmable
REM (20)  SOP The MAX5893 programmable interpolating, modulating, 500Msps, dual digital
REN (5)  3.9mm 01+ +15V - is the low voltage supply for all the internal logic and isolated
REP (129)  2005 Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and 2.5-V Fixed-Output and Adjust
REQ (1)  Output write current pulses are enabled when a high is applied to the WEN
RER (41)  DL 06+/07+   The CS5204−x family of linear regulators provides fixed or
RES (118)  N/A   LimitsSymbol Rever voltage (repetitive peak)30VRM Reverse voltag
RET (8)  Common-mode transient immunity is the maximum common-mode voltage slew ra
REU (7)  Raychem? 2. Memory Address Expansion The VP-1000A's internal 15-bit address count
REV (21)  N/A SMD 98+   Footprint compatibility in common packages within   the XC52
REX (6)  ST BGA N/A Digital Pixel Inputs These pins accept digital pixel data streams with ei
REY (1)  16-bit right justified 18-bit right justified 20-bit right justified 22
REZ (2)  Fault protection is provided by an output overvoltage comparator and opti
RF- (38)  UJU ELECTRONICS 05+   Variations on this circuit could easily be made Simply by revers
RF0 (45)  MIC SOP 05+ The HYM71V751601 H-Series are Dual In-line Memory Modules suitable for eas
RF1 (237)  high-frequency tube DEI 04+ Virtex devices feature a flexible, regular architecture that comprises
RF2 (560)  N/A N/A N/A • Cost-effective programming changes and   field software upgr
RF3 (164)  GA IWAKI N/A   As the beams attached to the central mass move, the distance from
RF4 (9)  AD 06+/07+ Xilinx development software (XEPLD) supports all mem- bers of XC7300 fa
RF5 (164)  RF SOP-8 Composite Video Output A 75 Ω termination resistor with short trace
RF6 (28)  BGA devastating effect is that, in the smaller crystal, undesired vibration
RF7 (20)  RFMD? BGA? 06+ If the accumulated value exceeds 1/3200 kWh, an external signal is gene
RF8 (3)  TI SSOP-20 Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input(4)
RF9 (85)  RF SMD 99+ MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which ca
RFA (10)  NO TO-247 01+ † Stresses beyond those listed under absolute maximum ratings may c
RFB (67)  N/A 12-CHANNEL GAMMA CORRECTION 10-BIT RESOLUTION DOUBLE-BUFFERED DAC REGIST
RFC (11)  N/A    Maxim evaluates pressure pot stress from every assembly proc
RFD (170)  HARRIS/FAIRCHILD TO The LTC®3416 is a high efficiency monolithic synchro- nous, step-down
RFE (3)  AD SOP8 04+   The one-time PROM product is capable of writing only once and is e
RFF (21)  PMI The internal bandgap reference is trimmed to 1.3 V 30 mV. This is used
RFG (36)  FAIRCHILD TO-3P 05+ 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 t
RFH (25)  FAIFCHILD TO-3P 04+   Vth can be expressed as voltage between gate and source when low o
RFI (37)  99 NORTH AMERICA Literature Fulfillment:  Literature Distribution Cent
RFJ (1)  SSM (LX)high-frequency Wiper position is maintained in the absence of power. This is accomplished
RFK (13)  MOT/ON TO-3 07+ Ring Command - A low active TTL - Compatible logic input. When enabled, t
RFL (45)  QUALCOMM QFN 05+ • A/D converter   • 10-bit resolution. 10 channels  
RFM (78)  MOT/ON TO-3 07+   The sensor can operate in three interface modes: master, snapshot
RFN (2)  MTI 06-07+ AC bandwidth is independent of voltage gain Inherently unity-gain stabi
RFO (3)  TOS RevisedSeptember 1, 2004 Preliminary - Filled out Package type(54ball FBG
RFP (260)  FAIRCHILD TO-220 05+ A linear voltage regulator can be broken down into four essential buildin
RFQ (3)  MYGIRL DIP22 Case: JEDEC DO-214AA molded plastic body Terminals: Solder plated, solder
RFR (76)  - 612 • Quad channel transceiver for 195 to 1500 MBaud serial   sig
RFS (19)  ANADIGIC The receive part is designed for a double conversion architecture. The in
RFT (91)  If an analysis is done of this (which is beyond the scope of this paper)
RFU (2)  PHILIPS QFP0505-32 00+ • Direct, indirect and relative addressing modes for   data a
RFV (1)  Intersil 06+ BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectiv
RFW (8)  QFN-28 06 Equivalent input rise time bandwidth assumes a first-order input response
RFX (11)  ROCKWELL 97+ High-end embedded control applications demand more performance from their
RFY (1)  TA = 0C to 70C / -25C to 85C (E) / -40C to 85C (I), unless otherwise spec
RFZ (2)  NOTE: The 100-µF capacitor has: ESL = 3 nH and ESR = 0.5 Ω to
R-G (1)  These three terminal positive regulators are supplied in hermetically sea
RG0 (5)  SMD Note that neither product term sharing nor product term steering have a
RG1 (30)  Highest sustained bandwidth per DRAM device • 8000/6400/4800 MB/s
RG2 (22)  N/A Features:   Operates from 2.4V to 26V supply voltage with reverse v
RG3 (9)  gi n/a Rev. A Information furnished by Analog Devices is believed to be accurat
RG4 (9)  Note 4 The M1 and M2 threshold specifications are normally referenced to
RG5 (2)  VIO AXIAL 6 nation for the bus as follows. If the DIFSENS signal is below 0.5V, the
RG6 (2)  RAY 扁平 陶封 This circuit consists of two independent, high gain, internally frequen
RG7 (2)  INTEL BGA 0224 RF output and bias pin. Biasing is accomplished with an external series
RG8 (221)  Jack(Available) • Process Technology: Poly Load • Organization: 64Kx8 •
RG9 (1)  WRITE RG90-18/50ODE The RG90-18/50/35Y is in the Write RG90-18/50ode whe
RGA (6)  N/A Include 6.8uF tantalum and 0.1uF ceramic capacitors on both positive and
RGB (7)  N/A   (Reset) - The RST pin functions as a microprocessor reset signa
RGC (36)  N/A • Single 3.3V0.3V power supply • All device pins are LVTTL co
RGD (1) 
RGE (76)  RAYCHEM . 06+ The operation mode of the M5M51008C series are determined by a combinati
RGF (26)  ZOWIE SMA 05+  fOSC(tc)Oscillator frequency over line and temperature Trimmed for
RGH (2)  I Dual-Mode Pin. Cascaded C The first device in the daisy chain will have
RGL (84)  Vishay DO-213AA 08+ NOTE: EP circuits are designed to meet the DC specifications shown in the
RGM (7)  ZOWIE 二极 1808 04+ The HC688 and HCT688 are 8-bit magnitude comparators designed for use i
RGO (1)  5 ON NOTES:   1. Dimensions are in inches.   2. Metric equivalents
RGP (134)  GS N/A DIP Notes:  1. An initial pause of 200 µs is required after power
RGR (2)  NATIONAL SOT23-3 03+ Hynix HYMD564646(L)8-K/H/L series is unbuffered 184-pin double data rate
RGS (9)  INTEL 02+ BGA Hidden refresh can be performed while maintaining valid data at the outpu
RGT (4)  94+ 485 二脚 • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V p
RGU (1)  The SRAM will meet any functional or electrical specifica- tion after e
RGW (1)  TDK new 1) Worst case package. 2) Max number of outputs defined as (n). Data in
RH- (184)  SHARP SQFP128 2007+   SymbolParameter L3000N HIGH VOLTAGE   Rth j-caseThermal Resi
RH. (1)  In addition to determining the off time during a fault condition, the sof
RH/ (1)  High Power Switching Regulator Controller for DDR Memory Termination VOU
RH0 (387)  ALPS 4X4-220K 05+
RH1 (50)  MITSUBISHI SOP SS (Pin 10): Soft Start. Connect a capacitor (CSS) from this pin to groun
RH2 (34)  MITSUBISHI SOP † Stresses beyond those listed under absolute maximum ratings may c
RH3 (14)  MITSUBISHI SOP These three terminal negative regulators are supplied in hermetically sea
RH4 (52)  NEC DIP N/A
RH5 (1083)  RICOH SOT89 05+ The Sidac is a silicon bilateral voltage triggered switch with greater p
RH6 (15)  HAN RUN SMD 2 The TLE 6225 G is a quad channel low-side switch with four power DMOS sta
RH7 (10)  N/A To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the
RH8 (99)  INTEL 01+ 26 The MAX3275/MAX3277 transimpedance amplifiers provide a compact low-power
RHA (8)  NEC DIP 04+ SS (Pin 10): Soft Start. Connect a capacitor (CSS) from this pin to groun
RHD (7)  ROHM 6000 07+ • Supports All Fibre Channel   Topologies; Arbitrated Loop &
RHE (32)  RAYCHEM RAYCHEM 08+ Note 5 The shortest allowable SK clock period e 1 fSK (as shown under the
RHF (1)  ECOS1CA682AA ECOS1CA822AA ECOS1CA103AA ECOS1CA332BL ECOS1CA332BA ECOS
RHI (11)  RHI DIP 06+ Ferrite Beads, Fair Rite 0.6 C 4.5 pF Variable Capacitors, Johanson Gig
RHK (4)  ROHM SOT-23 07NOPB The Inhibit pin is an open-collector/drain-negative logic input that is r
RHL (1)  The HYS64D128020GBDL are industry standard 200-pin 8-byte Small Outline D
RHM (1)  13. LOCAL/DISTANT SELECTOR (L/D)   Press this button to select local
RHO (4)  9 ON • Integrated Adaptive Receive Equalization for optimal Clock and Dat
RHP (15)  SOT-89 ROHM 05+ When the output load exceeds the current-limit threshold or a short is pr
RHQ (1)  6 ON 32KB EEPROM memory Durable, stainless-steel iButton package Built-in mu
RHR (156)  FAIRC TO3P 05+ The output stages switch at half the oscillator frequency, in a push-pull
RHS (2)  Turn-On Time: In the circuit of Figure 1, turning Q1 on applies a low vol
RHT (1)  The TPS758xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage v
RHU (16)  ROHM SOT-323 05+pb Note 1: Over-temperature limits are guaranteed by design, not production
RHV (2)  These I²C-compatible electrically erasable pro- grammable memory (
RI- (128)  TI 07+ During steady-state operation for a typical switching cycle, the oscilla
RI0 (1)  recom recom dc01 The R-C values are selected by matching the time constants of the R-C c
RI1 (5)  1000 Bidirectional 4-bit input/output ports. Schmitt trigger input and CMOS ou
RI2 (41)  RI 05+ EXPANSION IN (XI)   This input is a dual-purpose pin. Expansion In (
RI3 (1)  1850 Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maxi
RI4 (5)  CONEXANT 00+ SOP8
RI8 (1)  DSC SOP18W 2007+ The On/Off Control (pin 3) may be used for remote on/off operation. As sho
RIA (38)  JAT 1206 05+ When redundant instructions such as LD A,#im and LD EA,#imm are used conse
RIB (3)  ST 02+ 354 The HYM71V75S3201 N-Series are Dual In-line Memory Modules suitable for ea
RIC (35)  JRC DIP-8P The Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,
RID (1)  Figure 3 describes the noise model for the non-inverting amplifier conf
RIE (1) 
RIF (8)  PICOR MLP 04+
RIG (1) 
RIJ (1)  02 A buffered output-enable (OE) input can be used to place the eight output
RIL (3)  VOUT: Regulated negative-output voltage. A single 4.7-µF capacitor
RIM (2)  IC SOP The device also features split output bank power supplies which enable
RIN (3)  A/N QFP-100 05   ¡In the absence of confirmation by device specification shee
RIO (4)  RIOH 06+ The UCC1800/1/2/3/4/5 family offers a variety of package options, tem- p
RIS (5)  8 MIMOS 99+ If the accumulated value exceeds 1/3200 kWh, an external signal is gene
RIT (5)  STSL SOP20 99+ Absolute Maximum Ratings indicate limits beyond which damage to the devic
RIV (28)  ST BGA 99+  Maximum terminal current is bounded by the maximum applied voltage
RIY (1)  The IC must be equipped with external RC circuitry to limit the voltage i
RIZ (1)  vishay vishay dc00 The RIZ332KAQCF0K is a CMORIZ332KAQCF0K chip optimized to handle all the
RJ- (22)  HARRIS . need very low flicker noise. The HSMS-285x is a family of zero bias de
RJ0 (81)  amp amp dc0452 ANALOG-TO-DIGITAL CONVERTER (including MUX and attenuators)   Total
RJ1 (26)  BERG 00+ These devices can be used as two 8-bit transceivers or one 16-bit trans
RJ2 (126)  SHARP DIP16(镜面) 0 NOTES: A. CL includes probe and jig capacitance.   B. All input pu
RJ3 (15)  5 RSDS INTERFACE WITH SKEW CONTROL This functional block transforms CMOS l
RJ4 (34)  DIP ROHM 88+ This device actually guarantees that digital output data will be valid f
RJ5 (10)  SOP8 00+  TAOperating free-air temperatureC55125C4085C NOTE 4: All unused in
RJ6 (2)  In the following application circuits: *1 : For heavy loading application
RJ7 (5)  XYZ The maximum value of the temperature coefficient of the span is minus 27%
RJ8 (88)  Intel PBGA3535 1. Laser trimming of both initial accuracy and temperature   coeffi
RJA (22)  • Clock   • Built-in PLL clock frequency multiplication
RJB (2)  rjb rjb dc04 Device erasure occurs by executing the erase command sequence. This initi
RJC (42)  KEMET ELE address, and I/O pins that permit independent, asynchronous access for re
RJE (22)  LT 04+ NOTES: 1. These parameters are determined by device characterization, but
RJF (34)  AMPHENOL 301  This IC is 1 chip driv er IC f or spindle motor and 5 channel actu
RJG (7)  DELTA SOP 512 The users software can invoke the Idle Mode When the microcontroller is
RJH (70)  ELNA 2008+ KEY1~KEY8 all function as trigger keys. By mask option, the HT812L0 provi
RJJ (9)  During the soft start and the time-out delay duration with the IC in its
RJK (23)  RENESAS TO-3P 05+ † Stresses beyond those listed under absolute maximum ratings may c
RJM (5)  RSTA/RSTB (Pins 6, 15): Card Socket. The RSTA/RSTB pins should be connect
RJN (8)  RFSEMI SOT-423 Serial Data Output. This allows a number of parts to be daisy-chained. By
RJP (16)  ROHM SOT-89 05+NOPB Capacitor Table Table 1 identifies the characteristics of capacitors fro
RJR (65)  CLKBs output originates from the cross point switch and goes through a pr
RJS (12)  Should the Buyer purchase or use a Samsung product for any such unintende
RJU (6)  07+ This link option selects the source of the CLKIN input. When this link i
RJW (2)  SONY 2001 When VCC falls below the VPFD threshold, the SRAM automatically write-pro
RK- (24)  TOS QFP 05+ G5131-25T21U G5131-26T21U G5131-27T21U G5131-28T21U G5131-29T21U G513
RK0 (16)  alps alps dc98 The CY7C133 (master) and CY7C143 (slave) consist of an array of 2K words
RK1 (49)  rosem rosem dc79+ Where transient overvoltage protection in ESD sensitive equipment is re
RK2 (4)  PHI 03+ SSOP-5.2-16P 1. For DC outputs, especially those resulting from fault condi-   t
RK3 (18)  ROHM 02+ 00+   The MC74HC1G14 is a high speed CMOS inverter with Schmitt−T
RK4 (12)  SANKEN DIP-2 The D-channel is primarily intended to carry signalling information for c
RK5 (1)  *Note: These are stress ratings only. Stresses exceeding the range specifi
RK7 (6035)  The serializer transmits serialized data and appended clock bits (10+2 bi
RK8 (53)  INTEL CPU PIII 1.26G 133MHz 512KB FC-PGA370 Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a
RK9 (2)  ROHM 2004 SOP Once set, SDP will remain active unless the disable command sequence is i
RKA (3)  The LTC®3713 is a high current, high efficiency synchro- nous buck sw
RKB (1)  ELLINK 00+ SOP † Stresses beyond those listed under absolute maximum ratings may c
RKC (12)  The RKC1/8B3 incorporates Nationals CompactRISC® CR16B core (a high
RKD (2)  N/A N/A N/A * All specs and applications shown above subject to change without prior
RKF (2)  KOA 1206 software developers, enabling the design of highly efficient and compac
RKH (3)  The RKH09950044680R can perform speech record and playback (sometimes call
RKJ (2)  ALPS SALE--STOCK!! 08/09+ NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp
RKL (19)  If the boot loader revision in the device is previous to V1.63 then in up
RKM (4)  ROHM 93 1450
RKP (3)  RENESAS SOT-723 Call Progress Monitor and Group Listening - Adjust the Loudspeaking ampl
RKS (11)  Operating Voltage Range Sleep Mode Supply Current Supply Current (Ave
RKT (7)  SIP14 98 HY57V561620B is offering fully synchronous operation referenced to a posit
RKV (9)  40000 HITACHI 05+ PARAMETER Collector-emitter voltage peak value Collector-emitter volta
RKZ (39) 
R-L (1)  Before a byte can be reprogrammed, the main memory block or parameter blo
RL- (32)  RENCO/SINEC 00+ 1. Introduction VV5404 and VV6404 are CIF format CMOS image sensors capa
RL0 (87)  N/A Stanford Microdevices RL0805FR-07R16 series is a high performance GaAs He
RL1 (98)  RL 07/08+ The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca
RL2 (129)  between the two supply inputs is + 8.0 volts while the minimum voltage
RL3 (50)  N/A N/A N/A Electrical & Optical Specifications Specifications (Min. and Max. va
RL4 (52)  ROHM 1808 Members of the Texas Instruments SCOPE ™ Family of Testability Produ
RL5 (134)  C-CUBE 2008 Refer to the MSM9888L/MSM9889L Data Sheet. If the timing diagrams descride
RL6 (11)  SHIMA The flag bit is a volatile bit. It can be used to determine if a r
RL7 (27)  N/A The final output of channel I is an index pulse PO which is generated
RL8 (12)  I/O port with Schmitt trigger input (P2.0C P2.3 only) or push-pull outp
RL9 (4)  SSS CAN10 In this mode, CS is inactive (high) between serial I/O CLOCK transfers an
RLA (3)  ROHM 05++ 圆柱 When High, this input holds the address counter reset and puts the DATA
RLB (41)  The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally
RLC (22)  1210 Warnhinweise Bauelemente können aufgrund techni- scher Erforderniss
RLD (28)  ROHM TSOP 05+ Electrical Characteristics / Ta=25C   Drain to Source Breakdown Vol
RLE (5)  N/A QFP 06+   VOUT Temperature Coefficient   DC Crosstalk2 REFERENCE INPUT
RLF (47)  N/A The CD54AC534/3A and CD54ACT534/3A are octal D-type, three-state, posit
RLG (4)  When the supply voltage is switched on, a power-on reset pulse is generat
RLI (5)  output is latched precisely at the logic level of D data input. Power d
RLK (1)  RLK 00+ Regardless of the condition of E, the outputs will go to the OFF or high-
RLL (2)  NPC 05+ 100% production tested at the specified temperature. 100% production te
RLM (3)  MOT DIP-8 99+ Note: Some revisions of this device may incorporate deviations from publi
RLN (2)  MTI 06-07+ PCI Controller Compatible with PCI 2.1 specification. Integrated PCI a
RLP (20)  Intersil 06+ RoHS revision 13.2.2003. Glass and High Temperature Solder Exemptions App
RLR (1255)  N/A N/A 04+ The RESET/OE and CE pins control the tri-state buffer on the DATA output
RLS (100)  ROHM 04+ Device programming is performed a byte/word at a time by executing the
RLT (1)  CAUTION: These devices are sensitive to electrostatic discharge; follow p
RLU (7)  TAIYO 1206-12R 05+  Preliminary product information describes products that are in deve
RLV (7)  This advanced BiCMOS design is pin compatible with the industry standard
RLX (1)  SOP-16 98+ Chip Erase is a six-bus cycle operation. The automatic erase begins on th
RLY (3)  02+ SOP Power supply pin and RF GND pin. When the device is operating, always appl
RLZ (673)  SMD ROHM 05+ • External components   • External host for initialization
RM- (10)  N/A 1206X5   Description Numeric, Right Hand DP Numeric, Left Hand DP Over
RM0 (370)  CONEXANT QFN 07+ These 8-bit latches feature 3-state outputs designed specifically for d
RM1 (568)  MITSUBISHI SOP   TOSHIBA continually is working to improve the quality and the reli
RM2 (198)  N/A Before valid data exchanges between the serializer and deserializer can r
RM3 (109)  N/A SMD Latch Enable (Pin 1)   Latch Enable Input. A low level on this inpu
RM4 (138)  CRAY DIP-8P 07+/08+ • Simplifies logic control of 115/240 VAC power • Zero
RM5 (240)  RM 06+ The information in this document is preliminary and subject to change. Th
RM6 (43)  QUALCOMM QFN In case of using R1 with different condition from the above, formula is as
RM7 (1114)  N/A N/A N/A High level of integration - only one power semiconductor module require
RM8 (28)  A 1µF (min) capacitor from Vout to ground is required. Then output
RM9 (29)  IR 01+ These octal bus transceivers are designed for asynchronous two-way comm
RMA (6)  N/A N/A N/A The Fairchild family of Star*Power FETs includes a series of devices in
RMB (23)  KST 08+ The ADC11DL066 is a dual, low power monolithic CMOS analog-to-digital c
RMC (2068)  N/A † Package drawings, standard packing quantities, thermal data, symb
RMD (6)  CTIS 2008 The ZR78L Series three terminal fixed positive voltage regulators featur
RME (8)  716 Note : 1. * : These pins are not used in this module. 2. Pins 44, 45, 47
RMF (13)  Ramaxel SOP 06+ The total value of the resistor chain should not exceed 250KΩ tota
RMG (1)  N/A N/A N/A A low-side driver with internal current limitation and thermal shutdown a
RMH (2)  93 SOP   This new very low dropout linear regulator reduces total power di
RMI (1)  The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be us
RMJ (5)  TAIYO . 09+   The MSK 3554 is a pin compatible, low gain stable, drop-in replace
RMK (5)  ROHM SMD-8 00+ • Implements CCITT recommendations V.14 and   V.22 chapters 4.
RML (11)  0201c Mono-BTL Output Power   (RL = 8Ω, VDD = 3.0V, THD+N = 1%)410
RMM (5)  JYKJ SOP 06+ International Rectifiers R6 technology provides superior power MOSFETs
RMN (1)  SMD CHANNEL SELECT (F/R) Highest Logic Low Level Lowest Logic High Level
RMO (1)  The UCC3941 family of low input voltage single inductor boost converters
RMP (57)  1850 Note 4. Regulation is measured at constant junction temperature, using pu
RMR (2)  FAIRCHILD QFN16 04+ The OPA860 is a versatile monolithic component designed for wide-bandwi
RMS (54)  MINI 08+ Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Gene
RMT (22)  ZILOG DIP 00+   The absolute maximum ratings are values which must not individuall
RMU (78)  CTIS SOP/8 99+  IOLLow-level output currentVID = − 1 V,VOL = 1.5 V616mA &nbs
RMV (4)  SOP 96 There are a total of 16 global clock lines, with eight available per qua
RMW (2)  The LM27 is a precision, single digital-output, low-power thermostat co
RMX (1)  AMIS PQFP-160P 04+ • 1.5A minimum guaranteed output current • 500mV maximum dro
RN- (61)  ST 07+ International Rectifiers R6 technology provides superior power MOSFETs
RN0 (4)  This octal buffer or line driver is designed specifically to improve bo
RN1 (785)  TOSHIBA Switching frequency is set with an external capacitor, and the device can
RN2 (602)  angstrohm angstrohm dc76+   Two products are offered in the series with different output volt
RN3 (73)  angstrohm angstrohm dc80+ 4. In the case of CMOS Output Type: The time interval between the rising
RN4 (260)  angstrohm angstrohm dc72+ Positive analog supply pins. These pins should be connected to a quiet
RN5 (1792)  N/A N/A 04+ Note 1: All units are 100% production tested at TA = +25C. Limits over the
RN6 (339)  N/A N/A 04+ Capacitor Table Table 1-1 identifies the characteristics of capacitors f
RN7 (528)  N/A Hynix HYMD264646(L)8-K/H/L series is designed for high speed of up to 133M
RN8 (10)  To save pins without loosing speed, the TV-SAM is addressed serially usin
RNA (420)  03 Specifications are for the differential output (OUTA C OUTA or OUTB C OUTB
RNC (2293)  dale dale dc80+ NOTES: (1) Stresses above these ratings may cause permanent damage. Expo
RND (15)  Notes: 1. For Max. or Min. conditions, use appropriate value specified u
RNE (1)  roughly 1.25 V, well within the requirement of the NLAS44599. The other
RNF (19)  ST 07+ • CMOS Process Technology • 1M x 16 bit Organization •
RNG (2)  N/A Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less
RNI (1)  TOSHIBA SOT363 The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight p
RNK (4)  When the device is in current limit, there will be spurious oscil- latio
RNL (27)  vitrohm vitrohm dc96 The device contains two types of internal memory - data memory and connect
RNM (19)  N/A The time periods t1 (low) and t2 (high) are values that are easily read b
RNN (40)  dale dale dc80+ This device generates read instructions for the EEPROM. Read transactions
RNP (1)    In operation, the output transistor is OFF until the strength of t
RNR (871)  mepco mepco dc73+ Note 5: Junction-to-ambient thermal resistance is highly application and
RNS (27)  This combination of excellent dc performance with a common-mode input vol
RNT (6)  ROSENBERGER 08+ NOTE: Stresses greater than those listed under Absolute Maximum Ratings
RNV (43)  RICOH 05++ Stresses beyond those listed under absolute maximum ratings may cause pe
RNX (14)  MURATA Altera FLEX RNX002-01 devices are enhanced versions of FLEX 10K devices.
RNY (1)  N/A 08+  as Coss while VDS is rising from 0 to 80% VDSS. † Coss eff.
RO- (34)  The WP pin, in conjuction with a WPEN bit programmed HIGH, provides Har
RO1 (5)  RO QFP 0029+ Using CMOS construction, the quiescent current consumed by the MCP1726
RO2 (23)  RF MONOLITHICS INC 97 The voltage at the TOVER pin is equal to a logic-low level if the sensor
RO3 (3)  INTEL 02+ On-Off Control (Input): Logic low turns on all switches; logic high turns
RO4 (1)  All components of a charge pump, except the holding (bootstrap) capacit
RO8 (1)    The LVCC3245A is manufactured using advanced dual metal CMOS tech
ROA (1)  SAGEM 00+ 2350
ROB (2)  ROBOTIS QFP 00+ FEATURES 11 LDOs Optimized for Specific CDMA Subsystems 4 Backup LDOs f
ROC (7)  06+ SOP-8 This supplemental information applies to the GS816118/36T datasheet, which
ROD (2)  ph ph dc01   1.1 Scope. This specification covers the performance requirements
ROF (25)  ST PLCC32 2007+ 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of InternalOn-ChipDRAM
ROH (3)  23 NS 97 Literature Distribution Centers: USA: Motorola Literature Distribution;
ROK (9)  ERICSSON 01+ NOTE: Device will meet the specifications after thermal equilibrium has b
ROL (5)  NSC 2008 The CS4271s wide dynamic range, negligible distor- tion, and low noise ma
ROM (17)  TRAD Logic 0 Input Voltage (OUT = LO) Logic 1 Input Voltage (OUT = HI) ITRI
RON (45)  SYSTEM 9612+
ROP (215)  9841+ Notes: 1. Measurements at 900MHz were made using an ICM fixture with a do
ROR (1)  ROR SOP-8 N/A In encoding mode, audio data is input via the inte- grated A/D converte
ROS (80)  MINI 08+
ROT (1)  NS SOP-20 0018/SX Current Limit Response Timer: A capacitor connected between this pin and
ROU (2) 
ROV (56)  tyco tyco dc06 DigitalClarity CMOS Imaging Technology High frame rate Superior low-lig
ROX (1)  This product has been designed to meet the extreme test conditions and env
ROY (1)  DIP • Power-on Reset (POR), Power-up Timer (PWRT)   and Oscillato
RP- (5)  N/A DIP 95+ Inputs to VID D to A Converter Inputs to VID D to A Converter Connect
RP0 (19)  The simplest circuit is a simple op amp follower as shown in Fig- ure 3A
RP1 (67)  RF MONOLITHICS INC 97 The FAN7382 is a monolithic half-bridge gate driver IC for driving MOSFE
RP2 (22)  INTEL DIP 95+ Ground Rail. +3.3 Volt Power Supply. Serial data output stream. These st
RP3 (42)  GI 04+   The MI-MV13 is a 1280H x 1024V (1.31 megapixel) CMOS digital imag
RP4 (43)  schrack schrack dc90 Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circui
RP5 (53)  RICOH DIP 07+ The JAW050A and JAW075A Power Modules are dc-dc converters that operate o
RP6 (11)  schrack schrack dc88 WIDE x8 or x16 DATA BUS for HIGH BANDWIDTH SUPPLY VOLTAGE C VDD = VDDQ
RP7 (15)  schrack schrack dc00 The analog outputs of the RP710730 can be programmed to any one of 256
RP8 (30)  schrack schrack dc00 Command Line - Commands may be strung together in a single command line
RP9 (12)  schrack schrack dc93 − Glueless Interface to Asynchronous   Memories: SRAM and EPRO
RPA (3)  N/A 0402X2 Skyworks CX65105 Power Amplifier (PA) is a fully matched, 8-pin Leadless
RPB (1)  N/A 0402X2 We developed this new Type 1/1.8 5M-pixel CCD to respond to mar- ket dem
RPC (291)  N/A The AD8021 is not only technically superior, but also priced considerabl
RPD (6)  MINI 08+ The instruction and data caches operate independently from the rest of th
RPE (204)  murata murata dc99 need very low flicker noise. The HSMS-285x is a family of zero bias de
RPF (7)  RENESAS QFN 07+ Output clock data format C Controls the output clock (ODCK) format for ei
RPG (2)  „ Up to 64 general-purpose I/O pins (shared with on-chip  per
RPH (2)  schrack schrack dc93 In addition to the savings resulting from reduced parts count and circui
RPI (55)  ROHM JAT 05+NOPB Bidirectional I/O lines. Software instructions deter- mine the CMOS outp
RPL (1)  Hynix HYMD232M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence
RPM (119)  ROHM 06+ Supply voltage for the LNA, bias circuits, and control logic. External RF
RPN (15)   IC = 12 Adc, VCE = 5.0 Vdc  IC = 10 Adc, VCE = 5.0 Vdc Coll
RPO (1)  Description Clock input Gate for outputs Q1 through Q5. When G1 is LOW
RPP (4)  ROLAND 1599 05+ The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be us
RPQ (3)  MINI 08+   There are two limitations on the power handling ability of a tran
RPR (7)  ROHM 06+
RPS (6)  MINI 08+ Note 3: When the input voltage at any pin exceeds the power supplies (tha
RPT (40)  ROHM The CPU core can use on-chip rather than external   memory. This eli
RPU (5)  taiyo taiyo dc00 Agilent Part # and Options Commercial MIL-PRF-38534 Class H Standard
RPV (23)  The CY7C371 is a Flash erasable Complex Programmable Logic Device (CPLD)
RPW (9)  N/A 1020 code to stay in the device while data in the rest of the device is upda
RPX (2)  Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift
RQ- (4)  Hynix RQ-125B-K/H/L series is designed for high speed of up to 133MHz and
RQ0 (3)    2.2 Order of precedence. In the event of a conflict between the te
RQ1 (1)  SHARP 0222+ For applications requiring output voltage on/off control, the PT4120/414
RQ3 (1)  SamKen N/A DIP Table 1 through Table 3 show the various operations that are available on
RQ5 (71)  RICOH SOT-343 05+ SDA is a bidirectional pin used to transfer data into and out of the de
RQ8 (2)  SEEQ PLCC-20 06+ Note 2: Absolute Maximum Ratings indicate limits beyond which damage to t
RQA (5)  ROHM SMD-8 04+ The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-
RQC (1)  taiyo taiyo dc97 Note: Stresses greater than those listed under "Absolute Maximum Rat
RQD (2) 
RQG (3)  RENESAS 2900 07+ The basic unit of logic on the ispLSI 3320 device is the Twin Generic L
RQJ (7)  RENESAS 00+ If the duty cycle is to be varied over a small range about 50% only, the
RQK (7)  RENESAS 00+ An analog overcurrent detection circuitry is built into the ISP1521, whic
RQM (3)  MODULE MODULE Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output
RQS (1)  • Fast access time:   C 117, 100 MHz; 6 ns (83 MHz); •
RQW (4)  NTSC, PAL and SECAM composite video standards are interlaced video scheme
RR- (37)  TI The innovative design of the internal T/H assures an exceptionally wide 1
RR0 (134)  To allow for dc coupling to ADCs, its unique output common-mode control
RR1 (322)  N/A The Master begins a transmission by sending a START condition. The Mast
RR2 (16)  ROHM 05+ DC214 If the DPs are not required, then the connections shown in Table 2 can be
RR3 (6)  N/A The MCP6275s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 m
RR4 (2)  ALEPH CER-SOIC 00+ Texas Instruments and its subsidiaries (TI) reserve the right to make cha
RR5 (1)  The luma input is driven by either a low impedance source of 1VP-P or th
RR7 (1)  HF SOP The Hyundai HYM71V633201 H-Series are 32Mx64bits Synchronous DRAM Modules.
RRB (1)  TIMER - Le permite a Ud. marcar un horario especfico en el cual Ud. desea
RRC (12)  N/A The HYM72V64656H(L)T8 H-series are gold plated socket type Dual In-line Me
RRD (3)    ISB = 2 mA Fully asynchronous and simultaneous read and write ope
RRE (6)  FUJITSU 03+ SOP-8 The LNP has differential input and output capability and is strappable
RRH (1)  N/A DESCRIPTION HCF4020B is a monolithic integrated circuit fabricated in
RRL (9)  ∙ 2,097,152-word 8-bit configuration ∙ Single 5V power su
RRM (29)  KOA 03+ SOP Enables the associated DDR2 SDRAM command decoder when low and disables th
RRN (2)  WESTECH SOP 92+ The standard Xilinx Foundation Series™ and Alliance Series™
RRO (1)  † Stresses beyond those listed under absolute maximum ratings may c
RRR (1)  Features • The number of active dots: 1,456,000 (1.6-inch; 4.1cm in
RRS (5)  MOT 1996 TSSOP Quick Text-to-SI (T2SI) text entry to build noise robust SI recognition s
RRT (2)  I.1 - Setting the RRT113006 Application RRT113006 is a telephone set int
RRV (1)  Differential termination for Stratix devices is supported for the left an
RRX (2)  JAPAN QFP-64 Via the VCC input an external 5 V voltage regulator is continuously monit
RS- (235)  CITIZEN The CY7C68310 requires a 30-MHz signal to derive internal timing. Typical
RS0 (61)  VISHAY SOD-123 06+PB advanced circuit design to provide ultra-low active current. This is ide
RS1 (178)  RECTRON 07+   3.6 Certificate of compliance. For device classes Q and V, a certi
RS2 (225)  DIODES 05+ The VCS features the high peak current capability and low On- state volta
RS3 (144)  TSC DO214AC 05 The Hynix HYM76V4M635HGT6 Series are 4Mx64bits Synchronous DRAM Modules.
RS4 (87)  0402X4 The Master begins a transmission by sending a START condition. The Mast
RS5 (210)  台产 07+ The COP87L88GD/RD OTP (One Time Programmable) Family microcontrollers a
RS6 (47)  DIODES DO214AB 05 Small outline SO8 and TO92 style packages. No stabilising capacitor requ
RS7 (17)  N/A RQFP-100 98 The intended application of this device is for point to point baseband tr
RS8 (175)  0402X8 A typical multipoint application is shown in the above figure. Terminatin
RS9 (11)  RAYSON DIP16 Storage Temperature Junction Temperature Collector to Base Voltage Coll
RSA (28)  ROHM 08+ This family of CMOS analog switches offers low resistance switching per
RSB (47)  ROHM 12000 07+ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
RSC (14)  CUSTOMER N/A 98 1. 4-channel(4 Form A) of RF Photo- MOS Relays 2. SO package 16-pin type
RSD (7)  essors, but also eliminates bus contention in multiple bus microprocessor
RSE (12)  This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configurat
RSF (96)  ROHM   Composite type with an N-Channel Sillicon MOSFET unit : mm  
RSG (4)  hoku hoku dc04+ 12. Measured by the voltage drop between A and B pins at the indicated cu
RSH (16)  MITSUBSH 04+ The Control and Status Registers provide the user with a mechanism for
RSI (5)  In case of the spindle motor to repeat acceleration anddeceleration , the
RSJ (3)  05+ The TSOP344..SB1F - series are miniaturized receiv- ers for infrared re
RSK (2)  Differential output for the synthesizer. LVPECL interface levels. Active
RSL (14)  ROHM 07+/08+ In addition to parallel termination, SSTL-3 and SSTL-2 class II I/O stand
RSM (106)  07+ • 14-Bit (XRD9814) or 16-Bit (XRD9816)   A/D Converter •
RSN (69)  N/A sanyo 05+ The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, orga
RSO (5)  RFMs TX-series hybrid transmitters are specifically designed for short-ra
RSP (15)  BB QFP QFP 9.1 In no event shall DVSI be liable for any special, incidental, indirec
RSQ (12)  ROHM 07+/08+ The device provides ultrastable +4.500V output with 0.4500 mV (.01%) init
RSR (11)  ROHM SOT-23  Maximum terminal current is bounded by the maximum applied voltage
RSS (220)  JAT 05+ Notes:  1. TA is the instant on case temperature.  2. See the
RST (3)  TOKO Because the PMOS device behaves as a low-value resistor, the dropout volt
RSU (4)  ROHM SOT-323 0620nopb Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP#
RSW (3)  SOP-14 Mini-Circuits 03+ 100% TESTED FOR PARTIAL DISCHARGE ISO120: Rated 1500Vrms ISO121: Rated 3
RSX (21)  ROHM SOP 434   The K4S51163PF is 536,870,912 bits synchronous high data rate Dyn
RSZ (34)  ROHM 23-2.4v 05+   Ultra Low VF   1st in Marketplace with a 10 VR Schottky Recti
R-T (2)  SYMBIOS PLCC68 97+ The Hyundai HYM71V73C3201 N-Series are 32Mx72bits ECC Synchronous DRAM Mod
RT- (51)  LITEON The Hynix HYM71V32635AT8 Series are 32Mx64bits Synchronous DRAM Modules.
RT/ (1)  The device pins also have the ability to set outputs to fixed HIGH or L
RT0 (93)  RATO • Dual Marked with Device   Part Number and DSCC   Stan
RT1 (328)  MITSUBISHI SOT-523 05+ The HPR2XX Series uses advanced circuit design and packaging technology
RT2 (52)  CAN3pin 铁帽 金脚 322 To minimize noise, the analog and digital circuits in the ISD MicroTAD-1
RT3 (49)  MITSUBISHI SOT-353 • Single power supply: 5 V 10% • Full TTL compatibility R
RT4 (26)  94 The three transmitter operating modes C transmit ASK, transmit OOK, and p
RT5 (22)  BGA N/A   The UC62LV2008 is a high performance, very low power CMOS Static
RT6 (11)  RichTek The UCC383 family of low dropout linear (LDO) regulators provide a regula
RT7 (9)  CONEXANT 06+ 236 The LTC®4244/LTC4244-1 are Hot SwapTM controllers that allow a board
RT8 (57)  SOP 05+ Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In
RT9 (1279)  Richtek 01+ TO253/4   Data Bus, active High. In Word mode, these pins provide a 16-bit
RTA (17)  EPX Monitors two analog voltages or thermistor temperature   inputs On
RTB (16)  SCHRACK Relay(new original) * Antiparallel diode for high frequency   switching devices * Antis
RTC (269)  RTC QFP 00+   These phase detector outputs can be combined externally for a loo
RTD (46)  SCHRACK Relay(new original) Two different sections control the operation of the converter in either
RTE (59)  SCHRACK Relay(new original)   For more information on the PWP package, refer to TI technical bri
RTF (21)  ROHM 2008 153,000 Deviation Limiter In: Input to the on-chip deviation limiter. This input
RTG (21)  REALTEK DIP16 96+ Ground reference to LVDS and CMOS circuitry. For the LLP package, the D
RTH (27)    Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (t
RTI (10)  MITSUBISHI 23 To minimize noise, the analog and digital circuits in the ISD MicroTAD-1
RTK (3)  The offset voltage is trimmed on-chip to eliminate the need for external
RTL (252)  ROHM SOT-363 06+PB "with wake-up capability through INT0 pin" is removed. P-LCC-8
RTM (156)  REALTEK SSOP 06+ The CY7C4261/71/81/91V consists of an array of 16K, 32K, 64K, or 128K w
RTN (13)  ABCO 04+ Watchdog Timer The Watchdog Timer circuit monitors the microprocessor a
RTO (14)  VISHAY 00+ N/A   The MC10/100EP131 is a Quad Master−slaved D flip−flop
RTP (12)  MITSUBISHI SOT23 06+   There are two limitations on the power handling ability of a tran
RTQ (15)  ROHM SOT-163 05+NOPB 5k ESD damage can range from subtle performance degradation to complete devic
RTR (54)  TOKO原盘 SMD The ispLSI 2128VE is a High Density Programmable Logic Device available
RTS (150)  DIP • Separate Memory Banks by Address Space   C Simultaneous Re
RTT (9)  JAT SOT-153 05+ NOTES:2911 tbl 09 1. "X" in part numbers indicates power ratin
RTU (5)  ROHM SOT-323 05+PB A non-volatile marker is automatically inserted at the end of each record
RTV (8)  NEC 98+ 1450 Notes: 5. CX1 must be placed within 0.7 cm of the HSDL-3600 to obtain op
RTW (3)  N/A NSC 04+ The device operation is controlled by instructions from the host processo
RTX (28)  INTERSIL PLCC 00+ Data Line Pulsing: USB20H04 turns on its data line pull-up resistor (eithe
RTY (3)  This device contains protection circuitry to guard against damage due t
RTZ (2)  With up to 200 MHz bandwidth and 2 GS/s maximum sample rate, no other col
RU- (3)  SOP 05+ A tunable delay cell (controlled via CLKDACTRL) is integrated between the
RU0 (2)  A key component that follows the limiting amplifier in a receiver unit is
RU1 (9)  IR MLPM 04+ Neither time nor frequency are dependent on supply voltage, even though
RU2 (25)  ROHM SOT-143 The MPC7455 is the third implementation of the fourth generation (G4) mi
RU3 (18)  原装无铅 07/08+ Configured as an 8-Port M-LVDS Repeater − SN65MLVD128 2 LVTTL Rece
RU4 (21)  SANKEN DO-201 05+ 5 V, 3.3 V and 2.5 V operation Industrial temperature range After rese
RU5 (9)  CEM SMD 06+ Device erasure occurs by executing the erase com- mand sequence. This i
RU6 (16)  RICOH 2000
RU7 (1)    The NJU6673 is a 25-common x 100-segment bit map LCD driver to dis
RU8 (21)  INTEL QFP 1991 The components contained in Tables 2, 3, and 4 can be used to build typi
RU9 (5)  ROHM SOT-163 05+ The HC4015 consists of two identical, independent, 4-stage serial-input/
RUB (1)  Preformed Leads (SOD64 Packages) Some types of automatic insertion machi
RUD (4)  Each product in the FSDx321 (x for H, L) family consists of an integrat
RUE (91)  RAYCHEM . 06+ Package drawings, standard packing quantities, thermal data, symbolizatio
RUF (1)  PHILIPS 2008 The microprocessor can program the a8237 when the ncs input and the ain[
RUG (2)  N/A MODULE N/A Ground reference to LVDS and CMOS circuitry. For the LLP package, the D
RUM (1)  ROHM SOT-723 6.8 5% 7.5 5% 8.2 5% 9.1 5%  10 5%  11 5%  12
RUN (16)  AMI 00+ DIP-28 • Power-on Reset (POR) • Power-up Timer (PWRT) and  
RUR (267)  HARRIS TO-218 05+ Hynix HYMD216M726(L)6-K/H/L series incorporates SPD(serial presence detect
RUS (18)  KAIZEN QFP 97+ Test mode select. One of four terminals required by IEEE Standard 1149.1-
RUW (16)  ZILOG SOP 02+ Stresses above those listed under Absolute Maximum Ratings may cause pe
R-V (1)  HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates
RV- (25)  ELNA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t
RV1 (15)  83 In the 53 tap low pass filter mode, the GF9102A can replace the TMC2242 i
RV2 (61)  ELNA 5X5.3 05+ No External Components Required Internal Voltage Triplers Produce High Si
RV3 (16)  ELNA 4X5.3 05+ from Normal to Freerun. The Compare Circuit then measures the phase delay
RV4 (86)  RAYTHEON 06+ 500 ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operat
RV5 (38)  RICOH SSOP 01/P4 Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation
RV6 (23)  claro claro dc8902 The circuit of the TSOP22..YA1 is designed in that way that unexpected
RV8 (4)  REVOTEK SOJ 99+ • AC97 Rev 2.2 compatible stereo codec   - DAC SNR 94dB, THD C
RV9 (1)  Raytheon 04+ The Input/Output logic timing diagram is shown in figure 1. For proper ope
RVA (1)  MINI 08+ Output enable puts data outputs into high impedance state Easily expandab
RVB (5)  ELNA 4X5.3 05+  TAOperating free-air temperature−4085C NOTES: 4. VCCI is the
RVC (2)  These devices are fabricated using power-saving CMOS technology for high
RVD (1)  Caution: The BiCMOS inherent to the design of this component increases th
RVE (11)  0402c Use with 10 to 14-bit A/D converters 5 Megapixels/second minimum throughp
RVG (219)  MuRata 4X4-4.7K 05+ Outputs the extracted generic flow control bits (GFC) in a serial stream.
RVH (1)  elna elna dc99 AL,BL,CL - Are the lowside logic level digital inputs. These three input
RVI (4)  HIT 1990 DIP Fifth Generation HEXFETs from International Rectifier utilize advanced p
RVJ (12)  ELNA 2008+ The interface should be arranged to allow simple data transmission from t
RVK (1)  RST/VPP: Reset/Programming Supply Voltage: A low on this pin for two mac
RVL (5)  elna elna dc03 The charging sequence consists of four stages. The application of current
RVM (4)    FIGURE 5 Transfer Function Display Gain is displayed as the slope
RVP (2)  INTEL CPURVPXA271FC53121.8V256M336PIN Preliminary product information describes products which are in productio
RVR (5)  MURATA 4X4-10K 05+ format along with start, stop and optional parity bus. The TPUART will si
RVS (12)  ELNA 5X5.3 The self-timed write cycle includes an automatic erase- before-write ca
RVT (2)  95 NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Int
RVZ (4)  4 Integrated Switches: 2.4A Buck, 2.6A Boost, 0.35A Boost, 0.35A Inverter
RW- (7)  Guaranteed by design and characterization. Image rejection typically fall
RW0 (3)  1. The output optical power is compliant with IEC 60825-1 Amendment 2, Cla
RW1 (12)  recom recom dc0540 The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible l
RW2 (13)  CONEXANT QFP52L 2000+ The MAX4460/MAX4461/MAX4462 are instrumentation amplifiers with precision
RW3 (5)  Recommended operating conditions unless otherwise noted. Refer to Block D
RW4 (1)  Additionally, operations can be controlled by three methods: using chip s
RW5 (2)  <1mV/mA (see Figure 1) Low Crosstalk Between Switches Pin Compatible
RW6 (53)  dale dale dc77+ Bidirectional 8-bit input/output port. Software instructions determine the
RW7 (30)  dale dale dc77+ The FCT273 has eight edge-triggered D-type flip-flops with individual D
RW8 (4)    ICC1 and ICC3 are depedent on output loading and cycle rate. The s
RWA (4)  N/A QFP 98+ Note 3: Specifications over the C40C to 85C temperature range are assure
RWB (2)  TI 07+ † Stresses beyond those listed under absolute maximum ratings may c
RWC (5)  = 111, then all 4 bits are high. If TECH[2:0] = 001, then only bit 5 is h
RWD (2)  mands are provided to allow protection of some or all of the blocks and
RWH (3)  DETAILED FEATURES High Definition Programmable Features (720p/1080i) &n
RWK (2)  Senses motion of ring magnet targets Integrated filter capacitor
RWM (37)  The typical noise floor is 0.4 mg/ Hz allowing signals below 1milli-g to
RWN (1)  16 Channels 12-bit (4096 Steps) Grayscale PWM Control Dot Correction C
RWP (4)  Data Setup Time Data Hold Time Address Set-up Time Address Hold Tim
RWR (454)  dale dale dc80+ HIGH INDUCTIVE SWITCH-OFF OPERATION At the end of the last conduction ha
RWS (44)  LAMBDA Module N/A • Constant current and voltage charging • Charge disabling
RWT (6)  TOKO 91 Time timer and a Watchdog unit. The Real-Time Clock Tim- ing function c
RWW (1)  The IC is well suited for applications where small size, low cost, low au
RX- (35)  RSM DIP16 0602+ • External event interrupt control function   DTP/external int
RX0 (1)  The next four bytes of the EPROM STATUS memory contain the page address r
RX1 (14)  TOSHIBA DIP 1997 ADPCM Output Register The internal encoded parallel ADPCM data is loaded
RX2 (12)  RMC 943+ Input Channels 0-3 PECL/ECL differential signal inputs. Multiplexing of t
RX3 (34)  HIMARK SOP 00+ The RX3100A incorporates six basic functions of the Ethernet Transceive
RX4 (6)  These Intersil RS-485/RS-422 devices are ESD protected, fractional unit l
RX5 (7)  TAIWAN 04+ The RX55C133M1 is a receiver front-end for CDMA cellular applications,
RX6 (5)  RX DIP-18 1. By clocking each of the 256 row addresses (A0 through   A7) with
RX7 (3)  RAY 扁平 陶封14Pin 86 Note 10: For best long-term stability, any precision circuit will give be
RX8 (6)  ★Original and new, Special price! ★Original and new, Special price! 06+ The RM3283 consists of two analog ARINC 429 receivers which take differe
RX9 (1)  NS SOP-28 00-01+/SX • Function, pinout, and drive compatible with FCT and   F logi
RXA (2)  INTEL BGA 02+ Note 1: Limits are 100% production tested at TA = +25C. Limits over the op
RXB (6)  Output voltage set internally to 1.5% on SG7800A Input voltage range to 5
RXC (1)  Before entering the main metering routine, the firmware initializes its
RXD (7)  Footnotes: 1) Standard frequency stability (20,25,50ppm & others avai
RXE (119)  RAYCHEM . 06+ 5) Next, a heat sink with lower uSA than the one calcu-   lated in S
RXF (1)  Posistive excursions of input voltage may exceed the power supply level.
RXG (1)  DESCRIPTION The M74HC4094 is an high speed CMOS 8 BIT SIPO SHIFT LATCH
RXJ (3)  Note: Junction Temperature (TJ) is approximated by soaking the device un
RXL (2)  loop timing applications to assure PLL tracking, especially during GR-253
RXM (4)  This datasheet contains new product information. Anachip Corp. reserves th
RXT (20)  ROHM Note 5: For a power supply of 5V 10% the worst case output voltages (VOH,
RXZ (1)  grammer to identify the correct programming algorithm for the Atmel pro
RY- (18)  FUJITSU 3,599 This document is a general product description and is subject to change wi
RY0 (1)  the improvement in linearity of the transfer characteristic. Reduced inp
RY1 (22)  schrack schrack dc00 NanoStar and NanoFree Packages Supports 5-V VCC Operation
RY2 (19)  SCHRACK RELAY 06+ • Small, space-saving fuses provide a high degree of current-  
RY3 (10)  QMV PLCC The component placement around the LDO should be done carefully to achie
RY4 (7)  FUJ 02+ 4000 This family consists of two DC current regulators connected internally in
RY5 (13)  TYCO 5110 All 240xA devices offer at least one event manager module which has been
RY6 (6)  schrack schrack dc01 Nessuna parte del presente manuale pu essere riprodotta, trasmessa, trasc
RY7 (1)  ERICSSON SOP16W 06+ NOTES:   1. Dimensions are in inches.   2. Metric equivalents
RY8 (1)  SMD-8 03 04 The MGA-725M4 offers an integrated solution of LNA with adjustable IIP3
RY9 (5)  schrack schrack dc02 MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normal
RYA (4)  schrack schrack dc0419 The TLV246x is a family of low-power rail-to-rail input/output operationa
RYC (26)  TYCO 08+ The integrated 16 bit processor serves as a micro controller for USB perip
RYI (1)  The LVTH162244 devices are 16-bit buffers and line drivers designed for l
RYN (23)  ph ph dc89   The Header word is a 4 bit Manchester coded message 0110 or its co
RYR (3)  CAN3 The demo boards are designed to verify different features easily and qu
RYS (42)  schrack schrack dc93   Each channel consists of a TTL/CMOS-compatible logic input gated
RYT (149)  ERICSSON ++ CDIP24 Chip Center: X=0µm, Y=0µm Chip Size: X=7.54mm, Y=2.09mm Chip
RZ- (5)  The conditions at the binary-select inputs and the three enable inputs se
RZ0 (1)  RICOH TSOP-5.2-32P 6+ Using the RZ05MM002-0002amsung's proprietary digital phase-locked-loop tec
RZ1 (8)  QFP100 Package drawings, standard packing quantities, thermal data, symbolizatio
RZ2 (5)  SHARP CCD 01+ Data is written during a write or a read-modify-write cycle. Depending on
RZ5 (12)  RICOH TSOP/32 00+   The output is capable of supplying 200 mA to the load while confi
RZ7 (1)  RAY 91 LO IN=-4dBm See note 1 and 2. Mixer Preamp ON Mixer Preamp OFF Mixe
RZA (2)  2001 • Industrial applications for daisy chaining   multiple devic
RZB (86)  When the PCB trace between the clock output and the load is over 1 inch
RZC (10)  TDK new • The DAGs generate 24-bit addresses for data fetches from   t
RZD (2)  Reset (RSTN) C Used for testing and verification, the TTL   outputs
RZE (36)  This document is a general product description and is subject to change wi
RZS (1) 
RZT (4)  DIP   Data Bus, active High. In word mode, these pins provide a 16-bit
RZV (1)  The MC68SEC000 is a cost-effective static embedded processor engineered f
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