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  Mfg pack D/C Descrpion
K.3 (1)  Up to 12 DCM blocks are available. To generate de-skewed internal or ex
K00 (15)  SGS-THOMSON MSOP-8 03+ 2. The minimum load current is the minimum current required to maintain r
K01 (15)  Free PSoC "Tele-training" is available for beginners and taught
K02 (4)  SOP The K020X12B1E3 and K020X12B1E3 include a 110-Ω differential line
K03 (49)  SOT5 The Bt856/7 is designed specifically for video systems requiring th
K04 (12)  Trigger Voltage: The measured peak voltage across the ESD suppressor bef
K05 (5)  The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Rec
K06 (4)  Infineon 06+ TO-220 The waveform of the maximum DC applied voltage is flat. When a ripple vol
K07 (2)  Infineon 06+ TO-3P The M36L0R7050T0 and M36L0R7050B0 com- bine two memory devices in a Mul
K08 (4)  ST SON 05+ Full-field Image Sensor 3500 x 2300 Pixels Pixel 10 µm x 10 µ
K09 (3)  TECCOR 07+ Life Support Applications These NEC products are not intended for use i
K0S (1)  The DG308B/309B analog switches are highly improved versions of the ind
K0V (2)  PHILIPS PLCC44 06+ The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 5
K-1 (1)  N/A N/A N/A   The IDT71016 is a 1,048,576-bit high-speed Static RAM organized a
K10 (162)  TAIT 06+ 800 The Si3038 is an integrated direct access arrangement (DAA) chipset that
K11 (100)  HIT TO-3P 05+ VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signa
K12 (81)  TECCOR TO-220 04 Low power RS-485 systems Network hubs, bridges, and routers Point of
K13 (73)  TOSHIBA TO-220 The PCM1680 is a CMOS monolithic integrated circuit which features eigh
K14 (70)  Notes : 1. A Refriggerable one-shot multivibrator has an output pulse wid
K15 (92)  INFINEON TO-3P 04+ © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regis
K16 (54)  TOS/NEC/FUJI TO-220 04+ The state machine watches for transitions on RO. When a data-byte transf
K17 (38)  TO-92 Regular supply bypassing techniques are recommended. A 10µF capaci
K18 (25)  TECCOR The attached spice model describes the typical electrical characteristics
K19 (52)  NEC 00+ 2500 The external bootstrap capacitor is necessary to achieve the fastest gat
K1A (5)  KEC TO-92 99 Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee
K1C (1)  Input offset voltage is trimmed to less than 60µV. The low drift an
K1D (2)  This document is a general product description and is subject to change wi
K1F (1)   Typ. Max. UnitsConditions   CCC CCCVVGS = 0V, ID = -250µ
K1G (1)  The device supports low-power standby operation. When RESET is low, the d
K1K (4)  The LVTH16543 devices are 16-bit registered transceivers designed for low
K1M (5)  01 Hynix HYMD512G726(L)4M-K/H/L series is designed for high speed of up to 13
K1N (2)  The CMX866 shares internal register addresses and structure with the CMX86
K1S (16)  SAMSUNG Samsung products are not designed, intended, or authorized for use as com
K1V (20)  新电元 NOTES: 1. tPLH and tPHL are production tested. All other parameters guar
K1Y (1)  arcotronics arcotronics dc0346 • Drives N-channel High-Side and Low-Side MOSFETs in   a sync
K2- (3)  TOS/HITACHI 98 975 The undervoltage-lockout circuit turns the output transistor off whenever
K20 (75)  JRC 02+ Ruotare il selettore su OC . Quando lalimentazione a ON e si applica i
K21 (71)  PAN 03+ 220 Panel attachment K2129 has hole for panel attachment. Please be sure to
K22 (98)  TOSHIBA TO-3P 1. The maximum operating input voltage and output current of the device w
K23 (51)  TECCOR Hynix HYMD532M726(L)6-K/H/L series incorporates SPD(serial presence detect
K24 (56)  LF(TEC) TO-92 06+ The Customer Demonstration Board provides the ROC093XC radio with a PIC mi
K25 (48)  The MLX90247family sensors are thermopile sensors IC which detects very
K26 (58)  FUJI TO-220 04+ These modes are entered by placing a high voltage VPP on pin 19, with pin
K27 (46)  NEC TO-220 06+ The power switch is an N-channel MOSFET with a maximum on-state resistanc
K28 (42)  HITACHI This flip-flop has independent data, preset, clear, and clock inputs and
K29 (87)  Agilents ACMD-7401 duplexers provide high RF performance in a very small
K2A (1) 
K2C (1)  Most Significant Data Bit (MSB) Data Bits 10C1 Least Significant Data Bi
K2E (2)  MOT SMD-16 02   C Sixteen 2-Kbyte (16-Kbit) Zones   C Self-timed Write Cycle
K2F (1)  SAMSUNG SOJ Data enable. As defined in the DVI 1.0 specification, the DE signal allow
K2H (1)  This N-Channel MOSFET has been designed specifically to improve the overa
K2L (1)  Freescale 08+ Programming of each output occurs through an industry- standard, two-wi
K2M (1) 
K2N (5)  ST STM1403 SUPPORTS FIPS-140 SECURITY LEVEL 3+ C 4 High-Impedance Physica
K2P (1)  5000   Output Drive Capability: 15 LSTTL Loads   Outputs Directly In
K2S (1)  Program memory can store both instructions and data, permit- ting the AD
K2X (3)  PHILIPS The On/Off Control (pin 3) may be used for remote on/off operation. As sho
K-3 (2)  00 The EL2141 is a very high bandwidth amplifier whose output is in differe
K30 (61)  INFINEON TO-247 05+ The standard device offers access times of 100, 110, 120, and 150 ns, al
K31 (30)  NEC TO-220   The K3109 is designed for highCvoltage, highCspeed power switchin
K32 (27)  - Übertragungsrate: 10/100 MBit/s - Protokoll: Modbus/TCP - Integr
K33 (26)  TOS 00+ 2500   Designed with Motorolas advanced SMARTMOS, the 34923 is designed f
K34 (31)  N/A N/A Stresses greater than those listed under MAXIMUM RAT- INGS may cause pe
K35 (38)  TOSHIBA TO220 04+ Notes: 1. Standard packing: Carton (Tube): 40 pcs.; Case: 1,000 pcs. &nb
K36 (21)  89 DIP Input bus select / I2C clock input. The operation of this pin depends on
K37 (18)  TOS TO-220F 06+ Notes:  4. Test conditions assume signal transition time of 3 ns or
K38 (7)  N/A DIP-40P 91+ The third overtone mode is not necessarily at exactly three times the f
K39 (18)  FSC TO 04+ Zener Voltage Range: 6.8V to 200V Hermetically sealed DO-13 metal package
K3A (4)  • Power supply : Vdd: 2.6V 0.1V, Vddq: 2.6V 0.1V • Double-d
K3B (1)  In Slave mode, WDCLK may be at an arbitrary phase with respect to the i
K3C (2)  SAMSUNG SMD 2000 100KEP circuits are designed to meet the DC specifications shown in the a
K3D (1)  The two banks have their own dedicated frequency select pins and can be
K3E (1)  One master and as many slaves as necessary may be connected in parallel t
K3F (1)    Vth can be expressed as voltage between gate and source when low o
K3J (1)  The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmi
K3L (1)  SOT23/5   Designed for Class A or Class AB base station applications with fr
K3N (111)  SAMSUNG 00+ Power-Up Characteristic: Following the application of a valid input sour
K3P (18)  OKI 00+ DIP-42 Maximum ratings are those values beyond which device damage can occur. Ma
K3S (4)  SAMSUNG 03+ TSOP Note 1: Absolute Maximum Ratings are those values beyond which the life
K3T (2)  varicon varicon dc98 5Ω bi-directional switches connect inputs to outputsΩ Pin co
K3Z (1)  high-frequency tube PAN 04+ When a function generator drives a flip-flop in a CLB, the combinatorial
K-4 (2) 
K40 (28)  INFINEON TO-3P 06+ These pins are high impedance reference bypass pins. All these pins sho
K41 (8)  n/a 04+ Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 12
K42 (21)  FSC SOP-8 Inputs Are TTL-Voltage Compatible Provide Bus Interface From Multiple So
K43 (8)  HITACHI TO252 05+ 1 ms instruction cycle time Three multi-source vectored interrupts servi
K44 (8)  01   To reduce power consumption, there are two power-down modes: idle
K45 (5)  tfk tfk dc97 Notes   1. Output current rating may be limited by duty cycle, ambi
K46 (3)  LT SOP 99/00 VBIAS (VCC, VBS, VDD) = 15V, unless otherwise specified. The VIN, VTH and
K47 (10)  VISHAY 05+ 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block
K48 (6)  SEC SOP 97 The basic unit of logic on the ispLSI 1032E device is the Generic Logic
K49 (3)  N/A TO-220 04+ EPIC™ (Enhanced-Performance Implanted CMOS) Process Schmitt-Trigge
K4A (2)  The design of the DM562P is optimized for desktop personal computer appli
K4C (3)  05+ 55 SSOP-32 STANDARD DEFINITION MODE   Hue Accuracy   Color Saturation Acc
K4D (118)  SAM BGA 06+ Chip Select is a TTL compatible input which, when set HIGH, allows norm
K4E (273)  SAMSUNG   AD5382-5 is calibrated using an external 2.5 V reference. Temperat
K4F (197)  SAMSUNG SOP 19 AMD FusionE86SM partners provide an array of products designed to meet cr
K4G (26)  03 The device utilizes advanced temperature compensation for the high-pass &
K4H (119)  LED Dimming Signal Input C Provides the internal reference, via an interna
K4J (15)  ALT BGA Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH
K4L (1)  The AD5379 contains 40, 14-bit DACs in one CSPBGA package. The AD5379 pr
K4M (91)  SAMSUNG 727   The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-se
K4N (15)  SAMSUNG BGA 04+ HY57V641620HG is offering fully synchronous operation referenced to a posi
K4P (7)  SAMSUNG This document is a general product description and is subject to change wi
K4Q (1)  SAM SOJ 02+ HDRIVE, LDRIVE: The outputs of the PWM are totem pole MOSFET gate driver
K4R (28)  33 SAMSUNG Composite type with 2 NPN transistors in one package facilitating high-d
K4S (689)  SAMSUNG TSOP 03+
K4T (26)  SAMSUNG 0707+ The eight latches of the LVTH573 devices are transparent D-type latches.
K4V (2)  PHILIPS 04+ PLCC68 • AGC PIN diode drive circuit for FM RF AGC; AGC   detection a
K4X (10)  SAMSUNG 08+ 6. Load regulation and output voltage are measured at a constant junction
K4Y (1)  SAMSUNG 801 The CY2313ANZ is a 3.3V buffer designed to distribute high-speed clocks
K4Z (2)  25 SAMSUNG O4   The conditioning of the pressure signal begins with a capacitance
K-5 (2)  95   Except for the position of the carrier in respect to the two tone
K5- (3)  MITSUMI SW (Pin 4): Boost Regulator Switch Pin. This pin is the boost regulator s
K50 (52)  sot323 06+ Notes: 1Stresses above those listed under Absolute Maximum Ratings may c
K51 (15)  N/A DIP n/a The DDR SIO operation is possible by supporting DDR read and write operati
K52 (9)  N/A TO-220 04+ The Texas Instruments HPC3130A is a peripheral component interconnect (PC
K53 (11)  仙童* TO-220 10000 The devices also have 96 I/O cells, each of which is directly connected
K54 (5)  tfk tfk dc97 International Rectifier Radiation Hardened MOSFETs are tested to verify t
K55 (21)  N/A TO-220 04+ FEATURES Low-Noise Amplifiers Provide Low Noise and Low   Di
K56 (10)  HIT TO-3P 05+ The information appearing in this Data Sheet is believed to be accurate at
K57 (3)  DENSO . The incoming analog signal appearing between TIP and RING is presented at
K58 (6)  HIT T0-263 05+   The HYM72V64C756AT4 -Series are high speed 3.3-Volt synchronous dy
K59 (12)  Figure 2 shows a Bergerton diagram for switching both high-to-low and low
K5A (17)  SANSUNG? BGA? 07+ Once the device detects a button press, it reads the button inputs and
K5B (1)  Single-chip, low power UHF transmitter 75 MHz to 1 GHz frequency operati
K5D (20)  SAMSUNG BGA10.5*13 04+ RSDS INTERFACE WITH SKEW CONTROL This functional block transforms CMOS l
K5E (1)  SAMSUNG BGA 03+ • Diode noise level of this series is approximately 1/3-1/10 lower t
K5H (13)  N/A 2411 Light intensity is controlled by reducing the voltage at the CTRL input.
K5J (5)  SAMSUNG 04+ scribed in Table 3.), terminated by an acknowl- edge bit. When writing
K5L (6)  SAMSUNG BGA 08+   VOUT Output Voltage The MAX5069A EV kits output (VOUT) is set to
K5P (5)  SAMSUNG 05+ BGA   The absolute maximum ratings are limiting values above which oper
K5Q (4)  SEC BGA/10*11 04+ This protection function is splitted in 2 stages. As shown in figure A5,
K5S (2)  KANDA Hynix HYMD132G725A(L)8-K/H/L series incorporates SPD(serial presence detec
K5T (4)  SONY TSOP 97+   The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. Th
K5U (4)  Note 5: This parameter is guaranteed by design but is not tested. The bus
K5V (7)  SONY TSOP The ISL83488, ISL83490, ISL83491 are configured for full duplex (separat
K5W (1)  24 SAM 06+ At TA = +25C, VDDA = VDDB = VDDR = +5V, load resistance = 500Ω on e
K-6 (2)  150 NULL NULL Collector-to-Emitter Breakdown Voltage Continuous Collector Current Co
K6- (1)  A zero crossing output (ZX) produces an output that is synchro- nized to
K60 (9)  SEC The 80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable
K61 (6)  (4) The products and product specifications described in this material ar
K62 (15)  HIT TO-3P 05+ The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. I
K63 (2)  Dual MOSFET Drives for Synchronous Rectified Bridge Adaptive Shoot-Throug
K64 (9)  N/A TO-3P 04+ The applied external reference input voltage (VREF) determines the full-
K65 (3)  DENSO . The LPC2210/2220 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU
K66 (18)  NEC 袋装 The CS4271s wide dynamic range, negligible distor- tion, and low noise ma
K67 (7)  The READ instruction outputs serial data on the D0 pin After a READ inst
K68 (6)  The J-Series DC tachometer generators are low ripple units possessing a
K69 (4)  ST TO-220 2004+ Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4I
K6A (4)  Notes: 1. As stated in ARINC429. 2. VT refers ot the threshold voltage
K6B (4) 
K6E (24)  Complete PowIRtrain integrated power stage Specification and operating i
K6F (109)  SEC SMD 05+ The output current which can be drawn from the comparator reference (Ire
K6G (2)  A single heat source, centered in the silicon chip is suspended across
K6K (1)  SAMSUNG SOJ/44 0046+ The 56F8322 is a member of the 56800E core-based family of hybrid control
K6M (3)  DESCRIPTION Axial Power Schottky rectifier suited for Switch Mode Power
K6N (1)  K DIP-8 98+ Members of the Texas Instruments Widebus ™ Family State-of-the-Art
K6P (1)  This device is fabricated using LinCMOS™ technology and consists
K6R (557)  Hynix HYMD264646A(L)8J-J series is unbuffered 184-pin double data rate Syn
K6S (1)  If the CVBS input signal is to be decoded using an analog color decoder f
K6T (316)  Video Input These pins accept the YCrCb data in CCIR656 (4:2:2) digital
K6X (205)  SAMSUNG 04+ Hynix HYMD116M645A(L)8-K/H/L series is designed for high speed of up to 13
K70 (8)  TOS 00+ 2500 Parameters identified with boldface type apply over the full operating t
K71 (9)  N/A TO-220 04+   The MSK 3015 is an all N-Channel three phase power MOSFET Bridge C
K72 (12)  FUJI TO-3P 05+ Collector-Emitter Cutoff Current  VCE = 50 Vdc  VCE = 75 Vdc
K73 (6)  N/A TO-220 04+ Each of these Schottky-clamped data selectors multiplex- ers contains in
K74 (7)  HIT TO-220 05+ Data bits to be transmitted through the cable ports are received from the
K75 (6)  TOSHIBA TO-3P 2004+ Terminator technology provides an on-chip series termination resistor (R
K76 (5)  8. The K762 and K762A have RSET/RSET input pins.   An internal freq
K77 (14)  TO-3P 06+ Refer to Functional Diagram. The MIC5031 is a noninverting device. Appl
K78 (8)  NEC TO-3P 02+ Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
K79 (11)  N/A TO-3P 04+ Each port independently collects statistical information using SNMP and th
K7A (128)  SAMSUNG TQFP 05+ The ADP3419 includes an anticross-conduction protection circuit, undervo
K7B (59)  SAMSUNG TQFP 04+ † Notice: Stresses above those listed under "Maximum Ratings&q
K7C (1)  SUNSING QFP The bq2060 SBS-Compliant Gas Gauge IC for battery pack or in-system inst
K7D (14)  SAMSUNG 0619+ 657   Guaranteed Low Skew < 25ps (max)   Very low duty cycle dis
K7F (1)  KEC NA Each XC5200 CLB contains four independent 4-input func- tion generators
K7G (1)  KEC NA Table as shown lists type numbers, which indicate a tolerance of +/-20% wi
K7H (2)  SAMSUNG BGA1315 05+ 184-pin 1mm pin spacing Card Size: 133.35mm x 31.75mm x 1.27mm (5.25 x
K7I (12)  SAMSUNG 03+ n Supports high-efficiency PowerWise Technology   Adaptive Voltage
K7J (3)  6 BGA The TURBOTRANSCEIVER is designed for use in very high speed bus systems
K7L (1)  Note 2: The Absolute Maximum Ratings are those values beyond which the sa
K7M (24)  SAMSUNG 04+ Each of the off-chip memory spaces of the ADSP-21991 has a separate cont
K7N (107)  SAMSUNG TQFP 04+ The K7N161801A-QC13 is based on the powerful CPU030 processor which combi
K7P (20)  SAMS BGA N/A † Package drawings, standard packing quantities, thermal data, symb
K7Q (6)  SAMSUNG BGA The MAX1578/MAX1579 provide four regulated outputs to meet all the voltag
K7R (32)  SAMSUNG BGA 04+ The 74HC/HCT153 have two identical 4-input multiplexers which select t
K7V (4)  PHILIPS QFP 1997 • In-house programming of samples and prototype   quantities
K-8 (1)  MOT Stresses above those listed under Absolute Maximum Ratings may cause per
K80 (17)  TO-3P 06+ Crystal input, has internal load cap (36pF) and feedback resistor from
K81 (24)  Operating Voltage Standby Current Operating Current Input HIGH Volta
K82 (10)  PQFP80 00+ † All characteristics are measured under open-loop conditions, with
K83 (7)  N/A TO-3P 04+   The 12140 is a high speed digital circuit used as a phase compara
K84 (10)  vishay-gro n/a Stripped of its package, a Schottky barrier diode chip consists of a met
K85 (30)  N/A TO-3P 04+ Slew rate control. The programmed output volt- age rise and fall times
K86 (6)  Note 9: For best accuracy, minimize output loading. Higher sink currents
K87 (6)  HARRIS SOP-8 The four supply manager blocks are identical. Each contains three prima
K88 (4)  ESS 2008 Input Capacitors The recommended input capacitor(s) is determined by 1.
K89 (10)  N/A TO-220 04+ 1.5 V 2% 3.3-V Output Within 2 V of 1.5-V Output Under All Conditions 1
K8A (3) 
K8D (32)  SAMSUNG N/A 06+ The CY7C68310 implements a USB 2.0 bridge for all ATA/ATAPI-6 compliant m
K8F (3)  Figure 14.TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Packag
K8M (6)  99 The K8M1539BC OTP (One Time Programmable) micro- controllers are highly
K8N (4)  VIA BGA Package Description Untinted, non-diffused Untinted, non-diffused Untin
K8S (2)  SEC BGA 05+ Once the memory array is erased, the device is programmed (to a logical 0
K8T (7)  BGA VIA 03+
K8W (2)  PHI 99+
K90 (13)  FUJI TO-3P 05+ (7) Standby Control Function   By setting STBYB pin to L, the NJU87
K91 (4)  N/A 00+ PLCC-84 (1) VDRM and VRRM for all types can be applied on a continuous basis. Rat
K92 (11)  ROHM SOP8 This product is specifically designed as a final stage for 802.11a equipm
K93 (14)  EPCOS ZIP-5 07+ Note 1: Dice are designed to operate with junction temperatures of -40C to
K94 (19)  三极管 Includes ESD protection, level-shifting, buffering and sync impedance m
K95 (18)  FUJI TO-220 05+ The two address buses (PMA and DMA) share a single external address bus,
K96 (11)  N/A TO-220 04+ Notes: 1. Test conditions assume signal transition times of 5 ns or less
K97 (8)  N/A TO-220 04+ Writing a value to a DAC can either be a write to the DAC register only o
K98 (4)  东芝 排带 Note 6: Dropout voltage is the differential voltage between VOUT and VIN a
K99 (6)  2008 Instead of the usual two-diode arrangement for establishing idling curre
K9A (1)  KRD 06+ 500 Assembler. The macro assembler allows the assembly code to be merged sea
K9E (1)  PHILIPS SMD 1990 FEATURES • High capacitance has been achieved through precision te
K9F (377)  SAMSUNG BGA 03+ Adaptive or Manual Delay Control for Zero Voltage Switching Operation Ad
K9G (7)  SAMSUNG CAUTION: The BiCMOS inherent to the design of this component increases the
K9H (5)  Jack(Available) Handsets and Telecommunications Applications Two Differential Microphone
K9K (100)  SAMSUNG Note 1: The MAX5075 is 100% tested at TA = TJ = +125C. All limits over tem
K9L (6)  Samsung Modem Control Output For external modem, these pins are bit7~4 of the mo
K9M (1)  99 The Effects of Non-zero Aperture Time For the analysis of aperture time
K9S (1)  SAMSUNG 内存卡 52   (Note 8) (Continued) The following specifications apply for VA =
K9T (1)    The IRPT1053A Power Module, shown in figure 1, is a chip and wire
K9V (2)  2000 PHILIPS 99+ Maximum ratings are those values beyond which device damage can occur. Ma
K9W (33)  2000 PHILIPS 00+ Only few external Components required Input Undervoltage Lockout 67kHz
KA- (21)  HARVATEK 05+ROSH Synchronous function enable. When SYNCEN is asserted high, the internal s
KA/ (1)  TOS TFT Interface Programmable panel size up to 1024 by 1024 pixels. Suppo
KA0 (9)  The RM3183 is a dual line receiver designed to meet all requirements of
KA1 (185)  FAIRCHILD Total Endurance, ICSP, In-Circuit Serial Programming, Filter- Lab, MXDEV
KA2 (572)  SAMSUNG HSIP24 State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera
KA3 (391)  FAIRCHILD The Connect Memory data is received via the Microprocessor Interface at D0
KA4 (83)  FAIRCHILD N/A Two analog comparators. Full duplex UART. I2C communication port. Eight
KA5 (213)  FAIRCHILD O7+  Lead Temperature 1.6mm (1/16 inch) from case for 10s260C (1) Stres
KA6 (51)  BGA 03+ Note: Stresses greater than those listed under MAXIMUM RATINGS may cau
KA7 (541)  FSC 0749 The device integrates complete interfaces to stereo or mono microphones a
KA8 (129)  03+ The Fairchild Switch FSTU3253 is a dual 4:1 high-speed CMOS TTL-compatib
KA9 (68)  The VC33 instruction register is 8 bits long. Table 1 shows the instructi
KAA (18)  SAMSUNG 02+ BGA (1) Losses from power consumed by the internal   oscillator, switch
KAB (69)  SAMSUNG 4 BGA • FCRAM core with Single Data Rate SDRAM   interface •
KAC (6)  SENSOR 48PLCC 02+ • Meets or Exceeds the Requirements of ANSI   TIA/EIA-644-199
KAD (20)  SAM SOP-32
KAE (5)  05+PB is held high, the decoding function is inhibited and all the 8 outputs
KAF (6)  KAF The device is designed to comply with all industry standards set for sync
KAG (9)  SAMSUNG BGA 04+ Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained
KAH (2)  FAI 1250 The HT82V16 is a complete analog signal pro- cessor for CCD imaging appl
KAI (13)  MOTOROLA DIP56 9244 To achieve proper device operation, an initial pause of 200 µs foll
KAJ (2)  Information For further information on technology, de- livery terms and
KAK (1)  BGA 04+ The CM3004 is a very-low-dropout regulator that offers both fixed outpu
KAL (9)  SAMSUNG Stresses above these ratings may cause permanent damage. Exposure to abso
KAM (9)  2500 NOTES: 1. Measured from the differential input crossingpoint to the diff
KAN (8)  KENWOO QFP 96+ The bq2902 is a low-cost charger for rechargeable alkaline batteries such
KAP (5)  The LT®6230/KAP1106E/KAP1106E are single/dual/quad low noise, rail-to
KAQ (35)  COSMO DIP-6 05+ Note 8: Care should be taken to include the effects of self heating when
KAR (18)  FAIRCHILD ♦ Low Power: 511mW (fCLK = 100MHz) ♦ User Programmable  
KAS (12)  SAM 0607+PB The DAC8580 is a 16-bit, high-speed, low-noise, voltage-output DAC desi
KAT (10)  FAIRCHILD Modulo periferico di conversione digitale-analoghica ad alta risoluzione
KAV (12)  The MAX3058 features four different modes of opera- tion: high speed, slo
KAW (1)  • Programmable output from 2.1V to 3.5V using integrated   4-
KAX (2)  Once the memory array is erased, the device is programmed (to a logical 0
KAZ (1)    A typical single video channel connection diagram for the MSK 620
KB- (20)  100 SOP 00+ The operating temperature range varies with the supply voltage, with a hi
KB0 (3)  INFINEON TO:263 05+ As long as the LOCK register is not set, the output characteristic can
KB1 (43)  DIP16 93 each port are independent of one another and can be asynchronous or coinc
KB2 (40)  DIP16 91 This IC was developed for use in cordless telephones. It is a compander IC
KB3 (19)  SOT23-5 05+ The CY7B951 can be used in Local Area Network ATM appli- cations. The o
KB4 (8)  DIP16 93 LMD is the last measured discharge capacity of the battery. On initializa
KB5 (4)  100 MICREL 05+ As long as the differential input signal to the OTA remains under 50mV
KB6 (1)  The high-side driver is designed to drive low rDS(on) N-channel MOSFETs.
KB7 (1)  PRX SOP These devices are sometimes soldered to a small light- weight heat fin t
KB8 (26)  INTEL 95+ (< 50 mA in Sleep Mode) LIN−Bus Transceiver:  ♦ PNP&
KB9 (18)  QFP QFP 2005 The LEDs are packed in cardboard boxes after packaging in anti-electrostat
KBA (9)  MINI 08+ a. AC characteristics apply for parallel output termination of 50Ω
KBB (2)  SAMSUNG BGA 04+ • Industry Standard Size • Industry Standard Pinout  
KBC (19)  SMSC TQFP 06+ The AVR core combines a rich instruction set with 32 general purpose work
KBD (5)  - 9951+ 400 SOT-363 PCB Layout A PCB pad layout for the minia- ture SOT-363 (SC-70)
KBE (6)  SAMSUNG 0722+ 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access
KBF (8)  KYOCERA ElCO READ: The AT49BV16X4(T) is accessed like an EPROM. When CE and OE are lo
KBH (1)  The DAB is a quad-word FIFO that enables loading of quad- word data from
KBI (1)  KINGBYTE 97 The KBIC-951A is an audio power amplifier primarily designed for demandi
KBJ (39)  SEP 2007 Quasi Resonant Converter Controller Internal Burst Mode Controller for
KBL (51)  DSI n/a TEMPERATURE PROTECTION   The thermal protection shuts the LX8819 do
KBM (12)  208 • In-Circuit Serial Programming (ICSP™) • Internal 4
KBO (1)  Complete implementation of Plug n Play standard   Direct interface
KBP (207)  SEP 2008+ TDIR Direction Control TTL Levels EDIR Direction Control ECL Levels
KBR (68)  KYOCERA 5*7 (1) The algebraic convention, in which the least positive (most negative)
KBS (12)  Hardware Reset, active Low. Provides a hardware method of resetting the
KBU (104)  FS 07+ s No products described or contained herein are intended for use in surgi
KBW (2)  The ISL5757 is a 10-bit, 260+MSPS (Mega Samples Per Second), CMOS, high s
K-C (1)  PAN 04+   Information present at any register is transferred to the respect
KC- (7)  The HR700 Series of DC/DC converters has an upper operating temperature
KC. (1)  During steady-state operation for a typical switching cycle, the oscilla
KC0 (12)  KC 05+ Information in this document is provided in connection with Intel product
KC1 (22)  02+   This device contains protection circuitry to guard against damag
KC2 (22)  N/A NEW N/A Note: Capacitors with K tolerance (10%) and SL characteristics must be us
KC3 (31)  MOT PLCC44 07+ Designed for Digital Photography, Graphic Arts, Medical and Scientific App
KC4 (12)  KEC 02+ (3) The products described in this book are intended to be used for stand
KC5 (26)  KYOCERA 2001 High Voltage: Operation Up to 72V Synchronizable Operating Frequency and
KC6 (6)  DIP DIP   : When assigning bit operand, K1~K4 are used for 16-bit and K5~K8
KC7 (27)  SAM or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics O
KC8 (69)  intel intel dc0449  The Hynix HYM71V8M635B(L)T6 Series are Dual In-line Memory Modules
KC9 (5)  The processor provides six addressing modes, supporting memory-to-memory,
KCA (4)  MOLTILAYER 06+ 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-R
KCB (9)  kyocera kyocera dc02 *On products compliant to MIL-PRF-38535, this parameter is not production
KCC (11)  NIPPON 05+ SMD ICS has been shipping motherboard frequency generators since April 1990,
KCD (13)  NEC QFP 07+/08+ • Ideal for Battery Operated Applications • Telecommunicatio
KCE (6)  This IC provides protection for lithium ion batteries in the event of over
KCF (9)  NIEC T0-3P 04+ The highly integrated switches require no external memory at all, and th
KCH (30)  NIHON TO-3P 08+ • 1500 Watts for 10/1000 µs with repetition rate of 0.01% &n
KCI (1)  ? CDIP24 9131    This low failure rate represents data collected from Maxims
KCJ (2)  QFP80 Output Voltage Temperature Coefficient   • 150 ppm/C, typical
KCL (4)  NA NA Acknowledge is a software convention used to indicate successful data t
KCM (3)  KAR The charge sampler capacitor (Cs) can be virtually any plastic film or l
KCN (3)  KSD 05+ DESCRIPTION The 74VHC08 is an advanced high-speed CMOS QUAD 2-INPUT AN
KCO (11)  KOYO DIP-4 91+ Figure 1 shows the CY7B951 in an ATM system that uses the PMC-Sierra PM
KCP (6)  COSMO DIP 07+ over the range, 0.8 V to 3.6 V, using a single resistor.   Other o
KCQ (8)  NIEC TO-3P 04+ in portable applications such as cellular telephones. The de- vice also
KCR (9)  Dimension are in inches. Metric equivalents are given for general informa
KCS (12)  kyocera kyocera dc02 Hynix HYMD264G726A(L)4-M/K/H/L series is registered 184-pin double data ra
KCT (6)  3X4 +3 Volt single power supply Low power CMOS design 4-Wire serial interfac
KCU (4)  NIHON TO-3P 08+ In XC4000E, the H function generator is more versatile. Its inputs can
KCZ (1)  N/A A sequence of the digitalized time-code signal can be analyzed by a spec
K-D (2)  • FCT-C speed at 5.5 ns (FCT16841T Coml) • Power-off disable
KD- (4)  DIP16 93+ Notes:  1. ZZZZ or ZZZ denotes the assigned product dash number. Th
KD0 (14)  SEC 798 Low skew: < 200ps Fast switching frequency >133 MHz Fast output
KD1 (72)  ST TO-252 Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating
KD2 (64)  IR 04+ The bq2050 determines battery capacity by monitor- ing the amount of curr
KD3 (21)  N/A 1. Stresses above those listed under the Absolute Maximum Ratings may cau
KD4 (31)  IR 04+ Built-in power save circuit Built-in current limit circuit Built-in th
KD5 (14)  MOTO 03+ Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low
KD6 (29)  POWEREX SOP Hynix HYMD216646A(L)6J-J series incorporates SPD(serial presence detect).
KD7 (21)  K QFP-S32P 07+ CLKAs output originates from the cross point switch and goes through a pr
KD8 (13)  Collector-Emitter Voltage Emitter-Base Voltage Collector-Base Voltage P
KD9 (17)  SanRex SOP Parameter MPU PORT2, 3   SCLOCK Frequency   SCLOCK High Pulse
KDA (103)  SAMSUNG PLCC32 By leaving both the RCLK and RSER outputs unconnected or tied to VCC, t
KDB (1)  DIP 07+ 4Mbits (512k x 8 bits) organization FIFO Independent 8bit read/write port
KDC (5)  KEC Blackfin processors support a modified Harvard architecture in combinati
KDD (2)  TSSOP-8P 6+ The 34-pin PowerCap module integrates SRAM memory and NV control along wit
KDE (27)  sunon sunon dc02 Ground pin. This pin should be connected to system ground with minimum
KDF (9)  HIROSE 04+ This advanced BiCMOS design features low operating current, adjustable
KDG (1)  systems with output voltages below 7V, a 10µH inductor is the best
KDH (1)  Note 2: When using the shutdown input, the maximum output voltage allowed
KDI (2)  KDI 246 Inverter IGBT part (per 1 element), (Note-1) Inverter FWDi part (per 1
KDL (1)  2007 n Provides constant and proper gate drive to power   MOSFETs regard
KDM (2)  KTS DIP 07+/08+ Note 1: Specifications are 100% production tested at TA = +25C. Maximum an
KDN (17)  KTS 00+ Pin-for-Pin compatible with AMD® Am186ES/188ES devices All features
KDP (1)  Accuracy (each DAC)   Integral linearity error   Diffential l
KDQ (1)  KINGSKY PLCC 04+ PLL1, CLKA, and CLKB each have multiple registers supplying data. Program
KDR (50)  otax otax dc02 The MAX2654/MAX2655/MAX2656 high third-order intercept point (IP3), low-n
KDS (151)  KEC 08+ Flame-resistant   Suppress combustion and smoking after a malfuncti
KDT (1)  The AMC5902 contains a direct PWM control system for spindle and two sl
KDV (102)  SAMSUNG 00+ 12000 TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that
KDW (2)  ST DIP 1992 Note 4: The Absolute Maximum Ratings are those values beyond which the sa
KDZ (99)  KEC Stresses beyond those listed under "absolute maximum ratings" ma
KE- (7)  DATEL 1 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
KE0 (5)  The C-suffix devices are characterized for operation from 0C to 70C. The
KE1 (15)  1206-1.25A change state within a watchdog timeout period, U1 lights the LED by asse
KE2 (13)  DAILO 1206 05+   The 17517 can drive two motors in two directions one at a time or
KE3 (8)  1206 Stresses beyond those listed under Absolute Maximum Ratings may cause per
KE4 (12)  KAWASAKI qfp 05+ The above calculation is conservative: with VCC = 2.7V and the three tran
KE5 (46)  IR 04+ Notes:  2. See the last page of this specification for Group A subg
KE6 (2)  INFINEON 02+ QFP-64 Note 2: When the input voltage (VI) at any pin exceeds the power supplies
KE7 (17)  N/A † Signaling rate by TIA/EIA-485-A definition restrict transition ti
KE8 (3)  Daito 05+ Applications • DC-DC converters • Synchronous rectification
KE9 (9)  2007 The UCC381 provides unique short circuit protection circuitry that redu
KEA (2)  SAMSUNG BGA 05+ The MMUs support multiprocessing, virtual memory systems by translating l
KEC (16)  N/S  − Provides 22 kbits dedicated melody ROM   − Prov
KED (11)  PRX SOP Fixed Output Voltages of 2.048 V, 2.5 V, 3 V, 4.096 V, 5 V, and 10 V Tig
KEE (4)  PRX SOP   The frequency shifting is accomplished by switching out different
KEF (7)  ITT DIP 00= The device provides ultrastable +4.500V output with 0.4500 mV (.01%) init
KEG (3)  infineon O7+ Crystal Input Operation   The KEG3000D features a fully integrated
KEI (5)  N/A QFP Note 1: Absolute maximum ratings are DC values beyond which the device m
KEK (1)  Positive digital power supply. Ring oscillator/crystal input pin. Rese
KEL (42)  MOT SOP8 The LT®5534 is a 50MHz to 3GHz monolithic RF power detector capable o
KEM (13)  One of outstanding features of the KEMC0603C279C5GACTU is its CPU core, a
KEN (5)  F Computer-Operating Properly (COP) watchdog timer External interrupts vi
KEO (2)  ∙ 2,097,152-word 8-bit configuration ∙ Single 5V power su
KEP (5)  XADA SOP-8 N/A Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On This i
KES (24)  Data inputs for a 8-bit bus. When EF is LOW, the FIFO is empty and furth
KET (2)  KTNW00D 99 QFP SS (Pin 13) (soft start): SS will remain at Gnd as long as the IC is dis
KEY (8)  PHIL PLCC Forward Voltage Reverse Voltage Peak Wavelength Spectral Bandwidth Res
KEZ (1)  1800 05+ High-Performance Built-In Clock Management Circuitry - Eight fully digi
K-F (1)  FAIRCHILD Note 1) The specified condition Tj=25˚C means that the test should
KF- (1)  125 kHz RFID Chip for Cards and Tags 256 Read/Write EEPROM Bits, Divided
KF0 (11)  SOP 98 505µA supply current 75MHz bandwidth Power down to Is = 33µA
KF1 (16)  DIP16 98 The inhibit function is provided by the Inhibit* control, pin 1. If pin
KF2 (21)  rohm rohm dc98 Note 6: Total latency for the channel link chipset is a function of clock
KF3 (27)  ST TO252 2000 OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separati
KF4 (38)  ST 99+ SMD8 Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW
KF5 (40)  SAM 1999 芯片 1. One output at a time for a maximum duration of one second. Vout = 0.5V
KF6 (16)  ST 06+ 11720 The Discrete Products Operation of Fairchild Corporation has developed
KF7 (1)  This is a dual-purpose pin. During Master Reset, a HIGH on BE will select
KF8 (12)  ST 06+ These pins are connected to the inputs of the tone control op amps. A c
KF9 (5)  KEC ∗1 Indications of substrate voltage (VSUB) reset gate clock voltag
KFA (2)  • Single +5V supply • 24-pin SOIC • Compatible with fi
KFB (4)  TAIYO 05+ RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Vol
KFC (1)  ZHUANBAO SOP RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Re
KFD (1)  OTAX 07+ The HYM72V16M656H(L)T6 -Series are gold plated socket type Dual In-line Me
KFF (38)  N/A 865 The MAX1533/MAX1537 include on-board power-up sequencing, a power-good (P
KFG (8)  SAMS BGA 2006 10-Year Minimum Data Retention in the Absence of External Power Data is
KFH (3)  Wake-up Function for a Microcontroller with Preamble Detection 1 mVrms Se
KFJ (1)  1. A 0.1 µF low frequency tantalum bypass capacitor in parallel with
KFK (1) 
KFM (5)  cts cts dc99 Wide single supply voltage range or dual supplies : +2V to +36V or 1V to
KFN (5)  MOTOROLA CAN 00+ ACEX 1K device package types include thin quad flat pack (TQFP), plastic
KFO (7)  The VGA CMOS image sensor features DigitalClarity Microns breakthrough l
KFP (1)  The CLC425's combination of ultra-low noise, wide gain-band- width, high
KFR (9)  PHIL PLCC The microphone input transfers its signal to the on-chip preamplifier. An
KFS (17)  N/A N/A To be able to use a wide frequency range for the VCOs (i.e., VCO2 26.3 MH
KFW (15)  TriGem SOP-32 00+ Hardware data protection measures include a low V CC detector that autom
KFX (12)  0 SOP The B9946 is a low-voltage clock distribution buffer with the capability
KFY (2)  TESLA CAN3 N/A Sound volume, tone and balance controls for car audio systems and other
KFZ (1)  SHARP 2008 READ: The AT28C010-12DK is accessed like a Static RAM. When CE and OE are
KG- (2)  TAXAN QFP QFP DESCRIPTION Available either in through-hole of surface and T25 mount p
KG. (1)  The device is compatible with the JEDEC single power-supply Flash comma
KG0 (1)    The MAX422_EUT is 100% production tested at TA = +25C. Specificati
KG1 (2)  STANLEY 0805发 All units in these Hitachi MultiMediaCards are clocked by an internal clo
KG2 (13)  N/A 0805T Analog signals should be inputted through AIL and AIR pins. The signals t
KG3 (7)  100 SAMSUNG 00+ Insert the Controller through the hole in the panel from the front and p
KG5 (1)  SANSUNG QFP 99 NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the lar
KG9 (4)  96
KGA (2)  This information is believed to be accurate and reliable, however no resp
KGB (2)  SAMSUNG 798 AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inv
KGC (2)  KGC SOP-20 03+ Note 1 Absolute Maximum Ratings are those values beyond which the safety
KGF (47)  OKI SO-86 06+ Each cell in a multiple cell pack is compared to an internal reference
KGL (3)  OKI Hynix HYMD232M726A(L)8-J/M/K/H/L series is designed for high speed of up
KGR (1)  SEC CRemote Sense: This is the logic 0 reference for the inputs VID0 C VID4,
KGS (1)  The MIC5158 produces a brief logic-low error-flag output at start-up be
KGT (5)  01 First 14-bit ADC in a SOT-23 package. High throughput with low power co
KGV (2)  GOVT PROP 毛块 Added Package Pins to GPIO table in Section 8. Clarification of TRST usage
KGY (1)  6 SOP The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to g
KH- (5)  Relay(DZ) 9641+ ADC data outputs are internally connected directly to the receivers digi
KH0 (10)  1. Solder the copper pad on the backside of the   device package to
KH1 (5)  SAM DIP-20 93+   The KH138 has a differential LVPECL reference input along with an
KH2 (23)  CAN12 No signal input. Measure the current flowing into pin 13 . No signal in
KH3 (1)  Note 1: INL and DNL is measured using a sine-histogram method. Note 2: In
KH5 (4)  COMLINEAR CDIP24 0426+ (*) CPD is defined as the value of the ICs internal equivalent capacitanc
KH6 (3)  PRX SOP The AF/AE flag has two programmable limits: the almost-empty offset value
KH7 (1)  N/A SOP 98+ † Stresses beyond those listed under absolute maximum ratings may c
KH8 (4)  ON SOP-14 05+ The Si9711CY is a monolithic switch designed to meet the needs of the P
KH9 (2)  ZIP-16 These are single-chip 16-bit microcomputers designed with high-per- form
KHA (21)  Specifications in standard type face are for TJ = 25˚C and those wit
KHB (1)  ON SOP-14 04+ Highest sustained bandwidth per DRAM device • 8000/6400/4800 MB/s
KHC (6)  NIPPON 2522-225 05+ Guaranteed monotonic INL error: 4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/C
KHD (2)  ments are used to graphically indi- c a te av a ilab le c a p ac it y . T
KHF (1)  STMicroelectronics 32-bit, ARM core-based microcontrollers are supported
KHG (1)  N/A N/A N/A NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD
KHJ (1)  Note 6: Because the Bus LVDS serial data stream is not decoded, the maxim
KHM (2)  The constant-frequency, current-mode PWM architecture provides for low out
KHN (1)  The LTC ®1698 is a precision secondary-side forward converter control
KHO (25)  The 10 MHz CD outputs are enabled for about 1 µs at approximately
KHP (4)  Bus Interface   • 16-bit address output, 8/16-bit data input
KHS (21)  kyocera kyocera dc02 CD4053BC is a triple 2-channel multiplexer having three separate digital
KHT (4)  PHIL PLCC MODE. Logic input to set current-decay mode. In response to a PWM Off c
KHU (4)  The ICS9248-131 generates all clocks required for high speed RISC or CISC
KHX (2)  The SDA is a bidirectional serial data input/output pin for a 2-wire sl
K-I (3)  SIEMENS SMD 03/+04+ The HYM72V32C756AT8 H-Series are gold plated socket type Dual In-line Memo
KI- (4)  Low On-Resistance and wide bandwidth make it ideal for video and other
KI1 (2)  If the magnetic field exceeds the threshold levels, the current source
KI3 (1)  DIP No output filter required for inductive loads Externally configurable g
KI5 (2)  The ZL10354 is a superior fourth generation fully compliant ETSI ETS300 7
KI6 (2)  KODENSHI Features  NPT IGBT technology  low saturation voltage  l
KI7 (1)  94 SOP causes the DQ pins to tri-state. Crystal Connection, drives crystal on st
KI9 (1)  AT SOP20 05+ NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu
KIA (1144)  KEC TO-220F4 Resistance R1 Capacitance C1 at 2.5V dc; 1MHz, 30mV ac Stand-off Voltage
KIB (1)  KEC Device Protocol The X76F102 supports a bidirectional bus oriented pro-
KIC (119)  SOT23/5 02+ The devices are stable with capacitive loads up to 10 nF, although the 6-
KID (48)  94 SOP   device reliability. These are stress ratings only, and functional
KIE (1)  TROY QFP1420-64 1. Ground / thermal vias are critical for the proper   performance
KIF (2)  The error amplifiers exhibit a common-mode voltage range from C0.3 V to V
KIK (1)  Data terminal ready A/B (active low). To indicate that ST16C2552 is rea
KIN (5)  SOP/8
KIQ (1)  Note b: ICC and ICC are dependent on output loading and cycle rate. The
KIR (1)  Note 4: When the input voltage (VIN) at any pin exceeds the power supplie
KIS (2)  RF input pin. This pin requires the use of an external DC blocking capa
KIT (51)  FREESCALE O7+ PAGE WRITE: The page write operation of the AT28C010-12DK allows 1 to 128
KIU (1)  SAN sop 03+ The SN74LVT16646 is available in TIs shrink small-outline (DL) and thin s
KIV (4)  Shindengen A 1% resistor must be connected between pin 4 and pin 7 to set the output
KIX (3)  All data following is valid between 4.5V and 5.5V at ambient temperature.
KJ- (3)  The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level m
KJ0 (3)  CHINA DIP 05+ The regulator voltage output used to power the load. A nominal output cap
KJ1 (1)  N/A n 5 Volt Read, Program, and Erase   C Minimizes system-level power
KJ3 (1)  SEC 04+ † TPS3106E09 and TPS3110K33 will be available in August 2001; all o
KJ4 (2)  Elantec Semiconductor, Inc. products are not authorized for and should n
KJ5 (1)  ROHM SMD-8 00+ 1. Above specification may be changed without notice. EVERLIGHT will rese
KJ6 (2)  The differential inputs provide a full scale differential input swing eq
KJA (7)  KSD 05+ CPU_STP# is an input to the clock generator. CPU_STP# is asserted asynch
KJF (2)  The two PWM controllers that regulate the system main 5V and 3.3V voltage
KJR (1)  • High switching capacity 30 A for 1 Form A • 2 contact arra
KJT (3)  Sequencing. Auto-Track simplifies the task of supply voltage sequencing
KJZ (2)  Do not store the product in the area where temperature exceeds the maximu
KK1 (27)  1850 The HYM72V16M656B(L)T6 -Series are gold plated socket type Dual In-line Me
KK2 (15)  N/A SMD The device is entirely command set compatible with the JEDEC single-powe
KK3 (1)  These P-Channel MOSFETs from International Rectifier utilize advanced p
KK4 (10)  N/A N/A N/A Wide input voltage range 5V to 15V Tight line regulation 0 5% (typ) Outp
KK5 (13)  N/A N/A N/A As a member of the SWIFT™ family of dc/dc regulators, the TPS54873
KK6 (1)  High Current Transfer Ratio, 800 % Low Input Current Requirement, 0.5 m
KK7 (10)  SANREX 04+ The A and B Ports are protected against undershoot to support an extend
KK8 (1) 
KK9 (6)  No license is granted, implied or otherwise, under any patent or patent ri
KKA (11)  Glass passivated junction. 500W Peak Pulse Power capability on 10/1000
KKC (2)  KENWOOD 99+ QFP A page write is initiated the same as byte write, but the microcontroller
KKE (4)  1194 Note 5: Except pin G7: +100 mA, −25 mA (COP920C only). Sampled and
KKJ (1)  The IC41C1665 and the IC41LV1665 are CMOS DRAMs optimized for high-spee
KKP (1)  The AT8xEB5114 has 3 software-selectable modes of reduced activity for fu
KKQ (4)  KENWOOD SOP 07+ The EB-2100x accommodates either a coaxial or an optical S/PDIF digital a
KKS (1)  FUJI SOT-252 05+ The device is designed to comply with all JEDEC standards set for Synchro
KKT (1)  kec 06+ o6o3 IC ground Enable/disable Control input (duty cycle) Duty cycle reductio
KKZ (4)  00 Design complexity is enhanced by the addition of synchronous set and asyn
KL- (1)  KYOSAN Initialization of both devices must occur before data trans- mission beg
KL0 (1)  230 INTERSIL 02+ FEATURES Throughput Rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V
KL1 (14)  N/A N/A N/A Notes: 1. For Max. or Min. conditions, use appropriate value specified u
KL2 (12)  DIP Designed for DDR200/266/333/400 PC mother board clock buffering Supports
KL3 (119)  N/A 3225 If the state of the selected CAP/MAT signal is 1 and EDGE is set to detect
KL4 (1)  NEC SOT-23 04+   The SI-3033LSA is designed to meet the requirement for increased
KL5 (36)  06 Stresses above those listed under Absolute Maximum Ratings may cause per
KL7 (65)  N/A 0805L The PCX8582X-2 is a 2-Kbit (256 8-bit) floating gate electrically era
KL9 (5)  98+ 模块 Shutdown. When SHUTD input is low, the internal clock is stopped and the
KLA (4)  KEC NA Output enable. When logic HIGH, the outputs are enabled (default). When
KLB (2)  ROHM 00+ Rating to 200V VBR For surface mounted applications Reliable low cost co
KLC (2)  ROHM Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shi
KLD (19)  KYCON   The PT4310 modules are a low-power series of isolated DC/DC conve
KLE (4)  KOA 05+ The reset threshold is either the internal defined VRT voltage (typical 4
KLF (1)  • 40lower Eoff compared to previous generation • Short circui
KLG (3)  In a typical standalone IP phone, the DSP handles the voice processing fu
KLH (13)  COSMO DIP-6 01+ The KLH1056BM KLH1056BC buffered 8-channel data selec- tor is a compleme
KLI (11)  KYOSAN 04+ The MHF converters are switching regulators which use a quasi- square wa
KLJ (1)  Notes: 1. The luminous intensity, IV, is measured at the peak of the sp
KLK (26)  LITTELFUSE 0718+ The operational overview diagram in Figure 2 illustrates the operation of
KLL (6)  ST DIP8 The bq2016 gas gauge IC for battery pack or in-system installation mainta
KLM (4)  北京 NO信号调理模块   The RC4700 processor also supports a supervisor mode in which the
KLN (6)  KLN SMD 1993 The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiple
KLR (3)  KEC NA Data flow in the B-to-A direction, regardless of the logic element select
KLS (8)  ROHM DIP4*4 99+ 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continu
KLT (22)  MOT SOP8 00+ The ICS91309 is a high performance, low skew, low jitter zero delay buff
KLU (1)  Processor-Independent Pulse Width Modulation   (PWM) mode: Generates
KLV (1)  The MSA-series is fabricated using Agilents 10 GHz fT, 25 GHz fMAX, sil
KLW (2)  N/A Device Addressing Following a start condition the master must output the
KLY (2)  KEC NA Note 1: This device is constructed using a unique set of packaging techniq
KM- (6)  N/A N/A 05+ DESCRIPTION The CLP30-200B1 is designed to protect telecommunication e
KM0 (5)  KUNMING 06+ The contents of this specification are subject to change without further
KM1 (37)  N/A SOP24 03+ 1. Laser trimming of both initial accuracy and temperature   coeffi
KM2 (304)  SAMSUNG TSOP-44 For output voltages less than 10 V, the minimum input voltage is 7 V or (
KM3 (27)  SEC 97+ QFP1420-100 Key features include an 8-bit memory mapped architecture, a 16-bit time
KM4 (1481)  SAM TSOP 01+  This data sheet has been carefullyAPEX MICROTECHNOLOGY checked and i
KM5 (10)  SAMSUNG PLCC 03+   This 16-bit bus transceiver is built using advanced dual metal CMO
KM6 (1321)  SAMSUNG 04+ the 1Hz band to the power in the fundamental. When the re- quired offset
KM7 (247)  SAMSUNG TQFP1420-100 99+ VCC Threshold Reset Procedure The KM736V849T-75/KM736V849T-75 has a stan
KM8 (10)  SAMSUNG DIP The graphs and tables provided following this note are a statistical summ
KM9 (38)  SAMSUNG N/A N/A SEG21/P11.2 SEG22/P11.1 SEG23/P11.0 SEG24/P10.7 SEG25/P10.6 SEG26/P10
KMA (17)  N/A 0805F External Data pins allow for In-System Programming of the device and sett
KMB (5)  NEC QFP-80 99 A buffered output-enable (OE) input can be used to place the eight output
KMC (95)  ASAT LPCC 00
KMD (23)  N/A 0603F But, problems arise if you must connect two computers together. Both are
KME (137)  NCC SOP 1.125 (28.56mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC
KMF (31)  nec nec dc04 The M41T81S Serial Access TIMEKEEPER ® SRAM is a low power Serial R
KMG (55)  NIC 07+ To guarantee the Table 1 delay accuracy for input pulse width smaller tha
KMH (85)  nec nec dc04 • 10-bit Analog-to-Digital Converter module (A/D)   with: &n
KMI (13)  PHILIPS SOT453B 2001 ITH (Pin 3): Error Amplifier Compensation Point. The current comparator t
KMJ (1)  N/A 1206 Case: Similar to DO-214AA Terminals: Leads tin plated Thermal resistance
KML (1)  s Pin compatible with SC16C2550 with additional enhancements s Up to 5 M
KMM (103)  18 SEC 912 The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible l
KMN (1)  For best performance, keep the timing capacitor lead to GND as short as p
KMO (22)  COSMO Relay(new original)   CAUTION: These devices are sensitive to electrostatic discharge; f
KMP (93)  free free dc0447   Please be aware that an important notice concerning availability,
KMR (13)  OTAX 07+ Note: The HUMMER module is rated at a total operating power   more
KMS (30)  HIROSE 03+ The ADSP-TS202S processor has compute blocks that can exe- cute computat
KMT (3)  • Scanner/Printer Stepper Motor Control   − Four outputs
KMU (1)  Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
KMV (1)  In the 53 tap low pass filter mode, the GF9102A can replace the TMC2242 i
KMX (6)  nec nec dc00 As VCE is further increased, beyond the thermally limited region, the saf
KMZ (17)  PHI SOT195 06+ Just as the USB Interrupt is shared among 27 individual USB- interrupt
KN- (1)    The PT4140 power modules are a series of isolated DC/DC converter
KN0 (2)  Consult factory for available frequencies and specs. Not all options avai
KN1 (5)  PHI QFP-M80P 6+   For more information on the PWP package, refer to TI technical bri
KN2 (29)  DIP16 98 To protect the product from the effects of humidity until the package is
KN3 (15)  DIP 98 The ACT16241 are 16-bit buffers or line drivers designed specifically t
KN4 (50)  VIA BGA 0348+ Ultrasmall package facilitates miniaturization in end products. Especia
KN5 (2)  00+ To fully enhance the external N-channel switches, internal charge pumps a
KN6 (1)  SOP SOP tolerance voltage regulation. Through the use of external resistors, the
KN7 (1)  The Analog System is composed of 6 configurable blocks, each comprised
KN8 (2)  This is a dual-function pin. In the CY Standard mode, the FF function is
KN9 (1)  The LM4980 is a stereo headphone audio amplifier, which when connected
KNA (10)  N/A The device provides a standard mode (100 Kbits/s) 2-line serial interface
KNB (7)  The on-chip status register allows the progress of various operations to
KNC (1)  A bidirectional parallel port that includes   A modifiable address
KND (30)  98 ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2
KNE (1)  2003 Stresses beyond those listed under absolute maximum ratings may cause pe
KNF (13)  N/A The MAX2654/MAX2655/MAX2656 high third-order intercept point (IP3), low-n
KNG (1)  The KNG160VB33M10X20/KNG160VB33M10X20 are low-dropout, low-quiescent- cur
KNH (6)  KYOCERA 06+ SMD The Radiation Hardened HS-1825ARH Pulse Width Modulator is designed to
KNO (3) 
KNP (16)  The TFP513 combines PanelBus circuit innovation with TIs advanced 0.18 &m
KNR (1)    This 20 VGS gate drive vertical Power MOSFET is a general purpose
KNS (1)  An Intel 8254 timer-counter (or functionally equivalent device) generates
KNT (1)  • DigitalClarity™ CMOS Imaging Technology • Array Form
KNY (1)  Reset input to the decoded zero counter A logic 0 on this input resets a
KO1 (1)  IMI 1465 The IC41C4400x and IC41LV4400x are CMOS DRAMs optimized for high-speed
KO3 (4)  08+ Figure 4 shows the waveforms of the circuit of Figure 3. Note that the
KO4 (1)  ST The output stage of the MD1810 has separate power connections enabling th
KO6 (1)  *Stresses greater than those listed above may cause permanent damage to th
KOA (12)  KOA SOP-8 04+ Power Supply Bypassing   The KOA1002B is a mixed analog/digital pro
KOB (1)  The TPS6021x charge pumps provide a regulated 3.3-V output from a 1.8-V t
KOC (2)    The MP7523/XRD7523s excellent multiplying characteris- tics and l
KOH (1)  The UCC384-x family of negative linear-series pass regulators is tailored
KOI (2)    This device contains protection circuitry to guard against damage
KOK (2)  DMA Controller supports: 25 DMA channels for transfers between ADSP-2136
KOL (1)    Data are completed by a End-of-Message (EOM) word, consisting of 2
KOM (7)  OSRAM 2002+ 4. Values for two Turn-On loss conditions are shown for the convenience o
KON (6)  NEWPORT PQFP-128 99 0.368 x 1.136 Microstrip 0.151 x 0.393 Microstrip 0.280 x 0.220 Micro
KOO (1)  5. Diagnosis output (pin(25))   The diagnosis output terminal of pi
KOP (2)  Theory of Operation The AEDR-8300 series combines an emitter and a detec
KOR (4)  PHIL PLCC In contrast to the direction switches, the hazard input is a low-side typ
KOS (4)  VCC is the main 5V supply, which can be disabled in a PC, and VSBY is t
KOU (1)  SMD-14 04+ Widebus Family Designed to Be Used in Voltage-Limiting Applicati
KOV (3)  2000 PHILIPS 00+ Hynix HYMD132725B(L)8-M/K/H/L series is unbuffered 184-pin double data rat
KOW (4)  PLCC 03+/04+ RESET: An active high signal on this pin will put the chip into an inacti
KP- (15)  N/A The microcontroller instruction set is based on the AT architecture of th
KP0 (17)  schurter schurter dc99 The MAX1698 features digital soft-start and adjustable lossless LED curre
KP1 (89)  rft rft dc86 As shown in the tables on page 3, the KP1008 offers a Zero Delay feature
KP2 (31)  DIP-6 NOTES: 1. All typical values are at VCC = 5 V, Tamb = 25 C. 2. This is
KP3 (22)  COSMO Relay(new original) BiFET operational amplifiers offer the inherently-higher input impedance
KP4 (23)  SHINDEGEN 3W 05+ The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory desi
KP5 (29)  DIP 08+ SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sy
KP6 (5)  DIP 0423+ All devices are manufactured and tested on a MIL-PRF-38534 certi- fied
KP7 (13)  COSMO DIP 07+ Three types of memory are provided on the DS2751 for battery information
KP8 (46)  int int dc02 The KP80524KX366128SL3HQ is an IEEE1394-1995 and P1394a compliant link
KP9 (1)  F   The 5T929 will lock to, and track, a valid CLKIN signal; LOCK wil
KPA (13)  KINGBRIGHT . 02+ Allows Safe Board Insertion and Removal from a Live Backplane Controls S
KPB (11)  N/A CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA thr
KPC (56)  00 NOTE: EP circuits are designed to meet the DC specifications shown in the
KPD (5)  KYSEMI 05 The HPR4XX Series uses advanced circuit design and packag- ing technolog
KPE (8)  kingstate kingstate dc00 Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial
KPF (2)  DAC full scale current control. A resistor connected between this pin and
KPH (9)  INTEL PLCC 00+ Single channel 5 V, 3.3 V and 2.5 V operation 5 V tolerant inputs Ind
KPI (4)  KODENSHI 06+   = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A dat
KPJ (7)  KOREANA 05+ The ISO130 is a high isolation-mode rejection, isolation amplifier suite
KPK (3)  N/A 1206 The FCT373T and FCT573T consist of eight latches with three-state outpu
KPL (8)  N/A 1206LED Stresses beyond those listed under "absolute maximum ratings" m
KPM (1)  The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectab
KPP (1)  KODENSHI TOSHIBA is continually working to improve the quality and reliability of
KPR (1)  The DS1258AB provides full functional capability for VCC greater than 4.75
KPS (17)  COSMO SOP-4 07+ The tuning input is typically connected to the output of the PLL loop fil
KPT (87)  N/A N/A 05+ The DS8830, SN55183, and SN75183 dual differential line drivers are des
KPU (2)  Agilents thin-Film Bulk Acoustic Resonator (FBAR) technology makes possi
KPV (4)  N/A TSSOP-8 2004 The algebraic convention, whereby the most negative value is a minimum an
KPY (11)  sie sie dc92   These Darlington arrays are furnished in 18-pin dual in-line plas
KQ0 (90)  HIROSE 06+ n Mask optional for built-in RC oscillator with an   external resis
KQ1 (75)  KOA 2520-100J • Data transfer may be initiated only when the bus   is not b
KQ2 (6)  PRX SOP When the frequencies of SIGIN and COMPIN are equal but the phase of SIG
KQ3 (3)  HIROSE 05+ NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned th
KQ4 (2)  PRX SOP Power Up and Down Recommendations. There are no restrictions on the powe
KQ9 (1)  MOT 98 The KQ9696 is a PLL synthesizer designed specifically for use in AM FM r
KQL (5)  • Buffered Inputs • Typical Propagation Delay: 5.0ns at VCC =
KQT (1)  N/A 0402L NOTES 1 iJA e Thermal resistance between junction and the surrounding en
KQX (1)  PHILIPS PLCC- 07+/08+   The SY89833L is a 3.3V, high-speed 2GHz differential Low Voltage
KR- (8)  The DAC101S101 is a full-featured, general purpose 10-bit voltage-output
KR0 (2)  Notes 1 Pk/pk voltage at Pins 6 and 7 of a 1MHz sine wave derived throug
KR1 (20)  tsl n/a The HT815D0 is a single chip LOG-PCM voice synthesizer LSI with 11.2-sec
KR2 (16)  N/A SSOP The Fairchild Switch FSTU3384 provides 10 bits of high- speed CMOS TTL-
KR3 (8)  PRX SOP The DS1543 is in the write mode whenever WE and CE are in their active
KR4 (4)  PRX SOP The ATA5756/ATA5757 is a PLL transmitter IC which has been developed for
KR5 (2)  ST 07+ FEATURES lOptions :-   10mm lead spread - add G after part no. &n
KR6 (2)  SAMSUNG SOJ44 reliable operation, the stored energy from circuit inductance dissipated
KR7 (2)  PRX SOP ∗ In order to measure at Ta Tj (pulse measurement), fluctuations in
KR9 (8)  PRX SOP Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output
KRA (334)  KEC N/A This document is a general product description and is subject to change wi
KRB (29)  MORNSUN 08+ PCI compatible BusCfriendly architecture including programmable slewCrat
KRC (418)  KEC 05+ SOT23 Input IN1 serves as either the external clock input or the input to the
KRD (2)  KYOCERA 00+ SSOP Codec negative analog output. The DC level is Vcm, and the full-scale ac
KRE (8)  The advantages of low power consumption, I/O flexibil- ity, timer functio
KRF (7)  KYOCERA 96 Device erasure occurs by executing the erase com- mand sequence. This i
KRG (7)  nec nec dc97 A Read Data from Memory (READ) instruction loads the address of the fir
KRH (1)  NIEC TO-3P 05+   The IDT7200/7201/7202 are dual-port memories that load and empty
KRK (3)  PHILIPS VDM = 67% VDRM(max);20 Tj = 125 ˚C; exponential waveform; gate op
KRL (2)  krle krle dc81+ These three terminal positive regulators are supplied in a hermetic metal
KRM (10)  Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambi
KRN (3)  Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7
KRP (53)  PB n/a 01   The inputs are compatible with 5 V and 12 V logic systemsTTL, Sch
KRS (5)  kyocera kyocera dc01 Sending the WREN op-code causes the internal Write Enable Latch to be s
KRT (1)    This device is designed for FM tuning, general frequency control
KRU (1)  On Board 24Mhz Crystal Driver Circuit Can be clocked by an external 24MHz
KRX (37)  KEC SOT-453 8- to 32-bit and 16- to 32-bit word packing options Programmable wait st
KRY (2)    This device contains protection circuitry to guard against damage
KS- (51)  ARLITECH 04 TOSHIBA is continually working to improve the quality and reliability of
KS0 (135)  SAM 85 Notes :   1. H : High ( inactive) L : Low ( active) D : H or L &nb
KS1 (54)  SHARP CAUTION: These devices are sensitive to electrostatic discharge; follow p
KS2 (220)  SOP-8 SOP-8 *This is a stress rating only and functional operation of the device at t
KS3 (28)  F The APA2020A is a stereo bridge-tied audio power amplifier in various 24-
KS4 (16)  SANYO Radiation Hardened up to 1 x 106 Rads (Si) Single Event Burnout (SEB) H
KS5 (896)  HITACHI 00+ DIP-8 Information contained in this publication regarding device applications
KS6 (109)  POWEREX SOP Each device requires only a single 3.0 volt power supply for both read a
KS7 (335)  91 For applications where efficiency is a prime consideration, the buck cont
KS8 (391)  SAMSUNG SSOP16 04+ the next cycle. For conditional or multifunction instructions, there are
KS9 (55)  SHINDENGEN SOT-252 04+ The LM117 series of adjustable 3-terminal positive voltage regulators i
KSA (403)  FAIRCHILD 05/06+ The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable (OE) i
KSB (140)  FAICCHILD TO-126 05+ In all of the above scenarios, the digital output from the converter is
KSC (760)  FAICCHILD TO-220 05+ Notes: 1. Specifications subject to change without notice. 2. All dimen
KSD (264)  FAIRCHILD 06+ These pins form a 5´8 keyboard matrix which can perform keyboard i
KSE (203)  FAICCHILD TO-126 05+ The error amplifiers exhibit a common-mode voltage range from C0.3 V to V
KSF (33)  NIEC TO-3P 08+ PERFORMANCE CHARACTERISTICS   High performance   - Access tim
KSG (6)  PRX SOP The LTC®4210 is a 6-pin SOT-23 Hot SwapTM controller that allows a bo
KSH (104)  FS 07+ Available in the Texas Instruments NanoStar and NanoFree
KSI (5)  00 - Input pin for current sensing. Using   the sum of drain-source vol
KSJ (7)  The KSJ0M011 Series of quartz crystal oscillators provide enable/disable
KSK (32)  SAMSUNG/KEC SOT-23 07+(ROHS) EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of e
KSL (26)  TO-92 2001 Ultra Low Current Consumption Upgrade and Compatible to the LMX2370 2.
KSM (45)  03+
KSN (9)  MINI 0623+   Input-Output Enable, asynchronous input, active LOW. Controls the
KSP (170)  Note 2: The Absolute Maximum Ratings are those values beyond which the sa
KSQ (14)  NIEC TO-3P 04+ The line impedance presented by the Line Driver circuitry is determined by
KSR (175)  FSC SOT-23 06+ROHS The BS616LV1013 is a high performance, very low power CMOS Static Random
KSS (63)  OTAX 07+ Data is read from the KSS22T by using stan- dard microprocessor read cy
KST (196)  KEC SOT-23 04+ rupt input with pull up (23 pins only). 3 of the digital I/O pins serve
KSU (4)    Pb−Free Packages are Available*   Integrated Power Swit
KSV (28)  96 Figure 1 shows the waveforms associated with the commu- tation decoder lo
KSW (5)  MINI 08+   The 17510 can operate efficiently with supply voltages as low as 2
KSX (5)  PHILIPS Information furnished is believed to be accurate and reliable. However, S
KSY (7)  2008 At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6   perfo
KSZ (92)  MICREL Moving the data from two groups of registers to four common output buse
KT- (8)  K DIP20 05+ The OPA675 and OPA676 are wideband monolithic operational amplifiers wit
KT0 (2)    Please be aware that an important notice concerning availability,
KT1 (109)  C&K SMD 4 ♦ 640kHz/1.2MHz Current-Mode Step-Up Regulator   Fast Transie
KT2 (40)  SAMAUNG DIP 07+ VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω 1% to VCC - 2V,
KT3 (25)  LINEAR 05+ Each timer has one bidirectional pin and four registers that implement i
KT4 (11)  N/A 15 The CY74FCT16841T and CY74FCT162841T are 20-bit D-type latches designed
KT5 (18)  PRX SOP For best results, an Xtal oscillator design should drive the clock inverte
KT6 (12)  KEC ZIP-42P The CMOS bq3287E/bq3287EA is a low-power microprocessor periph- eral pro
KT7 (5)  KTC 12 Description MULT0 (Pin 43) Value. This bit is Read Only. Reserved Contr
KT8 (61)  VIA . Turbo codes improves a transmission link by an additional gain of 2 to 3
KT9 (14)  N/A 01+ TO-3 A fixed 1.4MHz operating frequency ensures operation outside the DSL freq
KTA (500)  TO92S KEC 03+ The output enable multiplexer (MOE) controls the output enable signal. Ea
KTB (76)  KEC SOT-89 06+ The LCX373 contains eight D-type latches with 3-STATE stan- dard outputs
KTC (832)  KEC TO-92 00+ To compensate the variation in production there is a fine adjust for each
KTD (131)  KEC TO-220 07+ Operate From 1.65 V to 3.6 V Specified From C40C to 85C, C40C to 125C, a
KTE (1)  KINGSKY PLCC 04+ The TPS2074 and TPS2075 provide a complete USB hub power solution by in
KTF (1)  CTS 03+ Vcc = 5.0V10%, TA = 0C to 70C (Normal), unless otherwise noted   -7
KTH (3)  The HYM72V16M636B(L)T6 Series are 16Mx64bits Synchronous DRAM Modules. The
KTI (4)  kingbright kingbright dc04 These devices feature a guaranteed maximum TTB window specifying all oc
KTJ (1)  The HD74LV1GT08A is high-speed CMOS two input AND gate using silicon gate
KTK (65)  55 MODULE NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. The increa
KTL (13)  PHI The memory has a capacity of 2605056 bit. It is organized as 212 rows by
KTM (20)  TQFP-80 The CCR-33 Switch is a broadband, SPDT, electromechanical, coaxial switch
KTN (61)  KEC 00+ The LM2462 is a high voltage monolithic three channel CRT driver suitabl
KTO (1)  The DSP56F801 is a member of the DSP56800 core-based family of Digital Si
KTR (5)  This power MOSFET is manufactured using an innovative process. This adv
KTS (34)  SIEMSENS TSOP-28P 6+ • Design Flexibility   Common Anode or Common   Cathode
KTT (1)  - DIP 07+/08+ The primary application of the transceiver is to provide high-speed I/O d
KTV (2)  TOKO 02+ The ICSI 4400 Series is a 4,194,304 x 4-bit high-performance CMOS Dynamic
KTW (1)  KEC 02+ The 138 can be used as an eight output demultiplexer by using one of th
KTX (23)  KEC SOT-563 05+ † Stresses beyond those listed under absolute maximum ratings may c
KTY (120)  INF Delay Time Range: 3.7 s to 20 h RC Oscillator Determines Timing Character
KTZ (2)  YAMAHA QFP 95+ The KTZ419B-FDY is an integrated driver for an n-channel MOSFET half-bri
KU- (1)  QFP This is the active high output drive signal for the (first) phase A win
KU0 (1)  The Design Browser allows users to select and import precon- figured des
KU1 (30)  SHINAENGEN 7   Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /C
KU2 (2)  Maxims MAX312/MAX313/MAX314 analog switches feature low on-resistance (10
KU4 (5)  新电源/K4F1213/1812 04+/05+ Note 1: The minimum operating voltage is 2.65V; however, the device is gua
KU5 (2)  SHIDENGEN SMB 05+ Blocks A and B typically have an open loop voltage gain of 56 dB, with th
KU6 (9)  INTEL BQFP164 Operating Temperature: - 55C to + 85C. (To + 125C with voltage derating.
KU8 (202)  INTEL QFP132 0638+ Vertical power TrenchMOS Low on-state resistance CMOS logic compatible
KU9 (2)  N/A QFP N/A Valid combinations list configurations planned to be sup- ported i
KUB (8)  Program Strobe Enable: The read strobe to external program memory. When
KUC (1)  The IS93C56-3 is a low cost 2,048-bit, non-volatile, serial E2PROM. It i
KUD (4)  OTAX 07+ Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible
KUE (7)  The KUEP-11A15-120 ARM microcontroller features 2 Mbits of on-chip SRAM a
KUF (5)  HOSIDEN 2001 These amplifiers have a 360-µV input offset voltage, a 17 nV/Hz inp
KUG (1)  The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low Volta
KUH (9)  4. Design your application so that the product is used within the ranges
KUI (1)  During power-on, RESET is asserted when supply voltage VDD becomes higher
KUL (5)  3.1 KSO0~7 These pins are direct output from the 8051 Port1 and dedicated
KUM (11)  Maximum ratings are those values beyond which device damage can occur. Ma
KUN (1)  PLL synthesizer (PLL SYNTH) for generation of the first and second local
KUP (50)  POTLER SOP 02+ Notebook/Desktop/Server applications. High current POL converters. Low
KUR (3)  STM SOP-16 04+ Capacitor #2 - An external capacitor to be connected between this termina
KUS (15)  2008 The PALCE29MA16 has a dedicated CLK/LE pin and one individual CLK/LE pr
KUV (1)  sFEATURES qInput Full-SwingVIN=VSS to VDD qOutput Full-SwingVOM2.7V min
KV- (7)  PANASONIC SOD-523 05+ Address inputs Bank select address Data-input/output Chip select Row
KV0 (2)  TOKO 02+ The TLC3704 consists of four independent micropower voltage comparators
KV1 (260)  TOKO SOT-23 06+ Notes: 3. Not measured 100% in production. 4. POUT measured at PIN cor
KV2 (4)  KILAR DIP 98+ State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design
KV3 (4)  KILAR DIP 99+ The design has been optimized to achieve the high accuracy associ- ated
KV4 (3)  FDS O7+ BVDSSDrain-to-Source Breakdown Voltage-200 ∆BV DSS /∆T J Tem
KV5 (1)  The device provides ultrastable +4.500V output with 0.4500 mV (.01%) init
KV6 (4)  TQFP OXFORD 04+ SelfCTest   The sensor provides a selfCtest feature that allows the
KV7 (3)  Expansion of serial cards beyond four channels is possible using the 8-b
KV8 (3)  INTEL QFP Advanced system features include output slew rate control and user-progr
KVA (13)  FAIRCHILD 05/06+ MH, MR, and MMR compression and decompression are provided in hardware.
KVC (1)  Input voltage. For regulation at full load, the input to this pin must be
KVD (2)  HITACHI 05+ IrDA Data Features • Fully compliant to IrDA physical   layer
KVH (1)  After determining which clock edge to use, a start and stop bit, appende
KVL (14)  MOT SOP No part of this publication may be reproduced or transmitted in any form
KVM (1)  Note 1: Absolute Maximum Ratings are those values beyond which the life
KVP (1)  MOT SOP   The R1170 Series are positive voltage regulator ICs by CMOS proces
KVR (22)  KINGSTON SOP Two data address generators (DAGs) provide addresses for simultaneous du
KVS (4)  koa koa dc97  DVDD is the power supply for the I/O pins while CVDD is the power s
KW- (1)  The MC-7856 is a GaAs hybrid integrated circuit designed to be used as
KW0 (7)  八脚铁帽 08+ The device incorporates auto-calibration and built-in self-test (BIST) ro
KW1 (5)  N/A 0805LED • Avalanche rated parts available • Package with DCB cerami
KW2 (8)  N/A SMB   C Supports both Firmware Hub (FWH) and LPC Memory Read and Write C
KW3 (4)  255 MICREL 05+ State-of-the-Art EPIC-B™ BiCMOS Design Significantly Reduces Power
KW4 (4)  SMD28 00+ • ML22Q54   The ML22Q54 is a speech synthesis device with a 4-
KW5 (1)  † Stresses beyond those listed under absolute maximum ratings may c
KW8 (8)  INTEL BGA 2005   The MC100ES6039 is a low skew 2/4, 4/6 clock generation chip desi
KW9 (1)  Right channel serial data input. Both LDATA and RDATA are assumed to be M
KWD (13)  LAMBDA 00+ This single mode transceiver is a Class 1 laser product. It complies wit
KWE (1)  Always use semiconductor devices within their recommended operating condi
KWF (1)  ONWA DIP 03+ The standard shipping format for serial types includes a lower or upper fa
KWI (1)  INTEL 04+ All typical values are at VCC = 5 V. On products compliant to MIL-PRF-3
KWM (2)  PAN DIP 97+ A LOW strobe on this pin will retransmit the data in the FIFO. This is ach
KWR (6)  ZILOG SOP 99+ This is the gate drive output for the Main FET. The totem pole output ha
KWS (12)  NEMIC-LAMBDA MODULE † Stresses beyond those listed under absolute maximum ratings may c
KWT (2)  N dividers by simply modifying the count length with the preset inputs
KX- (7)  YAMAHA The Status Register is located in the RTC area at address 003FH. This i
KX0 (14) 
KX1 (89)  SMD 95+ Connect to the gate of the external N-Channel MOSFET. A capacitor from thi
KX2 (6)  DIP-18 DESCRIPTION The STi7710 is STMicroelectronics first single chip set-top
KX3 (2)  geyer geyer dc03 2) Short-circuits from the output to VCC can cause excessive heating if V
KX5 (2)  The push-pull converter achieves high efficiency by using two external n-
KX6 (2)  -Port 92 Support -Fast Gate A20 and KRESET Outputs Serial Ports -Two Fu
KX7 (7)  KONY(16.934400) The time periods t1 (low) and t2 (high) are values that are easily read b
KX8 (2)  The HS-0548RH and HS-0549RH are radiation hardened analog multiplexers
KX9 (1)  TOSH 3200 The MPC7455 and MPC7445 are implementations of the PowerPC™ microp
KXA (1)  SOT-223 05+ Circuit diagrams and other information relating to SMSC products are inclu
KXC (1)  The devices are stable with capacitive loads up to 10 nF, although the 6-
KXD (1)  国产 06+ This 16-bit noninverting bus transceiver uses two separate configurable
KXG (2)  Operation of this device beyond any one of these limits may cause permane
KXM (4)  QFN Complete USB Hub Power Solution Meets USB Specifications 1.1 and 2.0 Ind
KXN (21)  cts cts dc98 Unless noted otherwise, all measurements are made with the filter install
KXO (69)  avx avx dc00   The IDT5T2110 is a 2.5V PLL differential clock driver intended for
KXP (56)  Designed for space critical applications, the ADR512 is a low voltage (1
KXS (1)  and 4 to 40 V Low current consumption of less than 0.8 mA Integrated out
KXW (1)  YAMAHA Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups Po
KY- (10)  YAMAHA DIP-20P 1992 The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G mod
KY0 (15)  N/A DIP 06+ TXCLK is an internally derived 1200 or 2400 Hz signal in Internal mode an
KY1 (6)  2008 The RC2207 is designed to operate over a power supply range of +4V to 1
KY2 (1)  The EL2141 is a very high bandwidth amplifier whose output is in differe
KY8 (1)  When reading data via the COUT pin and isolation resistor, the DQ line is
KY9 (5)  DIP 91 NOTES:   1. Dimensions are in inches.   2. Metric equivalents
KYB (2)  Pixel-based resolution with 10-bit RGB outputs Programmable Resolution
KYC (1)  07+ Clock 155.52MHz (LVDS output). Differential outputs for the 155.52 MHz cl
KYN (1) 
KYO (1)  The MBM29DL16XTE/BE are programmed by executing the program command seque
KYP (10)  diotec diotec dc00   Figure 3 shows the timing of the encoder output in short frame mo
KYT (1)  Note: while operation of the CS8920A is possi- ble without the use of a
KZ0 (1)  QFP Beneficial comments (recommendations, additions, deletions) and any perti
KZ1 (2)  ph ph dc86 Channels Selectable Autoskip Mode Integrated Boot Strap Diodes 180 Phas
KZ2 (18)  KE TQFP/100 97+ FUNCTIONAL DESCRIPTION The test set operates in one of three basic modes
KZ3 (12)  GSI SMB Write access are initiated when the following conditions are satisfied at
KZ4 (54)  KAWASKI QFP 02+
KZ6 (8)  9802+ 100KEP circuits are designed to meet the DC specifications shown in the a
KZ9 (1)    FIGURE 5 Transfer Function Display Gain is displayed as the slope
KZA (3)  Pb−Free Package is Available Highly Stable Oxide Passivated Juncti
KZB (1)  N/A QFP 07+ The device is compatible with the JEDEC single power-supply Flash comma
KZE (4) 
KZG (10)  SOP Hynix HYMD564646(L)8-K/H/L series incorporates SPD(serial presence detect)
KZN (1)  mot mot dc98 The KZN6922A is a single-chip Universal Serial Bus (USB) Host Controller
KZT (1)  N/A QFP 07+ When powered from a +5V supply, the MAX4626 offers 0.5 ohms max on-resista
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