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  Mfg pack D/C Descrpion
J.S (1)  MOT 02+ PLCC44 Valid Combinations list configurations planned to be supported in volum
J0- (3) 
J00 (60)  Pulse A A Capacitor Table Table 1-1 identifies the characteristics of capacitors f
J01 (13)  TELEGARTNER na Stapleford™ is a highly integrated, single- chip Ethernet switch wi
J02 (6)  RFMD 1990   The J02014 is a fixed frequency, dual current/voltage mode, swit
J03 (2)  The phase locked loop (PLL) synthesizer is completely integrated, includi
J04 (3)  NEC 光纤 Typ, min, and max values at TA = 25C, full temperature range is TMIN = &#
J05 (2)  N/A module 2005+ These full reels are individually barcode labeled and placed inside a p
J06 (4)  H 01+ PLCC-28 3. The window may also be managed by not allowing the first   SO si
J07 (1)  H PLCC-28 dresses are stable, the address access time (tAVQV) is equal to the del
J08 (4)  H 01+ PLCC-28 Start Condition All commands are preceeded by the start condition, whic
J0B (2)  (*) Our SO-8 package used for Voltage Regulators is modified internally t
J0C (1)  Pulse A A Output termination voltage VTT = 0V for VCC = 2.5V operation is supported
J1- (4)  90 Protect Register Disable (PRDS) The PRDS instruction is a ONE TIME ONLY i
J1/ (1)  additional link was included to isolate the zener diode used to supply th
J10 (42)  SILICONIX TO-92 04+ Parameter TEMPERATURE RANGE   Operating   Storage MAXIMUM CL
J11 (88)  SI S The UCSP is a unique package that greatly reduces board space compared to
J12 (7)  HIT TO-220 OPA688UThis VLA™ (Voltage Limiting Amplifier) has two inputs (VH a
J13 (22)  FSA TO92 0728vgc+ The no-correction window size is 324 ns for DPLL #1 and 32 µs for D
J14 (7)  33 TO252 04+ The Am29F016 device also features hardware sector group protection. Thi
J15 (6)  MITEL PQFP-208 02 These capabilities make the FM25L16 ideal for nonvolatile memory applic
J16 (7)  N The 7640 group, an enhanced family of CMOS 8-bit microcontrollers, offers
J17 (32)  VISHAY TO-92 Notes: (1)Low duty cycle pulse testing with Kelvin connections required.
J18 (6)    3.2 Item requirements. The individual item requirements shall be i
J19 (11)  H 01+ PLCC-28 SPI Serial Memory The memory portion of the device is a CMOS serial EEP
J1A (1) 
J1N (32)  CDWR SOP 8350 Digitally programmable dual function digital inputs. Can be programmed
J-2 (1)  The UC385 is a low dropout linear regulator providing a quick response to
J2- (32)  N/A To use the long frame mode, both the frame sync pulses, FSX and FSR, mus
J20 (25)  FUJITSU DIP-14 07+ Full implementation of CAN protocol specification, version 2.0A and 2.0B
J21 (19)  sil sil dc94   The A3946 is designed specifically for applications that req
J22 (15)  Xout C This pin is the digital output of the X-axis acceleration sensor.
J23 (12)  VISHAY TO-92 The PG terminal for the fixed voltage option devices is an open drain, ac
J24 (13)  N When the output load exceeds the current-limit threshold or a short is pr
J25 (21)  jermyn jermyn dc80+ This center tap Schottky rectifier has been optimized for very low forwa
J26 (9)  SI TO-92 98+ The LEDs are packed in cardboard boxes after packaging in anti-electrostat
J27 (10)  SILICONIX TO-92 04+ CT: The oscillator-programming pin. Only two components are required to p
J28 (9)  Factory locked parts provide several options. The SecSi Sector may stor
J29 (23)  N   and Class C (Exceeding 400 V) per Machine Model • Protection
J2E (1)  PLESSEY DIP8 The HS-6254RH is a Radiation Hardened array of five NPN transistor
J2J (1)  N/A 8/SOT23 05&06 A decode cycle begins immediately after the assigned re- ceive time-slot
J2K (5)  N/A Description The HCPL-354 contains a phototransistor, optically coupled
J2N (35)  FUJI 2008 The MAX7447 4-channel, buffered video reconstruction filter is ideal for
J2P (1)  Programmable options include the length of pipeline (Read latency of 1,2
J2Q (1)  100 天龙伟业 靳先生 The HYM72V16M636H(L)T6 Series are 16Mx64bits Synchronous DRAM Modules. The
J2S (4)  N/A Lead Temperature (1.6mm or 1/16 from case for 10s)+260C (1) Stresses be
J30 (24)  NSC TO-92 94+ The standard supply voltage for notebook computers and other portable equ
J31 (14)  SILICONIX TO-92 04+ NOTES:  7. The hi and lo frequencies can be obtained by connecting
J32 (14)  ST BGA 03 Secured Silicon Sector: Extra 256 Byte sector   Factory locked and
J33 (8)  No part of this document may be copied or reproduced in any form or by an
J34 (9)  and negative supplies separately and add the powers. If the waveform is
J35 (3)  HIT TO-220 Low Loss Replacement for ORing Diode in Multiple Sourced Power Supplies
J36 (9)  TOS SOT-89 05+   The circuit shown in Fig 9 is designed to illustrate the use of t
J37 (5)  TOSHIBA TO-252 04+ † Stresses beyond those listed under absolute maximum ratings may c
J38 (8)  NEC TO-220 03+   The A8282SLB output is set to 12, 13, 18, or 20-V by the VSEL ter
J39 (9)  N/A PQFP-100 00 The processor provides six addressing modes, supporting memory-to-memory,
J3B (1)  The uncommitted output transistors provide either common-emitter or emitt
J3S (2)  NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATING
J3T (1)  PCS 2008  Working Standoff Voltages: 5.5 volts to 171 volts  Metallurgi
J-4 (1)  Bypass all power supplies, as well as the REFERENCE OUTPUT (pin 21), to
J40 (6)  NEC TO252 00+ Power dissipation at 25ºC: 5.0 watts (also see  derating in Fi
J41 (22)  TELEDYNE CAN N/A Offered in 256Mx8bit or 128Mx16bit, the K9F2GXXX0M is 2G bit with spare 64
J42 (7)  MITACHI SOP8 07+/08+   Main CLK(Hz)Under 3.58M14.3M   Operating Voltage(min)2.2V3.6V
J43 (7)  NEC Package drawings, standard packing quantities, thermal data, symbolizatio
J44 (3)  TO-220F 06+ UNLESS OTHERWISE NOTED this document contains PRO- DUCTION DATA informa
J45 (6)  AGILENT 08+
J46 (10)  H 01+ PLCC-32 In order to saturate the power switch and reduce conduction losses, ade
J47 (13)  BOSCH PLCC 2004 Notes: 1. Some failed sectors may exist in the device. The failed sectors
J48 (10)  H 01+ PLCC-28 This device contains circuits to protect its inputs and outputs against d
J49 (5)  N Difference between measured full scale response [(+Fs) - (-Fs)] and the
J4F (1)  The AME8801/8840 family of positive, linear regulators feature low quie
J4S (1)  Play In: The input via SW2 from a voice storage device such as the MX812.
J4T (1)  SAM BGA 05+ Full compliance with the USB Specification v1.1 Dual serial port interfa
J5. (1)  TOS 1) CPD is defined as the value of the ICs internal equivalent capacitance
J50 (14)  97+ In the past 10 years, microprocessors have evolved at such a rate that a
J51 (7)  VISHAY TO-92 05+ DTC provides a means of limiting the output-switch duty cycle to a value
J52 (3)  147 TO252 04+ For example, S/H1 should not be commanded into the sample mode until al
J53 (7)  HITACHI SOT-252 The analog input RGB signals are first sampled by three channels of 8-bit
J54 (8)  H PLCC-28 G.703 2048kHz Synchronization Interface Compliant G.703 64kHz Centralize
J55 (6)  HIT TO220-3 02+ The Rambus RIMM modules are offered in a 184-pad 1 mm edge connector pad
J56 (6)  NEC 光纤 07+/08+ The J5653-0N03 and J5653-0N03 are precision 2.5V regula- tor diodes. Th
J58 (3)  One of the industry's first ultra high-speed, 8-bit data converters with
J59 (6)  NEC 光纤 07+/08+ Stresses above those listed under Absolute Maximum Ratings may cause per
J5A (10)  02+ 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature
J5I (1)  Vo(n) Rem Sense: An external remote sense input is provided for the two l
J5N (2)    Guaranteed Low Skew < 25ps (max)   Very low duty cycle dis
J5S (1)  The Bus Interface Unit (BIU) controls the interface between the on-chip m
J6. (1)  FEATURES 1 pC Charge Injection   2.7 V to 5.5 V Dual Supply +2.7 V
J60 (11)  NEC TO-251 07+ A capacitive load on the regulators output will appear as a short circui
J61 (7)  H 01+ PLCC-28 Three parallel I/O registers with open-drain capability Four baud-rate g
J63 (6)  05+ QFN Devices sold by AMI are covered by the warranty and patent indemnification
J64 (1)  2007 Shunt protection devices clamp voltage peaks at the Output-Pin and VDD-
J65 (35)  NEC SOP 05+ Current Limit Protection Isolation Test Voltage 5300 V RMS Typical RON
J66 (1)  stream and 24 Mbps downstream. This device is ide- al for power and are
J67 (8)  PLCC 04+ Thermal Ground FBAR resonators have a negative temperature coefficient o
J68 (12)  仙童 三极管 The device is powered-up in normal operation mode with the OS in compara
J69 (4)  FSC 03+ TO-3P The value of Ki may also be slightly different at the extremes of the
J-7 (1)  N/A OMRON 05+ The GRM is functionally similar to the switch matrices found in other a
J7/ (1)  N/A 8/QFN 05&06 These electrically erasable programmable memo- ry (EEPROM) devices are
J70 (3)  NEC 光纤 07+/08+ The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiple
J72 (3)  NQRTEL QFP-160 The QDMM provides dedicated data storage resources for the CPU030 in the
J73 (10)  H 01+ PLCC-28 ADV/LD is a synchronous input that is used to load the inte rnal registers
J74 (2) 
J76 (2)  NEC 0004- The counter is loaded digit by digit corresponding to the digit strobe o
J77 (1)  N/A TI 04+ These ICs are analog stereo enhancement processors. They use patented Q Xp
J78 (1)  div div dc80+ By integrating a rich set of industry leading system peripherals and mem
J79 (4)  H 01+ PLCC-28 During the switch between active and standby condi- tions, transient curr
J7A (1)  AD • Universal Asynchronous Receiver/Transmitter (UART) Module  
J7T (1)  Teccor Electronics is the proprietor of the SIDACtor®, Battrax®, a
J8- (1)  98 PCM input C 102 dB of Stopband Attenuation C Supports Sample Rates up to
J80 (5)  Pulse A A The HT24LC04 uses the A2 and A1 inputs for hard wire addressing and a tot
J82 (5)  H 01+ PLCC-28 The A-to-B enable (CEAB) input must be low to enter data from A or to o
J83 (3)  NSC SOP-8 0026+ OPTI-LOOP compensation allows the transient response to be optimized over
J84 (6)  UPD SOP The STA304A Digital Audio Processor is a single chip device implementin
J85 (1)  0251+ SOP8 Notes:  2. The voltage on any input or I/O pin cannot exceed the po
J86 (2)  H PLCC-28 Reset (active high) - A longer than 40 ns HIGH pulse on this pin will res
J87 (14)  H 01+ PLCC-28 ELAN Microelectronics products are not intended for use in life support a
J88 (1)  • Low current consumption by CMOS process with high   dielect
J89 (1) 
J8M (1) 
J90 (4)  SILICONIX TO92 Note7: CPD is defined as the value of the internal equivalent capacitance
J91 (4)  DIP Trisils are not subject to ageing and provide a fail safe mode in short
J92 (13)  H 01+ PLCC-28 Depending on the type of information to be switched, the MT8985 device can
J93 (4)  NS 0026   The 33981 can be controlled by pulse-width modulation (PWM) with a
J94 (16)  N/A NSC 04+ Bus Command/Byte Enable: During the address phase these signals define th
J95 (7)  LINEAR O7+ Three-phase bipolar drive Direct PWM drive (controlled either by control
J96 (4) 
J98 (3)  H PLCC-28   Operating air gap is dependent on the available magnetic field. Th
J99 (5)  MX
J9G (1)  The attack and decay time constant of the AGC is set by the internal se
JA- (2)  The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_
JA0 (7)  N/A 1210   Low profile 0.047" [1.19mm] maximum thickness.   Self s
JA1 (33)  飞利浦 Hynix HYMD116645B(L)8-M/K/H/L series is designed for high speed of up to
JA2 (2)  MITSUBIS 04+ These two schemes are shown in the 9310 data sheet The TC output is subj
JA3 (30)  JAALAA QFP 04+ Characteristic On-State Voltage Under-Voltage Lockout Over-Voltage T
JA5 (7)  JAALAA This material and the information herein is the property ofFuji Electric
JA6 (4)  298 N/A 99 • Hot-swapping and hot-docking (low resistance for PCI and  
JA7 (1)  . . . employing the Schottky Barrier principle in a large area metalCtoCs
JA8 (7)  TQFP144 08+ ESD damage can range from subtle performance degradation to complete dev
JA9 (7)  2 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature
JAA (15)  N/A 1206 The host system can detect whether a program or erase operation is comp
JAC (5)  RAKON 2005+ The JAC32-UM1SJ(5333R09-005-RE is a 16-bit bidirectional transceiver desi
JAD (7)  MATSUO 1206-1A 05+ The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set in
JAE (3)  N/A   The MSK 620(B) is a very high frequency video amplifier system cap
JAG (29)  GENE 06-07+ The customized communication expansion connectors on the EVB555 allows ac
JAH (9)  N/A Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups
JAJ (1)    These devices are designed primarily for highCefficiency UHF and
JAL (2)  The HY29F040A can be programmed and erased in-system with a single 5-vo
JAM (2)  MIT SMD 04+ If the DS1481 determines that it is the last device on the port it ignor
JAN (5144)  MOT CAN In-target operation Up to 20 breakpoints Single-step or full-speed opera
JAP (12)  N/A QFP-48 03+ +3 Volt single power supply Low power CMOS design 4-Wire serial interfac
JAS (7)  JEL (LX)high-frequency Cntrl (Bump A1): Shutdown control pin. When VCntrl is 1.4V, the LM3502
JAT (2)  03 Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
JAV (1)  Note 1: Supply current, output power, and efficiency are greatly dependent
JAW (15)  N/A A: The value of R JA is measured with the device mounted on 1in FR-4 boar
JAX (1)  Please be aware that AKE products are not intended for use in life suppo
JAY (2)  29 MICROCHIP 99+ The HYM7V65401B Q-Series are Small Outline Dual In-line Memory Modules sui
JB0 (2)  GPS PLCC The ADS5545 is a high performance 14-bit 170-MSPS ADC. Using an internal
JB1 (15)  PHILIPS 2008 a mechanical trimmer). When this permanent setting is achieved, the valu
JB2 (1)  N/A   The ELM312 is an interface circuit for use between high speed lo
JB4 (4)  JB DIP14 0134+ 1/ Stresses above the absolute maximum rating may cause permanent damage
JB9 (12)  ST n Drives up to 7 LEDs with up to 20mA each n LEDs controlled in 2 Disti
JBD (6)  MOT • A/D converter   • 10-bit resolution. 10 channels  
JBG (2)  ST 02+ The INT5130 IC is an integrated powerline MAC/PHY transceiver providing No
JBH (1)  A buffered output-enable (OE) input can be used to place the eight output
JBL (9)  MOT PLCC28 03/+04+ This new generation of trench MOSFETs from Zetex utilizes a unique struc
JBP (11)  TI Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260 (4) Stre
JBS (2)  The JBSFET1 is a member of the 56800E core-based family of hybrid control
JBT (4)  N/A N/A FO transceivers The widely used Time Division Multiplex (TDM) transmissio
JBV (6)  0719+ Cr-NiV-Ag ( 1kA-2kA-2.5kA ) 99% Al, 1% Si (0.004 mm) 0.181" x 0.
JBW (2)  TYCO Each ACEX 1K device contains an embedded array and a logic array. The em
JBX (4)  The HMS9xC7134 is a single-chip microcontroller of the 80C51 family, whic
JBY (1)  ST IC晶片 99+ G5131-25T21Uf G5131-26T21Uf G5131-27T21Uf G5131-28T21Uf G5131-29T21Uf
JC- (4)  01+ SOP Note A: All Characteristic data in the above graphs has been developed fr
JC0 (44)  PULSE SOP 603 C Serial port hardware handshaking with CTS,   RTS, ENRX, and RTR s
JC1 (33)  N/A An inhibit function is provided for HR150 converters when the inhibit in
JC2 (76)  Note 1: Absolute maximum ratings are DC values beyond which the device m
JC3 (8)  PHILIPS TO-92 Signal Processor (DSP): - SM/SMJ320VC33-150   - 13-ns Instruction C
JC4 (1)  PROGRAM MEMORY Program memory consists of 768 x 8 ROM These bytes of RO
JC5 (17)  The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC
JC6 (7)  Note 3:   Shut Down (SD) to transmit enable is the time required fo
JC7 (1)  This manual describes the characteristics of typical optocouplers. Also i
JC8 (1)  INTEL BGA 0717+ Hardware Reset, active Low. Provides a hardware method of resetting the
JC9 (1)  *1: Is1 is specified as the 5% drop point of output voltage VO on the con
JCA (1)  The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System
JCB (7)  N/A 0603B • Supports Cypresss Ultra37000™, Ultra37000V™,  
JCC (18)  Unlike conventional page-mode DRAMs, the column-address buffers in this d
JCE (4)  JVC QFP100 2007+ Sync detect C Output to signal when the link is active or inactive. The l
JCG (2)  JSW 00+ DIP-28 These PIN / Preamplifier combinations are coupled into a custom quantizer
JCH (1)  2. An overtemperature indicator is implemented by carrying out a  
JCI (26)  MICROCHIP SOP-7.2-18P 6+ Power Management and Signal Level Translators for Two SIM Cards or Smart
JCL (1)  MAXIM 16P The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks i
JCM (16)  SMD 00+ An internal power-on reset (POR) and an enable input (EN) control the ope
JCN (3)  SANYO The next concern is getting the input signal to the part and the output
JCO (29)  jauch jauch dc01 For A-to-B data flow, the device operates on the low-to-high transition o
JCP (74)  1) Worst case package. 2) Max number of outputs defined as (n). Data in
JCR (1) 
JCS (3)  Protection features of this controller IC include a set of sophisticated
JCT (1)  MHS O7+ Manchester encoding and decoding is made possible through the integrate
JCU (4)  TEMIC 2008
JCV (10)  JVC SOP/28 98+ Notes: 1. Test conditions assume signal transition times of 5 ns or less
JCX (1)  CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
JCY (38)  JVC TSSOP 01+ The subsequent analog signal is sent to the on-chip line driver where th
JCZ (2)  01 The HYM72V16M636T6 Series are 16Mx64bits Synchronous DRAM Modules. The mod
JD- (6)  PHILIPS DIP 1997 Instruction Structure The byte following the address contains the instru
JD0 (6)  JRC 2008 *The minimum value of dc input voltage is 8 V when the output is less t
JD1 (14)  JEAN 00+ The AT40KAL FPGA family is capable of implementing user-defined, automati
JD2 (3)  INTEL 03+ This pin establishes the reference current for the internal current steeri
JD3 (30)    C Sixteen 2-Kbyte (16-Kbit) Zones   C Self-timed Write Cycle
JD5 (16)  FEATURES lOptions :-   10mm lead spread - add G after part no. &n
JD6 (1)  Package thermal resistance is 40 C/W under the EIA/JESD51-3 compliant PCB
JD9 (6)  TOSHIBA TQFP 07+ • Generates 5 Regulated Voltages   - Synchronous Buck PWM Cont
JDC (10)  MINI 08+ Common Flash Memory Interface (CFI) The SST39VF160Q/VF160 also contain t
JDH (3)  TOSHIBA 05+ Collector-Emitter Voltage BVCEO Emitter-Collector Voltage BVECO Collec
JDI (1)  ActiveThe device operates at full speed using the high- frequency clock.
JDJ (1)  The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced
JDL (8)  FUJ 1989 DIP   TKVZat   %/K Min.Max.  00.07 0.030.08 0.030.08 0.05
JDM (4) 
JDP (18)  Toshiba 06+ The Low Power SDRAM provides for programmable options including CAS latenc
JDS (1)  The write cycle is the time from a valid stop condition of a write sequen
JDT (1)  Parameter DC INPUT CHARACTERISTICS   Input Voltage Range   In
JDU (2)  The AUP family is TIs premier solution to the industrys low power needs i
JDV (30)  TOSHIBA SOD-423 This is the connection to the emitter of the onCchip NPN power transistor
JDX (12)  The Flash memory on the A128 devices is a nonvolatile, electrically erasa
JE- (12)  JE SOP-8 07+ At turn-on, the external gate capacitor of the N-Channel MOSFET is charge
JE1 (15)  TO-92 MOTO 03+ Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups Th
JE2 (3)  ON TO-126 N/A   During normal operation, a synchronization pulse acts as the cloc
JE3 (8)  MOTOROLA TO92 First ASIC replacement FPGA for high-volume production with on-chip RAM
JE5 (1)  Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 St
JE6 (2)  FUJIXEROX QFP100 NOTES: 1. pin #9 = pin #17(internally connected). 2. Do not tie up Vp an
JE7 (3)  Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) s
JE8 (1)  NEC Note 1) The specified condition Tj = 25C means that the test should be ca
JE9 (4)  NEC TO92 99 Notes: 1. Operation of this device in excess of any one   of these
JEA (2)  PHILIPS 96+ The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire t
JEB (2)  MINI 08+ The function of the configuration unit is to transmit decompressed data
JEC (7)  APM SOP-8 N/A NOTES: 2. When the differential input voltage (VI+ C VIC) is less than or
JEE (3)  NOTES: A. CL includes probe and jig capacitance.   B. Waveform 1 is
JEF (3)  1. This device series contains ESD protection and exceeds the following t
JEG (1)    High incandescent lamp turn-on (in-rush currents) can contribute
JEI (1)  HY57V161610D is offering fully synchronous operation referenced to a posit
JEJ (1)  HOSIDEN The receiver is manufactured in a compact, 16-pin sur- face-mount packa
JEL (2)  The thermal shutdown debiases the output amplifier when the junction tem
JEP (3)  MINI 08+ Posistive excursions of input voltage may exceed the power supply level.
JES (4)  SANYO PB-FREE 05+ The primary function of the receiver is to recover clock (RCLK) and dat
JET (14)  JET DIP N/A Note: Capacitors with K tolerance (10%) and SL characteristics must be us
J-F (1)  1.2.2 Many Single-Byte, Multifunction Instructions The COP8 instruction
JF0 (7)  Parameter SENSOR INPUT   Measurement Range   Nonlinearity &n
JF1 (13)  CAL TO-92 00年   The MC74VHC1G04 input structure provides protection when voltages
JF4 (2)  Sorry about that! The thing to remember is that the triangle and sine wa
JFA (1)  The AT40KAL FPGA family is capable of implementing user-defined, automati
JFB (1)  (1) The marketing status values are defined as follows: ACTIVE: Product
JFC (4)  N/A   C High-performance 32-bit RISC Architecture   C High-density
JFD (2)  The LM3310 is a step-up DC/DC converter integrated with an Operational
JFJ (4)  HOSIDEN DIP3 00+ Conditions/Comments1 Maximum clock frequency SCLK cycle time SCLK high
JFM (7)  SOP 4091 • High current sink/source 25 mA/25 mA • Three external int
JFP (3)  The PKF series of DC/DC power modules are manufactured in surface mount t
JFT (2)  W 3脚大铁帽 08+ Function Positive Supply. Bypass to GND with a 100 pF or greater single-
JFW (14)  N/A N/A N/A
JG0 (3)  Pulse A A DRVOUT: (gate drive) The output drive for the boost switch is a totem-pol
JG1 (3)  06+ The SR (refer to Figure 4) contains the interrupt mask (seven levels avai
JG2 (4)  BGA 4 DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Cur
JG6 (8)  SAM 95
JG7 (3)  MB QFP208 98+   The switching characteristics of a MOSFET body diode are very imp
JG8 (23)  INTEL O7+ The clock input is a gated-OR structure which allows one input to be us
JGB (2)  The power switch has full over-current protection. Whenever the current l
JGC (11)  MOTOROLA SOP20 04+ † Pulsed-output patterns are tested during  AC switching at 2
JGE (1)  This pin is the power side of the external inductor and must be connected
JGG (3)  ST   Standby as low as 55 mA (typ) Mailbox function for message passing
JGN (2)  The Discrete Products Operation of Fairchild has developed a series of
JGR (3)  PAN 7M-100 05+ Efficiency at 3-A Continuous Output Current Uses External Lowside MOSFET
JGX (1)  100 天龙伟业 靳先生 Notes: 1. TC is defined as case temperature, the temperature of the under
J-H (2)  (Before using this chip, take a look at the following description note, it
JH- (11)  M/A-COM The ADSP-21262 continues SHARCs industry leading stan- dards of integrat
JH0 (1)  N/A N/A Note: 1 H = High Signal Level   L = Low Signal Level   Z = Hi
JH1 (5)  Panasonic Relay(DZ) *90707B ‧Telecommunications (PC, Electronic notepad) ‧Measuring and T
JH2 (1)  Each resistor array and comparator has associated with it a wiper count
JH3 (1)  NAIS RELAY 06+ The bq2050 measures the voltage differential between the SR and VSS pins.
JH4 (1)  • Packaged in 16 pin SOIC or TSSOP • Uses fundamental 10 -
JH5 (2)  The function of this IC series JH56R20.48MHZ is to accurately reset system
JH9 (1)  NS QFP 01+ The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid w
JHA (1)  MICRO SSOP 05+   : When assigning bit operand, K1~K4 are used for 16-bit and K5~K8
JHB (3)  ZTE PLCC • Photo detector and preamplifier in one package • Internal
JHC (1)  NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than
JHF (3)  N/A A doubled buffered serial data interface offers high-speed, 3-wire, SPI
JHG (3)  Note: CPD is defined as the value of the internal equivalent capacitance
JHK (1)  TOSHIBA is continually working to improve the quality and reliability of
JHP (2)  Bay Linear products are not authorized for and should not be used within
JHS (4)  M/A-COM Note 12: Ripple voltage should measured at COUT electrode on good layout
JHT (1)  Resolution: Accelerometers can be used in a wide variety of low g applica
JHV (1)  Notes:  1. PD indicates an internal pull-down and PU indicates an i
JHY (1)  Programmable) versions are available (COP8SGx7 Family). Erasable window
J-I (1)  Transmit data. These inputs carry 10-bit parallel data output from a prot
JI- (5)  PTC SOP28 03+   Mark/space ratio for the SCLK input is 40/60 to 60/40.   Mea
JI0 (1)  2004 SMD The ADSP-21991 integrates the fixed point ADSP-219x family base architec
JI5 (1)  TOSHIBA 00+ 芯片 o dcOutput Duty Cycle48 NOTE 1: Defined as skew between outputs at the
JIA (1)  Expansion Memory (Optional in 176-pin packages) Three address zones for
JIC (3)  MOT . A and B Ports Up To −2 V Bidirectional Data Flow, With Near-Zero P
JIE (1)  MOT MQFP208 9503 contains an Erase Suspend feature. This feature will put the Erase on h
JIL (1)  TI 05+   Parameter Forward Transconductance Total Gate Charge Gate-to-S
JIM (1)  TOSHIBA Information furnished is believed to be accurate and reliable. However, S
JIP (1)  namae namae dc00 • Thyristor for line frequency • International standard pac
JIS (1)    Thaler Corporation has developed a nonlinear compensation network
JIT (92)  fox fox dc98 The CKE input determines whether the CLK input is enabled. The next risin
JIV (1)  N/A N/A 2004 interoperability and reliability risks. Integrated memory reduces compone
JJ0 (3)  ST SQL 00+ • Burst Mode Operation to Reduce the Power Consumption   in t
JJ1 (1)  It is our intention to provide our valued customers with the best documen
JJ3 (1)  MOTOROLA DIP-8 07+/08+ At the output of all CCD's, transported pixel charge (electrons) is conv
JJ7 (1)  DIP The EL5172 and EL5372 are single and triple high bandwidth amplifiers des
JJM (2)  NAIS 原装 08+ HIGH ENDURANCE: C 100,000 Erase/WRITE Cycles of Flash   Memory C
JJN (1)    A major problem in attempting to suppress impulse noise in an AM
JJS (2)  55 MODULE The AD5241/AD5242 provide a single-/dual-channel, 256- position, digital
JK- (1)  NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't
JK0 (16)  Pulse A A Note: Stresses greater than those listed under MAXIMUM RAT- INGS may c
JK1 (3)  Panasonic Relay(DZ) *90218W Information furnished by Analog Devices is believed to be accurate and re
JK4 (1)  RESET is asserted and the condition is latched until VHTH > VTH. Reset
JK5 (1)    Optocoupler, precision reference and error amplifier in sing
JK6 (5)  Note 11: The given JA is for an HWD2119 package in an LDA08B with the Expo
JK8 (6)  NS PLCC 00+ max. This allows a value of 2.19 ms for tQUIET, satisfying the minimum re
JK9 (3)    1.1 Scope. This specification covers the performance requirements
JKE (1)  After D/CLK and RES have been set, the time slot begins when ENI is dri
JKM (1)  JAT 0603-151 05+ These edge-triggered multivibrators feature output pulse-duration control
JKS (1)  ?? Use multilayer PCBs to minimize power and ground inductance Keep clock c
JKX (2)  The decoder includes a brightness, contrast and saturation control circ
J-L (7)  JEPICO 04+ On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external so
JL- (11)  QFP120 4. Values for two Turn-On loss conditions are shown for the convenience o
JL0 (2)  SPANSION PBGA The LAN91C100FD is designed to facilitate the implementation of first gene
JL1 (18)  Note 2: Electrical Table values apply only for factory testing conditions
JL2 (5)  TI DIP Both current generators may be driven using an on- board temperature se
JL5 (2)  NSC These P-Channel MOSFETs from International Rectifier utilize advanced p
JL8 (3)  INTEL 07+   For convenience, a 4MHz crystal oscillator has been used rather th
JLA (3)  MITEL 2007 The Programmable Interconnect Array (PIA) solves inter- connect limitati
JLC (37)  MOTOROLA 2008 The ZL30414 has a built-in LOCK detector that measures frequency differenc
JLD (1) 
JLI (3)  JINGLUN SOP-7.2-24P 6+ ISSI reserves the right to make changes to its products at any time witho
JLJ (1)  2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. Low power consumpt
JLL (2)  天达 圆柱 DESCRIPTION The SuperMESH™ series is obtained through an extreme
JLM (1)  NEC N/A 2004   JLM031F33KR110543933392 is a CMOS LSI designed for a PLL frequency
JLP (2)  ZILOG DIP 03+ The information provided herein is believed to be reliable; however, BUR
JLS (5)  SMK Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or E
JM- (3)  N/A NKK 04+ Room = 25C, Full = as determined by the operating suffix. Typical values
JM0 (7)  ATQT 模块 02+ G2A or G2B is held high, the decoding function is inhibited and all the
JM1 (11)  Panasonic Relay(DZ) *90406F Output 1 (OUT1) can deliver a maximum of 40 mA, from a 1-V input, with ou
JM2 (29)  Jmicron 08+ • 1024 Resistor Taps C 10-Bit Resolution • SPI Serial Interfa
JM3 (2090)  JRC ZIP ZIP CMOS transistor switch. Only one tap point for each potentiometer is co
JM4 (11)  NSC 2002 JM4013BBDA: 16-bit resolution JM4013BBDA: 24-bit resolution Power  
JM5 (16)  NSC 2005
JM6 (1)  • Wide frequency rangeC80.0MHz to 180.0MHz • User specified t
JM7 (3)  N/A DIP Chip Select Input. CS HIGH, deselects the device and the SO output pin is
JM8 (11)  INTEL O7+
JMA (11)  1700 When the Deserializer detects edge transitions at the Bus LVDS input, i
JMB (6)  N/A ELECTRICAL CHARACTERISTICS Test conditions T amb = C40C to + 85C, VCC =
JMC (3)  EPSON QFP 1995 The HMJ1 is a high dynamic range, GaAs FET mixer. This active FET reali
JMD (2)  SANYO SMD 3 Infineon Technologies Components may only be used in life-support devices
JMG (5)  TECH (LX)high-frequency This module generates a slow System Clock (32.768 kHz) from an optional
JMI (1)  LEG 98+ These circuits are completely compatible with most TTL families. Inputs a
JMK (74)  TAIYO . 09+ Wire-bond and flip-chip packages are available. Table 4 and Table 5 show
JML (1)  This pin is capable of driving a standard CMOS or TTL load. No external
JMM (1) 
JMP (1) 
JMS (37)  MINI 08+ Current setting resistor (band-gap sense voltage). This terminal is conne
JMT (4)  99+   Unidirectional zener diode transient suppressors are recom- mende
JMV (1)  N/A VOUT = 1/2 VIN (Supply Splitter) Adjustable and Symmetrical Sink/Source
JN1 (6)  MATSUSHI RELAY 06+ The key parameters of a damper diode are the peak forward voltage (VFP)
JN2 (7)  JN QFP 2.5V to 20V Step Down Achieved Using Dual Input Output Voltage down to
JN3 (2)  Each data transfer is initiated with a Start condition and terminated w
JN4 (2)  Bay Linear products are not authorized for and should not be used within
JN5 (10)  PERIPHERALS 32-Bit, 33 MHz, 3.3 V, PCI 2.2 Compliant Bus Interface &nbs
JN6 (2)  The STR73xF requires an external 4.5 to 5.5V power supply. There are two
JN9 (21)  JRC DIP16 99+ Chip Enable, Output Enable and Write Enable sig- nals control the bus o
JNA (2)  NS dip/sop 0728vgc+ The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of da
JNC (1)  NEC DIP 91   This series of Zener diodes is packaged in a SOD−323 surface
JND (1)  The AC/ACT574 consists of eight edge-triggered flip-flops with individua
JNI (5)  JNI BGA 00+ NOTES (a) For a device surface mounted on 25mm x 25mm FR4 PCB with high
JNM (4)  N/A QFP-100 Microchip offers a QTP Programming Service for factory production order
JNR (4)  joyin joyin dc00 [CAUTION]  The specifications on this databook are only given for
JNS (1)  The ICS660 provides clock generation and conversion for clock rates com
JO- (1)  QUICKLOGIC QFP 04+ This is the timing reference frequency which is the transmit frequency d
JO1 (2)  (LX)high-frequency The AHCT244 devices are organized as two 4-bit buffers/line drivers wit
JO2 (3)  2008 with serial programming. The flags are updated according to the timing mod
JO3 (5)  (LX)high-frequency • Industrial applications for daisy chaining   multiple devic
JO7 (3)  Fully asynchronous operation from either port Separate byte controls fo
JOB (2)  TAI 0805-60R 05+   1.1 Scope. This specification covers the performance requirements
JOC (1)  ST TELECOM 02+ • High-speed access times:   8, 10, 12 and 15 ns • Hig
JOD (1)  TOKO 03+ SOP
JOJ (2)  XILINX PLCC-20P 02+ CEL certifies, to its knowledge, that semiconductor and laser products de
JOM (1)  If the centering error is less than 25 ppm, no adjustment is needed. If
JOO (1)  JRC Choice of three bright colors Standard T-1¾ package Small mecha
JOS (1)  XILINX PLCC-20P 02+ The input signal at pin DATA produces amplitude shift key (ASK) modulati
JOY (1)  The Intersil ISL84521CISL84523 devices are CMOS, precision, quad analog
JP- (2)  02+ SOP Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7
JP0 (2)  Spartan-IIE devices deliver more gates, I/Os, and features per dollar t
JP2 (5)  QFN 04+ These switches are fully specified with +5V, and +3.3V supplies. With +
JP3 (2)  Intersils Satellite Applications(SAF) devices are fully tested and guar
JP4 (1)  The WRAL instruction writes data into the entire 256´16 or 512&acut
JP5 (11)  ANAREN NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may
JP6 (1)  Two video control output signals (VIDCTL[1:0]) provide digital control
JPA (5)  PAN TO-92 The Hynix HYM71V16M655B(L)T6 Series are 16Mx64bits Synchronous DRAM Module
JPC (12)    Power Outputs (OUT A, OUTB, and OUTC). The power outputs of the A
JPD (11)  SOP 626 This pin is a high-voltage input used to wake-up the device from sleep mo
JPH (1)  TAITO 00+ DIP-40 The DP8417 8418 8419 8419X represent a family of 256k DRAM Controller Dr
JPJ (11)  The 64K bytes of flash EEPROM program memory are used to store the applic
JPM (5)  N/A 08+ NOTES: 11. Measured using Eastman Kodak neutral white test card having 90
JPN (2)  MAT DIP 1992 The open-collector overtemperature flag output (TFL) is fed back to
JPP (1)  * On products compliant to MIL-PRF-38535, this parameter is not productio
JPR (2)  N/A The UCC5672 is used in multi-mode active termination applications, wher
JPS (17)  MINI 08+ Pixel select C Selects between one or two pixels per clock output modes.
JPV (3)  N/A QFP-48 00 Packaged in the SOD523 package this addition to the Zetex Low Leakage Sc
JQ1 (30)  Panasonic 原装 08+ The attached spice model describes the typical electrical characteristics
JQ2 (1)  NAIS 95 † Stresses beyond those listed under absolute maximum ratings may c
JQC (1)  This device contains two independent positive pulse trig- gered J-K flip
JQG (1) 
JQL (2)  PAN QFP/304 The NT7702 is a 240-bit output segment/common driver LSI suitable for dri
JQM (1)  PANASONIC N-Channel Synchronous Rectifier MOSFET Driver Programmable Timeout Rever
JQS (1)  goodsky goodsky dc99 (1) Package drawings, standard packing quantities, thermal data, symboliz
JQX (11)  hongfa hongfa dc05 BENEFITS EMI / RFI noise suppression Required line termination for US
JR0 (3)  VOLTRONICS 03+ • SOP (Small Outline Package) • Isolation Test Voltage, 375
JR1 (6)  PANA 继电器 01+ The H8/3048 Series is a series of high-performance microcontrollers that
JR2 (4)    The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synch
JR5 (1)  WRLL 5P MATERIAL: Units are encap- sulated in a low thermal resis- tance moldi
JR6 (1)  Testing of the switching parameters is modeled after testing methods spec
JRC (463)  N/A N/A N/A The MAX2640 and MAX2641 are ultra-low-noise ampli- fiers that operate wit
JRE (2)  and other linear applications in the 1800MHz to 2000MHz band.   Th
JRM (1)  JRC SOP 06+ Notes:  1. TA is the instant on case temperature.  2. See the
JRN (10)  Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte
JRS (1)  N/A SMK 05+ The VTV 300 is a COMMON EMITTER transistor capable of providing 30 Watts
JRW (7)  JRC 704 Note 5: Skew is defined as the absolute value of the difference between t
J-S (1)  The AT91X40 Series Microcontrollers feature an External Bus Interface (EB
JS- (13)  FUJITSU 02+
JS0 (3)  JSI 00+ GND (Pin 10): Signal Ground. The oscillator, slew control circuitry and t
JS1 (51)  VOLTRONICS 08+ Mode 0: Basic Input/OutputPort A, port B, and port C (upper and lower)
JS2 (87)  VOLTRONICS 05+ Reference clock. REFCLK is an external 125 MHz input clock that synchroni
JS3 (3)  N/A N/A N/A serializer to send special SYNC patterns. This allows the SN65LV1224A to
JS4 (7)  AMS SOP24 PROGRAM MEMORY Program Memory consists of a 2048-byte external memory (
JS5 (14)  173 01+ The basic unit of logic on the ispLSI 2096VL device is the Generic Logi
JS6 (6)  DIP   The SDRAM provides for programmable READ or WRITE burst lengths o
JS8 (10)  2008 Margin Dn*: When this open-collector (open-drain) input is asserted to GN
JS9 (4)  takamisawa takamisawa dc04 Clocks in the ispLSI 1048 device are selected using the Clock Distributi
JSA (1)  The A128 devices contain the following: • ARM7TDMI 16/32-Bit RISC
JSB (3)  Power Dissipation and Thermal Characteristics   Maximum Power Dissi
JSC (47)  JAPAN N/A ter File, which includes the control and status reg- isters of the on-c
JSE (1)  Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs
JSF (3)  This converter uses proven circuit techniques to pro- vide accurate and
JSH (5)  90 N/A 2. Handling In order to avoid damage to beam lead devices, particular ca
JSK (1) 
JSL (2)  MOTOROLA 07+ Absolute Maximum Ratings indicate sustained limits beyond which damage to
JSM (14)  TI PGA 0519+ DESCRIPTION The JSM1032 is an high speed CMOS OCTAL LATCH WITH 3-STATE
JSP (12)  MINI 08+ This power MOSFET is manufactured using an innovative process. This adv
JSR (5)  JADE-STAR DIP 92+ Once the deserializer has synchronized to the serializer, the LOCK pin tr
JSS (9)  SONY 03+ BGA Meets or Exceeds the Requirements of ANSI TIA/EIA-232-C Wide Range of Su
JST (6)  复旦微 dip/sop 07+ The TLV247x is a family of CMOS rail-to-rail input/output operational amp
JSX (3)  CAPCOM QFP 07+ Description: Mitsubishi IGBT Modules are de- signed for use in switchi
JT- (52)  PTC SOP/20 02+ • Viewing Angles Match   Traffic Management Sign   Requi
JT0 (21)  These pins along with the HKS form a 4´4 keyboard matrix which can p
JT1 (5)  NA 04+  The HY62LF16404D is a high speed, super low power and 4Mbit full C
JT2 (3)  02+ SOP gate, deactivating the gate drive circuits and shutting off the in- vert
JT3 (2)  X B 500 MHz, 500 mV −3 dB bandwidth, AV=2 400 MHz, 2VPP −3 dB b
JT5 (9)  TOS N/A 98+ Parameter VDD to GND2 RFVDD to GND Digital I/O Voltage to GND Operatin
JT6 (15)  TOS 1997 芯片 An external inhibit port is provided to control con- verter operation.
JT7 (5)  RATO 02+ SOP-16 The LM45 series are precision integrated-circuit tempera- ture sensors w
JT8 (1)  JT DIP 07+ If the duty cycle is to be varied over a small range about 50% only, the
JT9 (5)  TOSHIBA 2000 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge
JTB (2)  &KDUDFWHULVWLFV The listed characteristics are ensured over the oper
JTC (6)  SAMSUNG TSOP 00+ - Übertragungsrate: 10/100 MBit/s - Protokoll: Modbus/TCP - Integr
JTG (1)  •Specimen : Paraformaldehyde-fixed, paraffin-embedded 1.0mm diameter
JTI (2)  Revision History Features and General Description Pin Description Power
JTJ (1)  Output Bus Select. With this pin at a logic high, both the I and the Q
JTK (1)  Notes: 1. Test conditions assume signal transition times of 3 ns or less,
JTN (12)  Note 7: All limits guaranteed at room temperature (standard typeface) and
JTO (40)  MINI 08+ The Texas Instruments TFP401 and TFP401A are TI PanelBus flat pan
JTP (19)  N/A • Plastic package has Underwriters Laboratory   Flammability
JTS (4)  FIREGRON QFP CS falling edge to first DCLK rising edge DCLK high pulse width DCLK lo
JTT (1)  A common ground is required between the input and the output voltages.
JTV (2)  The HY62SF16403A is a high speed, super low power and 4Mbit full CMOS SRA
JTX (203)  MOTOROLA CAN3 The non-overlap time is the time between turning off the conducting pai
JU- (9)  CLARION MODULE 00 The charge pulse can be a minimum of 1µs and therefore the circuit
JU0 (11)  DIP 05+ mounting the module with side B as the mounting plane. When assembling
JU1 (1)  TEMIC SSOP 97+ The DEW-B device implements all necessary communication protocols for sup
JU2 (1)  The HY57V56420T is offering fully synchronous operation referenced to a po
JU3 (1)  The JU3832768HZSA/JU3832768HZSB/JU3832768HZSC are three terminal output
JU7 (1)  NEC SOT-89 Forward-Current Transfer Ratio  IC = 15 Adc, VCE = 4.0 Vdc  
JUK (1)   Guaranteed by design. Not production tested.  Sample tested du
JUL (9)  AMIS PLCC68 The FM1233B features a highly accurate voltage reference to which VCC is
JUM (4)  ZMD PLCC   Features 1) The built-in bias resistors consist of thin-film resis
JUN (9)    completion of update   Separate battery pin 2 4V operation
JUP (2)  SAMSUMG 06-07+ Note 2: Unless otherwise specified, these specifications apply for temper
JUS (1)  The second, transient power due to load capacitance, can be derived fro
JV- (5)    The sensor can operate in three interface modes: master, snapshot
JV0 (4)  Pulse A A   The M12S16161A is 16,777,216 bits synchronous high data rate Dyna
JV1 (17)  EVERTECH N/A CDIP28 Hynix HYMD264646(L)8-K/H/L series incorporates SPD(serial presence detect)
JV2 (684)  MOT 2008 1. Stresses greater than those listed under ABSOLUTE MAXIMUM   RATIN
JV4 (3)  CAN6 9546 The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the
JV5 (1)  *The minimum value of dc input voltage is 8 V when the output is less t
JV6 (1)  Note 1: TA=25C unless otherwise specified. Note 2: ESD applied to input
JVA (2)  00 Specifications Outline Dimensions Pin Connections and Short Description
JVC (1)  SANYO HYB 04+ Regulators (ISRs). These ISRs are de- signed with premium low threshold
JVG (1)    External gain-setting capability   Available in space-saving
JVN (4)  Panasonic 原装 08+ Support for simultaneous operation of all above devices. (only one at a t
JVP (1)  QFP0707-48 The purpose of this 54C/74C Family Characteristics applica- tion note i
JVR (14)  N/A If the TEST input is forced to its MID or HIGH state, the device will op
JW- (5)  UTC 1812-271 A 8051 standard pin is a pseudo open drain pin. It can sink at least 4mA
JW0 (89)  LUCENT MODULE N/A Six channels of EMI filtering for data ports Pi-style EMI filters in a
JW1 (72)  LUCENT 04+ The LT1013 devices can be operated from a single 5-V power supply; the
JW2 (21)  TYCO SOP   The quiescent current is the current which flows through the grou
JW3 (1)  JAT 3M-330 05+ Collision Output. Balanced differential line driver outputs from the coll
JWC (2)  JW 04+ • Bring Shut Down (SD)/Mode pin to a logic High status. • Br
JWD (24)  AMF 8550+ CONDITIONS IN1, IN2 and OUT BAT VBAT = 4.2V Suspend Mode Suspend Mode
JWF (3)  N/A 1206L High speed instrumentation Scope and logic analyzer front ends Window c
JWG (2)  JW 0603-3R3K WE is used for data write enable/disable control. WE high level enables th
JWI (7)  SNEC [CAUTION]   The specifications on this databook are only given for
JWS (60)  LAMBDA Module N/A An I2C Bus interface configured as a slave receiver is used for programmi
JWT (15)  JW TSSOP Features  NPT IGBT technology  low saturation voltage  l
JX- (6)  The designed amplifier has a measured -1dB input compression point of -24d
JX0 (2)  N/A DIP18 04+ ∗ This is a stress rating only and functional operation of the devi
JX1 (9)  MSC DIP The hybrid performs 2 wire to 4 wire conversion by taking the 4 wire signa
JX2 (262)  MOTOROLA CAN3 This addendum to the M68000UM/AD Users Manual, Revision 8, provides corre
JX3 (1)  MOC 06+ 500 The HYM72V32M656AT6 Series are gold plated socket type Dual In-line Memory
JX4 (11)  TI CAN6 Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Curr
JX5 (7)  N/A N/A N/A The device also features split output bank power supplies which enable th
JXA (1)  FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
JXC (1)  • FCRAM core with Single Data Rate SDRAM   interface •
JXD (1)  PHI SOP 92+ Users have access to all the relevant signal quality information, includin
JXE (2)  jauch jauch dc02 NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca
JXG (1)  10-Bit Resolution Non-Linearity: 1/2 LSB to 2 LSB Nonlinearity Tempco: 0
JXI (2)  N/A SOP-10 SWITCHING PERFORMANCE  Maximum Conversion Rate  Minimum Conver
JXM (3)  MSC 95+ The serial control bus supports the I2C protocol, while the serial-audio
JXO (2)    This is not an extensive capacitor list. Capacitors from other ve
JXP (2)  PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic 1
JXS (4)  N/A SMK 05+ 184-pin 1mm pin spacing Card Size: 133.35mm x 31.75mm x 1.27mm (5.25 x
JXT (4)  1-Wire® to USB port adapter for direct connection to notebook and
JXV (1)  3. Cleaning For organic contamination use a warm rinse of trichloroethan
JY- (4)  N/A QFP 07+ 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC . 3. These ar
JY0 (3)  JY 2007+ Note 1: The SOIC package used is thermally enhanced through the use of a
JY1 (7)  NAIS 04+ (1) This is the inverse of the junction-to-ambient thermal resistance whe
JY2 (5)  N/A 05+ Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the
JY3 (2)   UL Recognized File # E-96005  Glass passivated junction  
JY4 (1)  The ISD1740A/50A/60A devices also support an optional vAlert (voiceAlert)
JY5 (1)  Panasonic 原装 08+
JYD (2)  MINI 08+ Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Gene
JYE (4)  The VCA2619s VGA section consists of two parts: the Voltage Controlled
JYM (2)  MINI 08+ ISOUT (Current Sense Amplifier Output): This pin is the output of the cu
JYN (1)  When multiple inputs are programmed to be connected to the same output,
JYP (5)  MINI 08+ The bq2085 SBS-compliant gas gauge IC for battery pack or in-system ins
JYX (1)  JYX DIP-8 Signals an interrupt when overflowing Supports Timer Clear when a match
JZ- (9)  100 天龙伟业 靳先生 Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserv
JZ0 (3)  3X4 In most applications, the chip address inputs A0, A1, and A2 are hard-w
JZ1 (8)  2x2 A: The value of R JA is measured with the device mounted on 1in2 FR-4 boar
JZ2 (9)  Notes:  1. ZZZZ or ZZZ denotes the assigned product dash number. Th
JZ4 (1)  3-analog input terminals. Only the input from one of these is input to th
JZ7 (1)  Stability The IRU1075 requires the use of an output capacitor as part of
JZB (1)  SUN 99+   Designed for Class AB amplifier applications in 50 ohm systems ope
JZC (4)  hongfa hongfa dc05 Notes: 1. The thermal resistance is referenced from the junction-  
JZD (1)  For applications requiring guaranteed RF-tested perform- ance up to 26 G
JZH (1)  静震 贴片 C Auto-mute on static samples C 44.1 kHz 50/15 µs de-emphasis av
JZX (1)  relay 08+ JAPackage thermal impedance(6)165C/W TstgStorage temperature range−
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