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E.B (1)  79 99+ • E.B-VERS1.0-1/2/3 are also available in white package by specifyin
E.F (1)  N/A Single chip, 8-port Gigabit Layer 2/3/4 switch/router High level of in
E/1 (1) 
E/P (2) 
E-0 (1) 
E00 (26)  TOS SOP 08+ LCD Segment output terminal / LCD Common output terminal SEG40 in 1/3Duty
E01 (75)  FAIRCHILD QFN 05+ • Optimum instruction set for controller applications   •
E02 (38)  EPSON SQFP128 2007+ Both data and clock lines remain HIGH when the bus is not busy. A HIGH-t
E03 (14)  CRY SOP- 8 Perpendicular Recording Drive R W Head and Pre-Erase Head PC87334 Compos
E04 (11)  The LTC6900 operates with a single 2.7V to 5.5V power supply and provides
E05 (103)  EPSON SQFP208 07+ Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Ou
E06 (21)  NIASH QFP100L 0039+ Information furnished by Analog Devices is believed to be accurate and re
E07 (12)  For applications that require no external memory or temporarily no exte
E08 (3)  Power supply for the A/D converter. Connect this pin as close as possib
E09 (25)  FUJI TO3P The sequence of the burst counter is determined by the MODE input signal.
E0A (1)  06+ QFN-12 Near-Zero propagation delay RON is 5Ω typical at 3.3V Fast swit
E0C (8)  EPSON 01+  All outputs loaded; thresholds on input associated with output unde
E0D (2)  The Hyundai HYM71V65M801 X-Series are 8Mx64bits Synchronous DRAM Modules.
E0E (4)  Half of the macrocells on the CY7C372i have separate I/O pins associated
E0P (1)  The internal feedback voltage dividers central tap is connected to the no
E-1 (7)  SEMITEC 04 The device that acknowledges, has to pull down the SDA line during the
E1- (10)  The baseband filters are 5th order Chebychev and provide excellent matchin
E10 (154)  FAJRCHILD The coupler consists of a AlGaAs LED that is optically coupled to a diele
E11 (62)  ELMOS SOP-16 2006 2. JA is measured in free air with the component mounted on a high effect
E12 (50)  MORNSUN 08+ High performance:   Chained (back-to-back) packet handling  
E13 (60)  FSC TO-220 05+ When you select the mode, a broadcast packet is sent out on the wire by sy
E14 (46)  N/A 0112+ An additional improvement of the driving capability may be achieved by u
E15 (11)  15 0351+ INTERSIL NOTES:  1. Dimension are in inches.  2. Metric equivalents are
E16 (22)  Transmit data, K-generator channels A and B. In multiplexed channel mode,
E17 (12)  95/96 Carrier Detect (Active-LOW). These inputs are associated with individual
E18 (12)  2023 • Precision Reference for Long Term Stability and   Low Gain T
E19 (10)  • High-speed access time: 55, 70, 100 ns • CMOS low power op
E1A (2)  NFC Quiescent current consumption for the device under normal (non-dropout) c
E1C (4)  VEXTA A sub-repertoire of 10646 consists entirely of a set of coded characters
E1E (1)  N/A SMD N/A There are three fuses on the device that must be blown during the device
E1F (1)  ELPIDA TSOP 03+ E1F65805FTA6T9HJ easily expands data bus width to 32 bits or more using t
E1H (1)  AMI PLCC84 An excitation voltage is applied to the thermistor (RTHERM) and precisio
E1L (1)  The design of the DM562P is optimized for desktop personal computer appli
E1M (1)  DG SMD A high-performance 1/10/100 Mbps Ethernet Media Access Controller (MAC)
E1S (12)  Propagation delay time, high-to-low  level output from A, B, or C t
E1X (1)     SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia
E-2 (1)  ALPS N/A 07+ Afterwards, the two frequencies where the voltage of the rf signal at th
E2- (3)  01+ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
E20 (58)  PULSE SOP 0438+ Under-Voltage Lockout The under-voltage lockout circuit assures that the
E21 (18)  ittcannon ittcannon dc99 − Glueless Interface to Asynchronous   Memories: SRAM and EPRO
E22 (10)  TAITO SOP44W 2007+ The device has a high-performance image scaler that can do up-and-down sc
E23 (8)  00+ SSOP-3.9-16P The AD5241/AD5242 provide a single-/dual-channel, 256- position, digital
E24 (23)  MACOM SOP-8 Gain Error Gain Temperature Drift Power Supply Rejection Noise Outpu
E25 (35)  04+ As indicated in the diagram, capacitors C1 and C2 deter- mine the trebl
E26 (14)  EPSON Specifications Outline Dimensions Pin Connections and Short Description
E27 (10)  CAN The E271 and E271 are dual 4-channel analog multiplexers or demultiplex
E28 (480)  The inverting input is internally connected to the reference voltage of
E29 (5)  N/A SMD4 07+   The MT28F322D20 and MT28F322D18 are high- performance, high-densi
E2A (4)  TI DIP-28 This device is designed for Ethernet 100 Mbps and Intra-Office Te
E2C (1)  Notes: 7. All typical values are measured at VCC = 3.3V, TA = 25C. 8. C
E2E (86)  The HAL 805 features a temperature-compensated Hall plate with choppere
E2F (6)  PVIN (Pins 6, 7): Input supply pin. PVIN is connected to the input voltag
E2H (1)  TI 798 • Surface Mount SOT-23/   SOT-143 Package • High Detect
E2J (1)  VISHAY 05+ The LM87 is a highly integrated data acquisition system for hardware mo
E2K (19)    The values for the equation are found in the maximum ratings tabl
E2P (1)  SMD-8 05+ The digital output stage of the TLC372 can be damaged if it is held in th
E2R (1)  Reduced harmonic content of input currents corresponding to standards
E2S (2)  FARADAY QFP-100P 6+ The ML6428 can be optimized for PAL video by adding frequency peaking to
E2U (1)  • Speziell geeignet fr Anwendungen im Bereich   von 400 nm bi
E2Z (1)  (1) An export permit needs to be obtained from the competent authorities
E-3 (1)  During discharge and charge, the bq2050H monitors V SR for various thresh
E3. (1)  FEATURES  • Two 10-bit Nonvolatile DACs   − INL 1
E30 (18)  nsc n/a The 74AUP1G79 provides the single positive-edge triggered D-type fl
E31 (10)  MIT PLCC 04+ "Write Disturb" means a phenomenon that frequent write cycles ex
E32 (83)  eic eic dc90 Unlike the QT110 device, the internal threshold level is fixed at one of
E33 (11)  HARRIS 03+ The device is entirely command set compatible with the JEDEC single-powe
E34 (11)  EUROSIL DIP 07+ Minimum Dielectric Strength, Input-Output Minimum Insulation Resistance,
E35 (12)  tfk tfk dc97   NorthAmerica: http:semiconductor.hitachi.com/   Europe: htt
E36 (10)  ST 06+ Other operating features include an on/off inhibit, and the ability to st
E38 (24)  TAiTO 97 With a 144 pin package, low power consumption, various 32-bit timers, 8-c
E39 (18)  Responsible electronic component and equipment manufacturers are alread
E3C (5) 
E3D (1) 
E3F (16)  WEB2U The 6B Series digital subsystem communication is compatible with the ove
E3G (3)  CDIP CDIP Power mode: Normal, Slow, Idle, Stop mode and SL_IDLE mode. Normal mode:
E3H (2) 
E3I (1)  TAIWAN TO92 The E3ICT32L performs the data serialization and deserialization (SERDES)
E3J (18)  This terminal provides a high impedance output for the loop phase detect
E3M (3)  Description This HEXFET® Power MOSFET is specifically designed for
E3P (10)  MOT 06+ 500 (2) Operating method   The LD shall change its forward voltage requ
E3R (4) 
E3S (42)  OMRON Notes: (1) The VS1 and VS2 ports may remain open-circuited without damag
E3T (8) 
E3V (2) 
E3X (19)  OMRON PROGRAM/ERASE SUSPEND C Read other Blocks/Sectors during   Progra
E3Z (21)  OMRON 05+ The SN74LVC2G241 is organized as two 1-bit line drivers with separate out
E4- (1)  FEATURES • The NL series are available in five form factors
E40 (17)  The ENDEC (Encoder Decoder) unit is the interface be- tween the Ethernet
E41 (8)  06+ PLCC-28 For surface mounted applications Metal-Semiconductor junction with guardr
E42 (7)  The SN65LV1023A and SN65LV1224A are a 10-bit serializer/deserializer chip
E43 (8)  six n/a Note 5: The maximum allowable power dissipation is a function of the maxi
E44 (6)  SMD-8 over the full operating temperature range. Unless otherwise specified: VI
E47 (8)  AMI SOP IF-Compensation Demodulator Chrominance Filter Frequency Demodulator
E48 (2)  RF bandwidth 500 MHz to 4 GHz 2.7 V to 3.3 V power supply Separate VP al
E49 (2)  SSOP28 † Stresses beyond those listed under "Absolute Maximum Ratings
E4D (1)  02+ HF420: Unsealed,2C, Soldering, Plug-in HF428: Unsealed,2C, PCB HF421: Un
E4N (2)  ONSEMI 00+ SOP-8   These smart power drivers have been designed with BiMOS II logic f
E4P (1)  NEC DIP-40 Testing of the switching parameters is modeled after testing methods spec
E4S (1)  • Space Saving SIP Package • +5V input • 5-bit Program
E4T (1)  MARCONI 00+ QFP144   During normal operation, a synchronization pulse acts as the cloc
E4X (1)  ML 798 Note 4: The maximum power dissipation must be derated at elevated tempera
E-5 (1)  ST 07+ Use a high quality ceramic capacitor with low ESL and ESR for best resu
E50 (20)  six n/a Thermal impedance (ZTJX ) for measurements initial qualific
E51 (9)  LMI SOP-16 6+ Stresses above those listed under Absolute Maximum Ratings may cause perm
E52 (32)  SMD-8 03+ Bus Command/Byte Enable: During the address phase these signals define th
E53 (9)  ST 04+ Active low input to stop diff outputs. 3.3V input for selecting PLL Ban
E54 (12)  SMD-36 05+ The basic unit of logic on these devices is the Generic Logic Block (GL
E55 (22)  TEMIC O7+ Chopper Stabilization is a unique approach used to minimize Hall offset on
E56 (12)  N/A Note 1: TA=25C unless otherwise specified. Note 2: ESD applied to input
E57 (3)  The AD5382 is a complete, single-supply, 32-channel, 14-bit DAC availabl
E58 (7)  99+ DIP The TL1466I is a six channel pulse-width-modulation (PWM) control circuit
E59 (8)  The Power Control section provides for two basic power configurations, ba
E5A (3)    The E5AZ-C3 is a high voltage monolithic MOSFET operational ampli
E5C (8)  ISB = 10 mA Fully asynchronous and simultaneous Read and Write operation
E5E (3)  The TMS320C80 is a single chip, MIMD parallel processor capable of perfor
E5F (1)  After a successful ATR, the Protocol and Parameter Selection (PPS) protoc
E5J (3)  Full Rise Electronics Co. 03+ Under many operating conditions, both the high-side (GH) and low-side (
E5L (1)  The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous
E5N (1)  Maximum voltage device can withstand without damage at rated voltage. &nb
E5P (2)  MOT SO8 03+ Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte
E5R (1)  TV SVHS OUTPUT MODE The device supports SVHS video format. The SVHS mode
E-6 (1)  ST SOP16 This device is fully specified for partial-power-down applications using
E60 (12)  *The minimum value of dc input voltage is 8 V when the output is less t
E61 (8)  HARRIS SOP-8 Using a CT by itself normally introduces a current lag, typically obser
E62 (31)  EUROSIL DIP 90 Note: There is no external connection for voltage feedback. Voltage sens
E63 (1)  Four 8-Bit Voltage Output DACs 5-V Single-Supply Operation Serial Interf
E64 (18)  HARRIS SOP-8 * All specs and applications shown above subject to change without prior
E65 (13)  FLW SOP 06+ This series of 500 W Transient Voltage Suppressors (TVSs) provides the hi
E66 (3)  The AUTO ON-LINE® feature allows the device to automatically "wak
E67 (7)  HARRIS 04+ The information provided herein is believed to be reliable; however, C&am
E68 (14)  ON 03+ SOP24 Fifth Generation HEXFETs from International Rectifier utilize advanced p
E69 (9)  N/A N/A N/A The Hyundai HYM71V32S755AT4 Series are 32Mx72bits ECC Synchronous DRAM Mod
E6A (4) 
E6B (9)  FSC 06+ 500 A basic familiarity with the information in Part I will help you to unders
E6C (8) 
E6E (1)  The M41T81S Serial Access TIMEKEEPER ® SRAM is a low power Serial R
E6F (1)  N/A Drain-Source Voltage  Gate-to-Source Voltage Continuous Drain Cur
E6N (7)  SMD-8 05+ coupling from the supply. Also, place the VCO as far away as possible fro
E6P (3)  SMD-8 05+ The HSDL-3600 is a low-profile infrared transceiver module that provid
E6S (1)  98 The HYM72V16M636TU6 Series are Dual In-line Memory Modules suitable for ea
E6U (1)  The DS8830, SN55183, and SN75183 dual differential line drivers are des
E6V (11)  ST SOP-8 The Texas Instruments MSP430 family of ultralow-power microcontrollers co
E-7 (1)  ALPS module 02+ Thermal Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x
E70 (8)  E QFP 07+ Crystal oscillator input Power supply (+3-5V DC) Ground (0V) Loop fil
E71 (6)  N/A N/A N/A Modulus control output for controlling an external dual-modulus prescaler
E72 (7)  INTEL BGA 02+ The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger
E73 (11)  ATG PLCC684 The numerical value of the current is positive if the charge of the car
E74 (4)  SIEMENS 07+ This 7 channel 1-bit to 4-bit address register/driver is designed for 2.
E75 (9)  INTEL 02+ Answer If the case temperature could be held to 25C, the current limit
E76 (4)  JRC 04+ SOP/8 (Load as specified in Figure 1; VCC = +2.97V to +5.5V (at the VCC pins); V
E78 (8)  2 AMIS Chip Enable (CEN) input pin, when low, disables both outputs (OUT1 and OU
E79 (1)  The AT84CS001 DMUX is started by the ASYNCRST control input that acts as
E7C (1)  STM SOP-20 04+ • 1.5 Mbps data rate • On-chip 3.3V regulator • Endpoi
E7N (3)  SMD-8 05+   The QS3VH861 HotSwitch with 10-bit flow-through pin out is a high
E7S (1)  Figure 1 shows a typical battery pack application of the bq2050 using the
E8. (2)  SOT23/4 The ispLSI 2032 and 2032A are High Density Program- mable Logic Devices
E80 (2)  Synchronous Address Inputs. These pins must tied to the two LSBs of the
E81 (4)  ON SOP-8 03 Allows Safe Board Insertion and Removal from a Live Backplane Controls S
E82 (10)  INSTEL 96   For more information on the PWP package, refer to TI technical bri
E83 (6)  Before data transmission the IC stays in standby listen mode. To prevent
E84 (1)  Connecting the inhibit input (Pin 2) to input common (Pin 10) will cause
E85 (3)  AXIS 16P N/A Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS
E86 (4)  ZILOG DIP 99+ The S1T8825B is a high performance dual frequency synthesizer with two in
E87 (1) 
E88 (35)  N/A SSOP8 07+ NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp
E8C (1) 
E8F (1)  In a novel approach to this problem, DASA IMT and Seyonic SA (both of Neuc
E-9 (3)  06+ QFP-44 Pericom Semiconductors PI74AVC+16820, a 10-bit flip-flop designed for 1
E9- (1)  EDGE 01+ NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp
E90 (13)  98
E91 (2)  06+ QFP   The PTH03060W non-isolated power module is small in size but big
E92 (7)  high-frequency tube ERICSSON 04+ PRODUCTION DATA information is current as of publication date. Products c
E93 (2)  These regulators feature a dedicated control input (EN, Active High) fo
E94 (5)  Extended data out does not place the data in / data out pins (DQs) into t
E95 (3)  Data is shifted into an eight bit shift register The first bit of the da
E96 (6)  95 NOTES: 1. Minimums are guaranteed but not production tested. 2. This par
E97 (2)  NS SOP-28 95+/SX Note: Definition of I/O column pneumonic on pin description table above:
E98 (3)  NS SOP-28 95+/SX B2: Writing this bit to a 1 protects the upper page of memory. If this b
E99 (3)  2007 The device is compatible with the JEDEC single power-supply Flash comma
E9B (1)  DIP-28 07+/08+ The C30737 type avalanche photodiode provides high responsivity between 5
E9C (1)  The ATE9C49 is a five-volt-only in-system Flash programmable and erasable
E9D (1)  TRIQUINT 镜面 03+ • HiPerFET TM technology   C low RDSon   C unclamped in
E-A (4)  ALPS 99+;07+ For the most current package and ordering information, see the Package Op
EA- (2)  显版 94+ The USB descriptors and keyboard matrix can be customized via an optional
EA0 (5)  N/A module 2005+ A common ground is required between the input and the output voltages. Th
EA1 (18)  PHILIPS SOP8 The DS1254 is a fully nonvolatile static RAM (NV SRAM) (organized as 2M wo
EA2 (63)  PANASONIC RELAY 06+ The TMS29F400T/B is a 524 288 by 8-bit / 262 144 by 16-bit (4 194 304-bit
EA3 (30)  MIC SWITCHING PARAMETERS QgTotal Gate Charge QgsGate Source Charge QgdGate
EA4 (13)  NIHON 00+ The EA40QC03-FM integrates 64K words of on-chip memory configured as 32K
EA5 (1)  Industrial Standard SPI Pin-out 8 Mbits of Page-Erasable Flash Memory
EA6 (28)  N TO252
EA7 (2)  To program the offset values, PEN can be brought low after reset. On the
EA8 (10)  MALAI 00+ Junction CapacitancepF Test Conditions: f = 1 GHz Video Resistancek͐
EAA (2)  ST 07+   VOUT Output Voltage The MAX5069A EV kits output (VOUT) is set to
EAB (2)  Pin 1 VCC1 ( a 5V) The logic and clock power supply pin Pin 2 DIRECTION
EAC (5)  VIN Range: 2.7-5.5Volts Fixed or adjustable VOUT: 1.0V - 4.2V 3A output
EAD (2)  epson epson dc95 UART channel B Receive Data or infrared receive data. Normal receive data
EAE (2)  DIP 00+ PhaseLink Corporation, reserves the right to make changes in its products
EAF (9)  99 NOTE: 10EP circuits are designed to meet the DC specifications shown in t
EAG (1)  SAMSUNG PQFP 00+ State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design
EAI (1)  PMI CDIP Note 3: The shortest allowable SK clock period = 1/fSK (as shown under th
EAK (1)  The Hynix EAK301 Series are 16Mx72bits ECC Synchronous DRAM Modules. The
EAM (6)  ECE N/A • Quad channel transceiver for 195 to 1500 MBaud serial   sig
EAP (1)    A fully released data sheet contains neither a classification head
EAR (3)  FUJI 828 It is an open drain output and may be wire-ORed with any number of open
EAS (7)  Control data comes from the data receiver is used to generate the control
EAT (5)  N/A DIP 07+ If CS2 exceeds 0.5V the outputs will be disabled and a softstart commen
EAV (1)  EPSONS 99 The PWM pin is designed to drive a low cost transistor or MOSFET as the
EAW (2)  N/A The time-domain maximum slope argument can be appropriate for non-sinusoi
EAY (2)  ST 07+ SSCG uses a patented technology of modulating the clock over a very nar
EAZ (2)  Assembler. The macro assembler allows the assembly code to be merged sea
EB- (4)  SOP24W 2007+ (25-MHzC165-MHz Pixel Rates) Universal Graphics Controller Interface C 1
EB0 (4)  The CS4344 family contains on-chip digital de-empha- sis, operates from a
EB1 (3)  N/A 0805LED
EB2 (57)  NEC Relay(DZ) 99+ Two freely connectable operational amplifiers, OP1 and OP2, are used to
EB3 (3)  2. MATERIAL: Units are encapsulated in a low thermal resistance molding
EB4 (7)  N/A SMD 5 • HF signals that are input are sliced at an accurate level,  
EB6 (3)  Ripple current, less than 300 mΩ equivalent series resis- tance (E
EB7 (7)  06+ SOP-5 The Fairchild Switch FST3126 provides four high-speed CMOS TTL-compatibl
EB8 (17)  2008 • 1 kV/µs Minimum Common Mode   Rejection • Comp
EB9 (4)  1LC3 Active Mixer with Conversion Gain No External LO Driver Necessary Low LO
EBA (8)  The EBA2 can be programmed to output progressive scan images up to 30 fps
EBB (1)  ENCV Variable clock enable (TTL compatible input) - This input directly c
EBC (41)  Notes:  1. Test conditions assume signal transition times of 5 ns o
EBD (2)   High-speed access time: 8, 10, 12, and 15 ns  CMOS low power
EBE (7)  95 The device is organized as a 10-bit or 20-Bit bus switch. When OE1 is LO
EBF (1)  TOTO QFP 07+ Note 1: RL is connected to VEE for AVOL sourcing and VOH tests. RL is conn
EBG (5)  EBG 2007 Disconnect the EBG33RJ from power and PC. Remove the PIC microcontroller
EBL (20)  DIP 1996 To enhance the flexibility and function of the clock synthesizer, a two-s
EBM (77)  0805BEAD Three operating modes can be programmed using the SNOOZE pin. When SNOOZE
EBN (1)  If the voltage on the output pin rises above the input voltage, as might
EBO (2)  N/A N/A N/A To reset the new VTRIP voltage start by setting the WEL bit in the cont
EBP (2)  MOT TO-220 99 The M36L0R7050T0 and M36L0R7050B0 com- bine two memory devices in a Mul
EBR (6)  ST 07+  TAOperating free-air temperature−4085C ‡ Defined by th
EBS (7)  N/A 06+ 500   Please be aware that an important notice concerning availability,
EBX (1)  ADV/LD is a synchronous input that is used to load the internal registers
EBZ (1)  Designing with Intels FlashFile Architecture enables OEM system manufactu
E-C (1) 
EC- (90)  SEIKO EPSON The AHC574 devices are octal edge-triggered D-type flip-flops that featur
EC0 (59)  ALPS SALE--STOCK!! 08/09+ AMDs Flash technology combines years of Flash memory manufacturing experi
EC1 (322)  QFP48 The ground return for the digital supply for the ADCs output drivers. T
EC2 (168)  DIP The output pull-up structure can be globally configured to be either a
EC3 (109)  CYPR QFP 03+ The U4256BM is especially designed for AM up/down converter systems, tog
EC4 (34)  Note: 6. Distribution data sample size is 398 samples taken from 4 differ
EC5 (44)  ACE SMD 03+ The ISP1563 is a Peripheral Component Interconnect (PCI)-based, single-ch
EC6 (18)  SOT-252 OPA688UThis VLA™ (Voltage Limiting Amplifier) has two inputs (VH a
EC7 (4)  N/A 04+ SW (Pin 4): Boost Regulator Switch Pin. This pin is the boost regulator s
EC8 (15)  NIHON SOD-6 05+ The recommended input capacitance is determined by 350 milli-amperes (rm
EC9 (9)  ATMEL PLCC68 4 3 1 Command Register 4 3 2 Data Configuration Register 4 3 3 Receive C
ECA (315)  Panasonic 2008+ On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external so
ECB (13)  SAM BGA 01+ The 82C37A allows an external signal to terminate an active DMA service b
ECC (127)  PANASONIC 2007+PB High temperature metallurgically bonded construction Cavity-free glass
ECD (7)  NIHON SOD-6 05+ These N-Channel enhancement mode power field effect transistors are produ
ECF (13)  N/A N/A The ECFB100505GB601T is a monolithic CMOS analog-to-digital con- verter
ECG (229)  HAR TO-99 The 60320 uses burst-mode charge transfer methods pioneered and patented
ECH (448)  PANASONIC n/a Signal Processor (DSP): - SM/SMJ320VC33-150   - 13-ns Instruction C
ECI (5)  N/A QFP 07+ Operates from a single +5V supply Maintains near rail-to-rail performan
ECJ (397)  PANASONIC 2007+PB Collector-emitter voltage peak value Collector-Base voltage (open emitt
ECK (95)  PANASONIC 2007+PB !Features 1) Built-in overvoltage protection circuit, overcurrent protect
ECL (48)  NIHON 00+ This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed
ECM (39)  CORP CLCC 2001 (prescaler OFF) Input sensitivity fi = 80 - 1000 MHzPSC = 1Pin 13 fi =
ECN (70)  HIT DIP 07+ There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877)
ECO (66)  CYANLECHNO TQFP/100 07+ When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE
ECP (33)  WJ 2005   The Rambus ® RIMMTM module is a general purpose high-performa
ECQ (414)  PANASONIC 2007+ FLEX 8000 devices contain an optimized microprocessor interface that per
ECR (91)  PANASONIC 3X4-3P 04+ HY57V56820A is offering fully synchronous operation referenced to a positi
ECS (411)  ECS 2007+PB Intel and Pentium are registered trademarks of Intel Corporation. Lexmark
ECU (298)  PANASONIC 0603-332K • Horizontal SYNC input up to 150 KHz. • On-chip PLL circuitr
ECV (15)    The current source provides a closely regulated zener current, wh
ECW (310)  N/A   A code bit is the basic component of the encoded waveform, and can
ECX (46)  All typical values are at 25C and with a 3.3 V supply. tsk(p) is the mag
ECY (1)  (All voltages referenced to GND unless otherwise noted.) VIN to GND VCC
ECZ (3)  DARFON 03+ HY57V56820A is offering fully synchronous operation referenced to a positi
E-D (2)  APOGEE 08+ The Design Browser allows users to select and import precon- figured des
ED- (13)  SUPERTEX I 2008 The product identification mode identifies the device and manufacturer as
ED0 (22)  ST SOP-20 06+ The F1, F2 and F3 Series were developed as timing extraction filters for
ED1 (63)  N/A TO-92 N/A Stresses beyond those listed under absolute maximum ratings may cause per
ED2 (15)  3. Preventive measure against oscillation   For preventing the oscil
ED3 (10)  PANJIT TO-252 04+   To maximize I/O throughput and improve host and SCSI bus utilizat
ED4 (21)  PRX SOP Watchdog Timer The Watchdog Timer circuit monitors the microproces- sor
ED5 (14)  WTF 00+ Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers ar
ED6 (6)  96   For each bridge the PHASE input controls load current polarity by
ED7 (7)  Xilinx thoroughly benchmarked the Virtex family. While per- formance is
ED8 (9)  Maximum ratings are those values beyond which device damage can occur. Ma
ED9 (4)  This data sheet identifies products, their specifications, and their char
EDA (5)  AMIS 06+ The MAX3873A is implemented in Maxim's second-generation SiGe process and
EDB (9)  WFP4M 2007+ Now microcomputers are widely used for microwave ovens, air conditioner
EDC (7)  SANYO SSOP 1998   Please be aware that an important notice concerning availability,
EDE (27)  Elpida 06+ Command Buffer - The command buffer stores up to 40 characters, includin
EDF (13)  Vishay DFS 08+ The OXCF950 also incorporates a bridge to an 8 bit Local Bus in Local Bu
EDG (8)  N/A ECE 05+ • Input Voltage Range:   36V to 75V • 35W Output Power
EDH (12)  N/A N/A N/A The GS9068 inputs are self-biased, allowing for simple AC coupling to the
EDI (69)  edi edi dc90 To integrate so many transistors on a piece of silicon, their physical g
EDJ (1)  Fifth Generation HEXFETs from International Rectifier utilize advanced p
EDK (15)  st 07+ 5890   Designed with Motorolas advanced SMARTMOS, the 34923 is designed f
EDL (13)  TDK DIP 2006 Output driver for the synchronous power MOSFET. Analog ground for interna
EDM (11)  GOULD EDME 钢面 08+ The EDME0141A0864/EDME0141A0864 are high speed comparators fabricated on
EDN (2)  VIA BGA 0320+
EDO (5)  N/A 25201008 In most applications the input coupling capacitors are 0.1µF. The
EDP (2)  Maximum ratings are those values beyond which device damage can occur. Ma
EDR (21)  MOTOROLA 06+ QFP *Stresses above those listed under Absolute Maximum Ratings may cause per
EDS (56)  TI 07+ The Laser Diode and the ZL40518 are connected together by interconnect tra
EDT (32)  N/A QFP 07+ • Low power consumption: STANDBY   - 72 µW max at 3.6V
EDW (1) 
EDX (2)  ELPIDA BGA 05+ Note 6: Load regulation is measured on a pulse basis from no load to the
EDY (2)  Motorola reserves the right to make changes without further notice to any
EDZ (30)  N/A N/A 2006+ Xilinx in-system programmable products provide a mini- mum endurance le
E-E (2)  Most Significant Data Bit (MSB) Data Bits 10C1 Least Significant Data Bi
EE- (214)  OMRON Parameter Blocks : The boot block architecture includes parameter blocks
EE0 (12)  Adjustable regulator output (Regulator #1) C It is recommended to bypass
EE1 (9)  SMD ROHM 05+ The Enhanced PCI-IDE Interface is a single-chip controller packaged in a
EE2 (52)  NEC 0046+ NOTE: EP circuits are designed to meet the DC specifications shown in the
EE3 (2)  N/A N/A 07+ Absolute linearity is utilized to determine actual wiper voltage versus e
EE4 (1)  During a Bank Activate command cycle, A0-A11 defines the row address (RA0
EE6 (1)  25MHz clock can be connected to the CKIN pin. The chip senses activity on
EE7 (1)  Power Up and Down Requirements. There are no restrictions on the power-u
EE8 (56)  INT 05+ The FMS6346 Low Cost Video Filter (LCVF) is intended to replace passive
EE9 (5)  ATMEL 01+ The bq2060 supports the smart bat- tery data (SBData) commands and charg
EEA (10)  Panasonic 2008+ DESCRIPTION Intended for analog and digital satellite STB receivers/Sat
EEC (53)  PANASONIC 2007+PB Reference level for the relative attenuation arel of the TFS 1220B is the
EEE (118)  PANASONIC SMD 07+ Rating to 200V VBR For surface mounted applications Reliable low cost co
EEF (108)  PANASONIC 2V220UF PB-FREE 06+ The C6203 device has a powerful and diverse set of peripherals. The perip
EEG (2)  All typical values are at 25C and with 3.3 V supply unless otherwise note
EEI (2)  DIP-14 5161 The new package that consists of OSAs and ESA with the combination of
EEJ (17)  N/A 0805TAN Transmitter Output Control. TTL/CMOS control input. /TXEN is an active LO
EEL (20)  ST SSOP-16P 07+ An additional toggle bit is available on I/O2 which can be used in conju
EEM (2)  NEC 00+ One of its notable features is MaverickKey unique IDs. These are factory
EEP (1)  The Master begins a transmission by sending a START condition. The Mast
EER (1)  Note 1: Absolute maximum ratings indicate limits beyond which damage to t
EES (13)  omron omron dc01 VOUT as Low as 0.6V High Power Switching Regulator Controller for 3.3V-5
EET (9)  PANASONIC 2007+PB The GS1545 is a high performance integrated Equalizing Receiver designed
EEU (260)  Panasonic 2008+ (1) Junction temperature = ambient for +25C specifications. (2) Junction
EEV (218)  Panasonic 2008+ Two-Wire I²C Serial Interface Supports 400kHz Protocol Single Sup
EF- (3)  CERATECH The ADSP-21991 provides 40K words of on-chip SRAM memory. This memory is
EF0 (23)  PANASONIC 2004 Low level at pin NW:Mode without standard conversion High level at pin
EF2 (9)  RFMD 02+ The EF2189TR13E is a special-purpose karaoke DSP that implements the sig
EF3 (6)  99 Data enable. As defined in the DVI 1.0 specification, the DE signal allow
EF4 (1)  90% Efficiency High Supply Capability to Deliver 3.3V 100mA  with
EF5 (2)  N/A DIP8 03+   The ELM312 is an interface circuit for use between high speed lo
EF6 (127)  ST DIP N/A   Symbols This specification uses various picture symbols to prevent
EF7 (18)  N/A N/A N/A The LTC1998 is a low battery warning indicator and is especially designed
EF8 (3)  ST DIP-16 08+ Description The ACPM-7833 is a fully matched CDMA Power amplifier modul
EF9 (10)  ST DIP40 04+/05+/06+/07+ ‡ See The Texas Instruments document, PowerPAD Thermally Enhanced P
EFA (12)  EAGLEWARE 00+ Compliant with IrDA Specification Data Rates 9.6 Kb/s to 4.0 Mb/s
EFB (11)  ST DIP-16P 9914+ The asynchronous data transfer (pins TDI, TDO) is accomplished by gener
EFC (102)  N/A These devices are fully specified for hot-insertion applications using Io
EFD (4)  220 9801 The LM78LXX is available in the plastic TO-92 (Z) package, the plastic
EFF (3)  THOMSON DIP-40 08+ +15V - is the low voltage supply for all the internal logic and isolated
EFG (11)  ST 06+ PLCC-28 outputs will follow the data input precisely. When the LE is taken low,
EFH (2)  GLAN DIP18 06+ By substituting the attenuated values of Vd and Id for the Vi and Ii in
EFI (3)  ST TQFP 07+ The MC68HC000 is an implementation of the M68000 16/-32 bit microprocesso
EFJ (8)  N/A State of the art Hyperfast recovery rectifiers designed with optimized per
EFM (39)  RECTRON 07+
EFN (3)  WRITE CLOCK (WCLK)   A write cycle is initiated on the LOW-to-HIGH t
EFO (28)  PAN 1808 05+ For a general estimate of ICC, the following equation may be used:  
EFP (11)  TrenchMOS output stage Current limiting Overload protection Overtemper
EFR (1)  The integrated combination of photodiode and transimpedance amplifier on
EFS (37)  99+ Vcc = 1.7V~2.3V, TA = 0C to 70C/ -40C to 85C(I), unless otherwise specifie
EFT (2)  ALCATEL   handles imagers up to 1000 pixels wide l Integrated Correlated Do
EFV (2)  PAN 4X5.8 05+ The Simultaneous Read/Write architecture provides simultaneous operation
EFX (3)  haltec haltec dc90 New B6HF bipolar technology, 25GHz fT Small outline P-TSSOP 16 package
EFY (1)    The amplifiers have been provided with two ground leads to avoid
EG- (30)  EPSON The load counter pulse must be at VSS 2 µs prior to the positive t
EG0 (14)  SANKEN DO-41 07+ Notes:  1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Dont
EG1 (16)  Eglos N/A 4. Designed to meet these characteristics over the stated voltage and tem
EG2 (17)  When the GPIO[1] pin is configured as an input, this pin can be used to
EG4 (2)  When the deserializer detects edge transitions at the LVDS input, it atte
EG5 (7)  AD8152 is a member of the Xstream line of products and is a breakthrough
EG6 (2) 
EG7 (4)  Each logic block features a 72 x 87 programmable product term array. Th
EG8 (28)  INTEL QFP100 06+ The SMA ZenBlock™ is designed to protect the MOSFET in flyback co
EG9 (4)  1812-750MA Note 13: Comparator thresholds are expressed in terms of a voltage differ
EGA (6)  INPAQ Output used in conjunction with DETECT1. When a Call Progress High Band
EGC (3)  AIM O7+ Array Description The X9269 is comprised of a resistor array (see Figure
EGD (2)  FUS . N/A Information at input D is transferred to the Q output on the positive go
EGE (2)  FUS . N/A Notes: 1. IDD depends on output load condition when the device is selected
EGF (10)  ZOWIE 07+ Extended Data Out Mode capability Read-modify-write capability Multi-bit
EGG (5)  egg egg dc95 The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal mi
EGH (1)  samxon samxon dc00 Electrically isolated: DBC base plate 3500 VRMS isolating voltage Stan
EGI (2) 
EGL (50)  GS 5000 07+ ! Available in a single mode (160-bits shift register) or in a   dua
EGM (1)  Stresses beyond those listed under Absolute Maximum Ratings may cause per
EGN (1)  LT 05+
EGO (7)  NSC 2008 The Intersil ISL84715 and ISL84716 devices are low ON-resistance, low vol
EGP (75)  EGP全系列专卖 07/08+ The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intels lat
EGR (2)  To provide the high input sensitivity necessary to receive optical signals
EGS (4)  PANASONIC Hynix HYMD232M646(L)8-K/H/L series incorporates SPD(serial presence detect
EGT (6)  Notes: 1. See test circuit and wave forms. 2. This parameter is guarante
EGV (3)  99 SOP-8 Digital data is placed on the SDATA pin and clocked into the FS6011 int
EGX (1) 
EGY (1)  Notes: 1. In accordance with the given electro-optical characteristics,
EH- (1)  q NEW DMOS TOPOLOGY:   Ultra Low Dropout Voltage:   115mV Typ
EH0 (22)  Halfbridge-Output 3; Internally contected to Highside-Switch 3 and Lowsid
EH1 (9)  SZNKAN V+ (Pin 8): Positive Power Supply. This supply must be kept free from noi
EH2 (21)  N/A DIP 07+ For increased noise immunity, hysteresis may be added to the power-fail
EH3 (4)  ECLIPTEK 730 CDS is a CMOS Schmitt Trigger input structure. It is used to distinguish
EH5 (14)  2007 The DAC8580 is a 16-bit, high-speed, low-noise, voltage-output DAC desi
EH7 (8)  FEATURES AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP   A Version
EH8 (1)  • 1.25 (31.75mm) PCB Height • 168-Pin Unbuffered DIMM with Do
EH9 (2)  * Absolute maximum continuous ratings are those values beyond which damag
EHA (19)  02+ The PI90LV02 and PI90LVT02 are single differential line receivers that u
EHB (8)  Panasonic SIP-5 08+ A sub-repertoire of 10646 consists entirely of a set of coded characters
EHC (2)  4. Design your application so that the product is used within the ranges
EHD (26)  N/A
EHF (46)  N/A Stability The output capacitor is part of the regulators frequency comp
EHM (5)  mot mot dc72+ It is a single-pin crystal oscillator, operating at the series resonant
EHN (1)  Isolation Barrier The isolation barrier consists of two transformers and
EHO (2)  AD 2008
EHP (2)  stocko stocko dc97 The SSM2165 is a complete and flexible solution for condition- ing micro
EHR (24)  div div dc72+ NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from fl
EHS (3)  SOP   The CSPU877A is a PLL based clock driver that acts as a zero delay
EHT (24)  A variety of packaging options are available. Dependingonapplicationandp
EHV (3)  div div dc80+ 2.8Msps Conversion Rate Low Power Dissipation: 14mW 3V Single Supply Ope
EHX (1)  N/A 1206X5 As long as the LOCK register is not set, the output characteristic can
EI- (9)  The external magnetic field component perpendicular to the branded side
EI0 (2)  八脚铁帽 08+ FS8S0965RCB is a Fairchild Power Switch (FPS) that is specially designe
EI1 (23)  02+ SOP-8 Output Voltage Temperature Coefficient   • 150 ppm/C, typical
EI2 (4)  07+/08+ PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port ar
EI3 (5)  era era dc02 The WRITE instruction includes 16 bits of data to be written into the s
EI4 (4) 
EI7 (3)  The AGC dynamically adjusts the gain of the preamplifier to compensate fo
EI8 (2)  EPIC PLCC68 Transmit Clock. These ECL 100K outputs (+5V referenced) provide the bit r
EIA (5)  AMD The UPC8187TB is a silicon monolithic integrated circuit designed as a
EIC (89)  EIC 00+ Acknowledge Polling Since the device will not acknowledge during a write
EID (3)  97+ 341 The FMS6346 provides an internal diode clamp to support AC- coupled inpu
EIE (1)  AM 04+ • Message and streaming status modes • Variable-length trans
EIK (2)  100 天龙伟业 靳先生 Supply Voltage Supply Current Output Voltage Load Regulation Line Regu
EIL (1)  EPIC 99+ PLCC-68 There is one variable gain amplifier in each channel of the receiver. Th
EIM (2)  DYNEX SOP The HT74XX series is a set of three-terminal high current high voltage
EIN (10)  NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
EIP (1)   Stresses beyond those listed under Absolute Maxi- mum Ratings may
EIR (2)  Open-Drain Output to Power Transistor Driving Fan. Connect to the gate of
EIS (5)  92 This is a product in the pre-production phase of development. Device cha
EIT (1)  The HYM7V73AC1601B N-Series are Dual In-line Memory Modules suitable for
EIU (1)  2 QFP The internal bootstrap diode and an external bootstrap capacitor supply
EIZ (1)  iskpa iskpa dc95 Data inputs for a 18-bit bus. MRS initializes the read and write pointers
EJ1 (3)  PLCC Fluid analysis is essential in a wide range of current applications. Biol
EJ2 (2)  Sumida For example, if a block of data is to be transferred from RAM to an I/O
EJ3 (2)  FEATURES lOutput high under incident light lBuilt in Schmitt trigger cir
EJ4 (3)  SGS 87+ QFP multivibrator can be calculated by : T = 1/2 RX CX for CX > 0.01&micr
EJ5 (1)  Chip-Select-Not input; CSN is an active low input; serial communication i
EJ6 (1)  infineon QFP 05+ NOTE: EP circuits are designed to meet the DC specifications shown in the
EJA (1)  05+ 3/SOT-23 When the CH7009 is operating as a VGA to TV encoder in master clock mod
EJB (1)    The melting temperature of solder is higher than the rated temper
EJE (2)  Parameter VDD to GND VOUTA, VOUTB, VBZ to GND Digital Input Voltages to
EJH (3)  The Constant, B, related to the failure mechanism is derived from either
EJR (1)  0603L (1) This data was taken using the JEDEC standard High-K test PCB. (2) Po
EJY (1)  TDK SOP 00+ Functional Description The HSDL-3310 is a small form factor infrared (
EK- (7)  2008 A programmable digital audio effects processor enables bass, treble, mi
EK0 (6)  SANKEN LMD is the last measured discharge capacity of the battery. On initializa
EK1 (8)  JRC DIP-8 0001+ The W29EE512 includes a data polling feature to indicate the end of a prog
EK2 (2)  Ruotare il selettore su SF . Quando lalimentazione a ON e si applica i
EK3 (8)  ST 07+ FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connect
EK4 (1)  The ID sent by the chip can be between 32 and 152 bits in length (in mu
EK5 (4)  ELNA 06+ These parameters, although guaranteed over the recommended operating cond
EK6 (12)  NULL 06+ 500 • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide outp
EK7 (1)  N/A * This is a stress rating only and functional operation of the device at
EK9 (4)  NA The HC595 contain an 8-bit serial-in, parallel-out shift register that
EKB (2)  SAMHWA Notes: 1. The luminous intensity, I v, is measured at the peak of the s
EKC (4)  In addition to having the same functions as port P1, these pins function
EKE (15)  vishay vishay dc00   CAP.   PF   6800.0   8200.0   10,000.0 &nb
EKF (1)  † Stresses beyond those listed under absolute maximum ratings may c
EKG (1)    Designed for ultraClinear amplifier applications in 50 ohm systems
EKH (1)  cient of the circuit. The adjustment range is gener- ally sufficient to
EKI (12)  M/A-COM 2004 dt of greater than 10 kV/µs. This clamp circuit has a MOSFET that
EKJ (1)  Edition 08.95 Published by Siemens AG, Bereich Halbleiter, Marketing- K
EKK (1)  The ADC122S051 is a low-power, two-channel CMOS 12-bit analog-to-digital
EKM (81)  UCC 2006+ Filter Connection (Optional). Use to bias the photodiode cathode. An inter
EKO (2) 
EKR (2)  1) Worst case package. 2) Max number of outputs defined as (n). Data in
EKS (5)  vishay vishay dc02 Supply Voltage Input for the internal PMOS Power Switch. Not internally c
EKV (1)    C High-performance 32-bit RISC Architecture   C High-density
EKW (2)  *Note: Stresses above those listed under Absolute Maximum Ratings may caus
EKY (2)  NIPPON CHEMI-CON 2007+PB A recommended PCB pad layout for the miniature SOT-363 (SC-70, 6 lead) p
EKZ (7)  NIPPON CHEMI-CON 2007+PB Indicates RF part is ON Digital ground Analog ground Analog ground An
E-L (129)  ST The ballast design incorporates two parts, hardware and software. The bal
EL- (47)  N/A module 2005+ Operating voltage: 2.4V~3.6V Directly drives an external transistor PWM
EL. (1)    Matching networks optimized for 802.11g mode operation.   Wi
EL0 (106)  TDK 9+ The leadless chip carrier (LCC) package represents the logical next ste
EL1 (362)  ELANTEC 05+ 32-position digital potentiometer 10 kΩ, 50 kΩ, 100 kΩ
EL2 (606)  02+ The following Functional Description describes the base architecture of
EL3 (26)  ELANTEC SOP20 This is a dual function pin. In the IDT Standard mode, the EFB function is
EL4 (220)  N/A SSOP-16 2003 the ISAnet evaluation adapter card is designed and configured for
EL5 (1160)  INTESIL STK 06+ Input Voltage Noise Non-Inverting Input Current Noise Inverting Input
EL6 (392)  ELANTEC LCC 03+ 16-Bit Monotonic Over Temperature Relative Accuracy: 8 LSB (Max) Glitch
EL7 (519)  EL SOP8 N/A Notes: 1. For Max. or Min. conditions, use appropriate value specified u
EL8 (203)  Intersil sot23-6 06+ Maximum ratings are those values beyond which device damage can occur. M
EL9 (65)  ELNETEC SSOP16 04 Byte write operations are qualified with the Byte Write Enable (BWE) and
ELA (65)  AMD TQFP208 01+/02+/03+/04+ x IFAVM rating includes reverse blocking losses at TVJM, VR = 0.8 VRRM, d
ELB (22)  EVERLIGHT This pin is used to connect the base of an external PNP transistor. The ou
ELC (57)  PANASONIC 1995 Serial address. A 4-bit serial address selects the desired analog input o
ELD (55)  EVERLIGHT Stand Alone Switch On A Chip 8 Ethernet 10/100/1000 ports MII/GMII inter
ELE (54)  ELANTEC SMD 03+ 1. Specifications typical at Ta=+25],resistive load,nominal input voltage
ELF (39)  EVERLIGHT 0403+ Notes : 1. A Retriggerable one-shot multivibrator has an output pulse wid
ELG (1)  ELGA 05-07+ The CNA (cable-not-active) terminal provides a high when there are no twi
ELI (6)  T PLCC The ELINET has internal EEPROM to store the two calibration points. The
ELJ (893)  PANASONIC 3225-221K 100KEP circuits are designed to meet the DC specifications shown in the a
ELK (28)  JAT 05+ Low inductance RF/DC ground connection required below part as bottom groun
ELL (63)  Panasonic As an alternative to a full chip erase, the device is organized into sect
ELM (359)  ELM 00+ The SST49LF080A flash memory device is designed to interface with the L
ELN (1)  N/A SMD 1997 Notice: This document contains information on new products in production.
ELO (1)  Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Si
ELP (12)  JPC 91 READY Ready (Output, active High). This signal can be used to control the
ELR (9)  Panasonic   77 instructions   C-Language friendly architecture   PI
ELS (43)  The devices feature single 3.0 V power supply operation for both read and
ELT (54)  EVERLIGHT 0403+ OUTPUT DRIVE ENABLE (ODE)   The ODE pin is the master output three-s
ELU (28)  N/A The ELU-601 programmable color light-to-frequency converter combines conf
ELV (5)  SMD-44 92 1. Life support devices or systems are devices or systems which, a) are i
ELW (1)    Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm (one layer, 70&mi
ELX (27)  TA = 25C; VCC = +3V, unless otherwise stated. RF frequency = 90MHz; RF in
ELZ (1)  The ADS5423 is available in a 52 pin HTQFP with heatsink package and is p
E-M (4)  AD PLCC20 7.5 ATM Encapsulation and spanning-tree RFC 1483/2684 provides a simple
EM- (16)  SIGMA DESIGNS QFP 95 With the addition of an internal P-channel Power MOS, a coil, capacitors,
EM0 (19)  TM 2000 TSOP The DG201HS is an improved monolithic device containing four independent
EM1 (70)  EPSON TQFP 199943 The initial setup sequence programs the two blink rates/duty cycles for
EM2 (64)  EM DIP 99 The Link Fault Indicator (LFI) output is a TTL-level output that indicat
EM3 (22)  EPCOS 509 250-kHz Sampling Rate 4-V, 5-V, 10 V, 3.33-V, 5-V, and 10-V Input Ranges
EM4 (34)  N/A N/A N/A Advanced+ Boot Block Flash Memory 70 ns Access Time at 2.7 V Instant
EM5 (69)  ETRONTECH BGA 07+ 4-channel CODEC with on-chip digital filters Software selectable A/&micr
EM6 (190)  1. Intersil Pb-free plus anneal products employ special Pb-free   ma
EM8 (124)  SIGMA BGA 07+ The extremely high maximum data rate is achieved by three internal shift
EM9 (118)  EMC Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS
EMA (32)  EMP MSOP8 07+ Input/Output Capacitors: The PT6440 regulator series requires a 100µ
EMB (24)  ROHM SOT-563 05+ Charge termination methods include: Voltage slope (+∆V/dt and +/- p
EMC (117)  ANTI DIP40 07+ The SMF series TVS arrays are designed to protect sen- sitive electronics
EMD (116)  ROHM EEPROM serial clock. When EXTMEM is high, the EEPROM interace is disabled
EME (64)  N/A SOP- 8 DESCRIPTION The HCC40192B, HCC40193B, (extended tem- perature range) an
EMF (41)  ON 06+ 700 Transmit and Receive frames and time-slots may be skewed from each othe
EMG (73)  ROHM N/A q NEW DMOS TOPOLOGY:   Ultra Low Dropout Voltage:   115mV Typ
EMH (51)  EMH 93 The lamp current is limited by a control amplifier that protects the exte
EMI (109)  sumida DIP-4 08+ INPUT Initial Offset Voltage   vs Temperature   vs VS1 &nbs
EMJ (1)  The HT814D0 is a single chip LOG-PCM voice synthesizer LSI with 8.4-seco
EMK (145)  TAIYO . 09+ This document specifies SPANSION memory products that are now offered by
EML (2)  This device operates from a single 3.3-V supply. The device has integrate
EMM (2)  ON 2001 The PFKC03 series offer 3 watts of output power from a package in an IC co
EMN (2)  ROHM SOT-563 05+ CLBs provide the functional elements for implementing the users logic.
EMP (79)  ROHM SOT-563 05+pb Program Store-Enable Output, Active Low. This signal is commonly connecte
EMQ (3)  N/A N/A N/A † Stresses beyond those listed under absolute maximum ratings may c
EMR (39)  FUJI 模块 The DS1388 I2C real-time clock (RTC), supervisor, and EEPROM is a multif
EMS (17)  EM-TECK NA The following figure provides a graphical repre- sentation of the MTC20
EMT (24)  ROHM SOT-563 04+PB IRQ: Interrupt Request. An output for µProcessor operation; normally
EMU (22)  01 Notes: 1. Effective Carrier Lifetime () for all these diodes is 100 ps m
EMV (73)  NIPPON SMD 07+ Included in both the ISAnet evaluation kit and the software/ documentati
EMW (1)  IOR The API8208A eliminates the need of complicated circuitry in voice playb
EMX (21)  ROHM SOT-563 * All specs and applications shown above subject to change without prior
EMY (2)  ROHM SOT-553 Hynix HYMD232G726B(L)8-M/K/H/L series is designed for high speed of up to
EMZ (23)  ROHM SOT-563 05NOPB   Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /C
EN- (2)  The HCC4000B, HCC4001B, HCC4002B and HCC4025B (extended temperature range
EN/ (1)  !Features 1) Built-in bias resistors enable the configuration of an &nbs
EN0 (7)  SMD-8 alpha/skyworks 05+ The ispClock5510 and ispClock5520 are in-system-programmable high-fanout
EN1 (44)  ENTROP QFN 05+ the device has a Sector Protect function which hardware write protects
EN2 (170)  EON 07+ PFC Driver Output. This pin must be connected to the PFC power MOSFET gat
EN3 (57)  99+ 56 TSSOP The HIP6601 drives the lower gate in a synchronous-rectifier bridg
EN4 (14)  Alpha Industries QFN-16 2002 The ISL6434 includes an Intel® -compatible, TTL 5-input digital-to-a
EN5 (59)  ENPIRION BGA 05+ Chip Enable output, to be connected to the CE input of the next PROM in
EN6 (24)  AI 03+   Sharps LH28F016SU 16M Flash Memory is a revo- lutionary architec
EN7 (12)  Alpha Industries SOP 07+ For a VCC value below 1.0V, the FM1233A does not sink very much current
EN8 (43)  INTEL PLCC84 0518 Because the CY7C1353F is a common I/O device, data should not be driven i
EN9 (3)  SMD infineon 04+ Notes: a. Connect DA and DB together externally for single-ended operati
ENA (12)  SIS BGA 3 Turn On Procedures Upon receiving the amplifier, the characterization s
ENB (1)  FUJI • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew)
ENC (32)  MICROCHIP 08+PBF 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 10 Clock Outputs: D
END (6)  02+ BGA The Fairchild Switch FST16862 provides 20-bits of high- speed CMOS TTL-
ENE (1)  NSC 2008 Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an
ENF (95)  pan pan dc99 WARRANTY / REMEDY   Honeywell warrants goods of its manufacture as
ENG (52)  MOTOROLA 2000 TEMP: This is the output voltage produced by the modules internal temper
ENH (2)  PHIL PLCC Each channel has a request bit associated with it in the 4-bit Request re
ENI (4)  03+
ENJ (4)  POWERNET 02+ Aperture Delay (ta). The average (or mean value) of the delay between the
ENL (1)  The MAX5631/MAX5632/MAX5633 are 16-bit digital-to- analog converters (DAC
ENM (2)  QFN alpha/skyworks 03+ Thermal Resistance (Typical, Note 5)JA (oC/W)   PDIP Package . . .
ENN (1)  Current Settling Time, Clocked Mode Current Settling Time, Clocked Mode
ENP (10)  Alpha Industries 0701+   These outputs provide access to the outputs from the RF and refer
ENS (9)  FUJI SMB N/A PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Therm
ENT (1)  ENTRIDIA 06+ 500 2DESCRIPTION In a 1.4 x 7 x 7mm low-profile Ball Grid Array pack- age,
ENV (8)  MURATA The ADC works in fully differential mode from the analog input to the dig
ENW (6)  PAN 1) If change is made to the constant of an external circuit, allow a suff
ENX (2)  ST TQFP64 99 Revision History Features and General Description Pin Description Power
ENY (1)  Digital ground reference. Connected to external crystal to excite the I
ENZ (1)  DONG 1206 05+ Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info,
EO- (1)  AT&T DIP Maximale Streuung des Widerstandswertes bei der Temperatur T in % Nennto
EO1 (6)  N/A QFP-44 l Built-in a watchdog timer l Time period for monitoring and generating
EO2 (1)  EPSON QFP These EPROMs and OTP PROMs operate from a single 5-V supply (in the read
EO3 (4)  HARADA DIP/16 92+ The W29EE512 includes a data polling feature to indicate the end of a prog
EO5 (4)  EPSON BGA 07+ No part of this document may be copied or reproduced in any form or by an
EO6 (2)  Note 5: Set FB to C0.3V, 2.5V and insure that COMP does not phase invert
EO7 (1)  Positive analog supply pins. These pins should be connected to a quiet
EO9 (1)  ALTERA PLCC Provides High-Performance Static Superscalar DSP Opera-   tions, Op
EOA (1)  MARVELL 04+
EOB (3)  ST SOP28 The DS1554 also contains its own power-fail circuitry which automatically
EOC (26)  SEIKO 2000 裸片 The enable input, Pin 9, is buffered for 1024Tosc2 during switching on a
EOD (1)  SEIKO SOT-89 By integrating a rich set of industry leading system peripherals and mem
EOF (2)  ALTERA 9731+ 1 512 (V) x 2048 (H)7.17 mm (V) x 28.67 mm (H)AA1 or 25Adapted optical form
EOG (2)  N/A N/A N/A The RM3283 consists of two analog ARINC 429 receivers which take differe
EOL (1)  LINEARITY   Linearity refers to how well a transducers output follo
EOM (4)  07+ l Built-in a watchdog timer l Time period for monitoring and generating
EON (1)  PH QFP 95   SPICE level output buffer models are available for engineers who
EOS (2)  QFP 02+ Operating voltage: 2.4V~5.0V Directly drives an external transistor Low
EOZ (1)  SMD ON 05+ The 56F802 supports program execution from either internal or external me
E-P (6)  AD PLCC28 Drain-to-Source Breakdown Voltage Gate Threshold Voltage ➃ Gate
EP- (15)  TEC QFP160 Figure 1 shows CCA reported power level versus input power. Note that CCA
EP0 (32)  N/A N/A 03+ The transceiver contains a supervisory circuit to control the power supp
EP1 (1340)  ALTERA SOP As seen in the block diagram, these modules contain a single Light Em
EP2 (1766)  2000 Alteta 6+ The external crystal must be connected as close to the chip as possible
EP3 (316)  ALTERA PLCC28 POWER SUPPLY  Supply Voltages   AVDD5   DVDD  Anal
EP4 (15)  The APA2020A also served well in low-voltage applications , which provide
EP5 (17)  ALTERA DIP-16 05+ Internal, dual, high-performance phase locked loop (PLL) synthesizers/VCOs
EP6 (230)  ALTERA CDDIP24 The WCFS0808V1E is a high-performance 3.3V CMOS Static RAM organized as 3
EP7 (54)  CIRRUS LOGIC BGA 2002   The HYM72V64C756T8 H-Series are high speed 3.3-Volt synchronous dy
EP8 (33)  alt alt dc90 NOTE: Device will meet the specifications after thermal equilibrium has b
EP9 (206)  ALTRA PLCC44 02+   At any given temperature and voltage condition,   tHZCE is l
EPA (75)  PCA Life Support Policy: HY-LINE does not authorize the use of any of its prod
EPB (50)  AETEL   The 833C/W for the SOT-563 package assumes the use of the recomme
EPC (249)  PLCC N/A ROM-less product of the µ PD78078 Counter-measure against EMI noi
EPD (6)  NEC QFP80 07+ One or more of the following United States patents apply: 4,616,197; 4,610
EPE (26)  99+ 43 BGA 2.5% output accuracy (25˚C) Low dropout voltage: 450mV @ 1A (typ,
EPF (2187)  ALTERA O7+ Upon a UV condition the PGOOD signal will pull low when tied high through
EPG (12)  N/A 04+ There are two popular conventions for establishing the rela- tive phasin
EPH (30)  SHINDENGEN 2007 The Texas Instruments HPC3130A is a peripheral component interconnect (PC
EPI (47)  MMC 00 When the device is configured for programmable flags and both LD and WE
EPJ (15)  ece ece dc03 Multi-function Input One (1): If Mode = L (m68 mode), Read/Write* pin,
EPK (9)  Altera PQFP208-2828   Removed 166MHz part from speed bin   Defined IDD specificati
EPL (64)  PANASONIC SOP/32 An external voltage must be supplied to the VRef pin which provides the r
EPM (3516)  ALTERA PWM current drive is integrated with 8 bits of control. Four bits are glo
EPN (9)  DIP Device bus operations are initiated through the internal command regist
EPO (1)  PANASONIC SMD 01+ Luminance bandwidth Chrominance bandwidth (Extended B/w mode) Chromina
EPP (7)  ATRICA Power Management and Signal Level Translators for Two SIM Cards or Smart
EPR (4) 
EPS (95)  ST QFP 07+ External Access enable: EA must be externally held low to enable the de
EPT (9)  ALTERA TQFP 02+ VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pi
EPU (1)   The S8S3122X16 is 4,194,304 bits synchronous high data rate Dynami
EPV (2)  ELAN   The MC100ES6039 is a low skew 2/4, 4/6 clock generation chip desi
EPX (91)  ALTERA BGA 05+ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
EPY (1)  *2) Lamp frequency of inverter may produce interference with horizontal s
EQ- (5)  EXABYTE PLCC28 An attenuator from the CONOUT (control output) to the appropriate VCA con
EQ0 (6)  06+ SMD Always use controlled impedance lines (microstrip, coplanar waveguide, et
EQ1 (3)  bit or any arbitrary channels in ESF mode. The signaling insertion, idle
EQ2 (1)  PLCC Stresses beyond those listed under Absolute Maximum Ratings may cause p
EQ3 (1)  This pin can be connected to either VSS, VCC or left floating. An
EQ4 (1)  When evaluating with evaluation chips and other means, take careful note
EQ5 (2)  NS 07+ 1. Required LO level is a function of the LO frequency. 2. The LO input
EQ6 (1)  PLX 2007 WE904/905 are single-chip FM/FSK transceiver ICs operate between 100 to 10
EQ8 (3)  97   The AMC7123/4 is member of ADDM North Star White/Blue LED driver
EQA (8)  CH1 Soft-Start Input CH5 Enable Input CH6 Enable Input Step-Up Conv
EQB (7)    The NCP304 and NCP305 series are second generation ultra−low
EQC (1)  1) CPD isdefined as the value of the ICsinternal equivalent capacitance w
EQK (1) 
EQN (1)  2008 Acknowledge is a software convention used to indicate successful data t
EQR (1)  PANASONIC 00+   These Hall-effect switches are monolithic integrated circuits with
EQU (4)  N/A 00+ PLCC-44
EQV (9)  MIC
EQW (5)  The TSB17BA1 is a single-port 100-Mbps transceiver used in transporting I
EQX (11)  Genesis Microchip Inc. reserves the right to change or modify the informat
EQZ (8)  Four independent 128-bit wide internal data buses, each con- necting to
E-R (1)  Information furnished by Analog Devices is believed to be accurate and r
ER- (7)  MICROCHIP   TheVIN input should be capacitively bypassed to reduce AC impedan
ER0 (58)  N/A
ER1 (53)  PHOENIIX DIP Production tested at TA = +25C. Maximum and minimum limits are guaranteed
ER2 (26)  VISHAY DO-214 2008+ The amplitude of start pulse öst is the same as the ö1 and &ou
ER3 (36)  08+ FFeatures 1) Corrects distortion in the rising section of audio sig- &n
ER4 (22)  TELEDYNE CAN8 00+ Multi-Function Output Channel A. This output pin can function as the OP2A
ER5 (19)  MOT 06+ SMD DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to
ER6 (4) 
ER8 (5)  LINEAR SMD 03+
ER9 (3)  The information herein is given to describe certain components and shall
ERA (234)  N/A 0402X4 C1=12pf, ATC "B" (100MIL) C2=6.2pf, ATC "B" (100MIL)
ERB (74)  100 天龙伟业 靳先生 The AD5258 provides a compact, nonvolatile 3 mm 4.9 mm packaged solutio
ERC (71)  FUJI Notes:   1. Permanent device damage may occur if the above Absolute
ERD (312)  N/A (3) The products described in this material are intended to be used for s
ERE (7)  10-bit resolution. 12 channels Casting time for serial/parallel convers
ERF (32)  NS DIP 99 When CS is high, or UB and LB are high, the device enters standby mode: t
ERG (227)  PANJIT 2003 Vcc = 2.3V~2.7V, TA = 0C to 70C, unless otherwise specified   -12
ERH (3)  A thermal warning indicator is activated by the DDX-2100 when its junctio
ERI (12)  . • automotive   - AC drives - starter generator   for 12/
ERJ (2838)    The VRE114 series voltage references have the ground terminal bro
ERK (3)  N/A The figure below shows a lump model of the thermal properties of the size
ERL (5)  The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca
ERM (5)  DIP 02+ ALO,BLO,CLO - are the logic inputs for controlling the switching of the
ERN (3)  N/A N/A N/A This hermetically packaged QPL product features the latest silicon and pa
ERO (109)  N/A Available in the Texas Instruments NanoStar™ and NanoFree™ Pa
ERP (2)  The MSA power supply noise rejection filter is required on the host P
ERQ (12)    Both magnetic characteristics are available in a choice of two ope
ERR (1)  ALTERA N/A   To maximize I/O throughput and improve host and SCSI bus utilizat
ERS (62)  RIFA 1210-333 Failure to adhere to the above restrictions could result in a modifica-
ERT (105)  N/A A six byte command (bypass unlock) sequence to remove the requirement o
ERU (1)  It is significant to note that this equation and Figure 7 apply to all 5
ERV (2)  N/A N/A N/A The ISD MicroTAD-16M interrupt pin goes LOW and stays LOW when an Overfl
ERW (4)  Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Co
ERX (105)  N/A floppy disk controller is the 82078 core The serial ports are 16550 compa
ERY (8)  N/A • Host writable message header (4 bytes) for identifica   -ti
ERZ (132)  N/A No external capacitors (919 only) Excellent signal quality Very low jitt
E-S (25)  ST 05/06+ Internal Organization When ORG is connected to VDD or ORG is floated, th
ES( (1)  NS The digital data is supplied to either an AM- or FM-input pin, the outpu
ES0 (37)  95 DIP-20 Conexant products are not intended for use in medical, life saving or lif
ES1 (235)  N/A Combined Current Source and A/D Positive Input for Remote Diode. Connect
ES2 (164)  N/A TSQFP 08+ Note:  1. Stresses greater than those listed under absolute maximum
ES3 (158)  ESS QFP The ISSI ISES3880F/FML is a high-speed, 2,097,152-bit static RAM organize
ES4 (64)  N/A The circuit makes use of a peak hold capacitor, CHOLD, at the output of t
ES5 (56)  N/A DIP28 N/A The operation of the MQ photoelectric sensor area reflective type is ex
ES6 (97)  ESS QFP 00+ State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera
ES7 (32)  ERSO DIP-20 08+ Precision Fixed Operating Frequency KA1M0265R (70kHz) , KA1H0265R (100k
ES8 (38)  INTEL 07+ RECEIVER The receiver input can be either transformer-coupled or capacit
ES9 (35)  N/A QFP 06+ The architecture provides three modes of operation: user mode, superviso
ESA (195)  FUJI TO-220 08+ The 78P7200 is a line interface transceiver IC intended for STS-1 (51.84
ESB (22)  LSI BGA 99 • UltraFast: Optimized for high operating up to   80 kHz in h
ESC (69)  N/A N/A N/A • Wide frequency rangeC1.0MHz to 80.0MHz • User specified tol
ESD (195)  ST 04+ Multiformat video decoder supports NTSC-(M, N, 4.43),   PAL-(B/D/G/
ESE (38)  N/A PANASONIC 05+  Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds300C (
ESF (4)  Clock Enable Input, active LOW. When asserted LOW the Clock signal is rec
ESG (9)  The external bootstrap capacitor is necessary to achieve the fastest gat
ESH (23)  NIHON 00+ Hynix HYMD264G726A(L)4M-M/K/H/L series is designed for high speed of up to
ESI (20)  HITACHI 06+ BOOT BLOCK LOCKOUT DETECTION: A software method is available to determin
ESJ (37)  FUJi This datasheet contains new product information. Myson Technology reserves
ESK (6)  SEC QFP 2001   The serial interface centers on a fourteen bit shift register. The
ESL (19)  NIHON 00+ For more detailed information on cabling options including RS485, transfo
ESM (108)  N/A 2183 Notes:  1. NC pins are not connected to the die.  2. E3 (DNU)
ESN (1)  AEC-Q100† Qualified for Automotive Applications Customer-Specific
ESO (3)  protek 06+ 600   , LTC and LT are registered trademarks of Linear Technology Corpor
ESP (31)  Wide acceptance angle pixel architecture enabling compact camera module
ESQ (72)  SAMTEC N/A 2006 Logic to logic isolator Programmable current level sensor Line receive
ESR (19)  N/A The UDA1384 supports conventional 2 channels per line data transfer confo
ESS (42)  SOP8L The receiver includes a half wave rectifier that rectifies the analog si
EST (21)    The IDT octal buffer/line driver is built using an advanced dual m
ESV (10)  SIEMENS 07+/08+ The IGBT is ideal for many high voltage switching applications operating
ESW (32)  samtec samtec dc05 Input offset voltage is trimmed to less than 60µV. The low drift an
ESX (2)  This is an NTSC/PAL signal switching IC. In PAL conversion mode, a freque
ESZ (1)  KAE 00+ These devices do not normally require heat sinks, however, standard prec
E-T (45)  ST 07+   Extensive applications information for Hall-effect sensors is avai
ET- (18)  29 ET O2+  The NJM2742 is a high speed single supply operational amplifier .T
ET0 (37)  IT 05/06+ Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Different
ET1 (63)  VISHAY DIP DIP ALERT alarm is an open drain, active-LOW output which requires an exter
ET2 (38)  QFP44 The ET2090FOA/ET2090FOA are available in PDIP and SO packages in industry
ET3 (26)  ET DIP 07+   The second mechanism controls the replacement algorithm, when a T
ET4 (39)  N/A 00+ N/A The LT1013 devices can be operated from a single 5-V power supply; the
ET5 (17)  长电 SOT89 05+ EPIC ™ (Enhanced-Performance Implanted CMOS) Submicron Process Pack
ET6 (19)  AD QFP 07+ Output, Pin 14, is suitable for controlling a power MOS- FET. During the
ET7 (13)  EM QFP 00+ Description: Mitsubishi IGBT Modules are de- signed for use in switchi
ET8 (16)  SOP 102 00+ Therefore, do not burn, destroy, cut, crush, or chemi- cally decompose th
ET9 (17)  ETEN QFP Audio Processing l Decodes MPEG1 (layer-1, 2, 3) stereo   channel
ETA (7)  SHARP 90+ For split supply operation, this pin serves as circuit ground. For single
ETB (6)  SYNC - This pin is the input pin for external frequency synchronization.
ETC (185)  ST N/A N/A II. Circuit Design A schematic of the two-stage LNA is shown in Fig. 1. T
ETD (6)  ece ece dc99 Features   ♦ ST-BUS compatible   ♦ 8-line x 32-cha
ETE (5)  FUJITSU TO-3   Features 1) Made of same material as the general purpose chip resi
ETF (2)  FUJI SOP EXPANSION OUT/HALF-FULL FLAG (XO/HF)   This is a dual-purpose output
ETG (12)  04+ Notes: 1. Gate Open 2. Measurement using the gate trigger characteristic
ETH (4) 
ETI (3)  Notes:   1. The Si3056 specifications are guaranteed when the typic
ETJ (11)  PANASONI SMD 05+ Minimum time between read command (i.e., a write to Communication Regist
ETK (18)  QFP ET 04+ 5. Data Access   The ETK3699 series can operate from 2.0V to 5.5V.
ETL (28)  E DIP-24 08+ Two individual input channels o MIC+/MIC-: differential microphone inputs
ETM (7)  TI QFP 99 Stereo Audio DAC C 100 dB A Signal-to-Noise Ratio C 16/20/24/32-Bit Data
ETN (18)  1735  − Dynamic Range:   − 132 dB (9 V rms, Mono) &nbs
ETP (4)  DIP A variety of frequency ranges and packaging options are available. The
ETQ (54)  PANASONIC Features selectable via special function register 50/60 Hz display Lev
ETR (14)  N/A PLCC 07+ The select-control (SAB and SBA) inputs can multiplex stored and real-t
ETS (1)  DC CHARACTERISTICS RHEOSTAT MODE  Resolution  Resistor Differ
ETT (2)  QFP
ETU (2)  1735 • Compact slim body saves space Thanks to the small surface area o
ETX (2)  NEC 06+ 1127 Interrupts : 18 sources, 10 vectors   1. Three priority (low, high
ETY (1)  Differential termination for Stratix devices is supported for the left an
E-U (36)  STM The power management control facilities include socket power control, i
EU0 (8)  SMD SMD Each channel has a mask bit associated with it which can be set to disabl
EU1 (11)  原装无铅 07/08+ The design is based on an ARM® microprocessor that controls the entir
EU2 (4)  —— QFP 07+ In XC4000E, the H function generator is more versatile. Its inputs can
EU4 (1)  N/A In the event that any or all SANYO products(including technical data,serv
EU5 (2)  N/A Input Specifications Voltage range Filter Isolation Specifications Rat
EU6 (1)  The LM45 series are precision integrated-circuit temperature sensors, w
EU8 (1)  The information provided herein is believed to be reliable; however, BURR
EU9 (2)  POWER THERM stock  Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D, DB,
EUA (38)  HOSONIC 05+ One or more of the following United States patents apply: 4,454,488; 4,616
EUC (8)  NA 02+ Package drawings, standard packing quantities, thermal data, symbolizatio
EUF (1) 
EUL (2)  Panasonic SMD 00+
EUM (9)  N/A HALF-FULL FLAG (HF)   After half of the memory is filled, and at the
EUP (53)  EUTECH 06+ A write operation requires an 8-bit data word address following the devic
EUR (11)  N/A QFP 07+ Drain-to-Source Breakdown Voltage Gate Threshold Voltage# ➃ Gate-
EUS (17)  N/A † Stresses beyond those listed under absolute maximum ratings may c
EUT (6)  irgb irgb dc87+   length is 24 bits with triangular PDF dither added for dynamic ran
EUV (1)  N/A N/A 2004 CURRENT LIMIT COMPARATOR  Output Voltage   Normal Mode  
EUW (2)  1735 NEC's EUW252415 contains one NE894 and one NE687 NPN high frequency sil
EUY (1)  There are three kinds of registers on this device, the General Purpose Inp
EUZ (1)  BENEFITS  Enables equipment to meet IEC 61000-4-5  High off-s
E-V (2)  Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode S
EV- (2)  • C compiler optimized architecture/instruction set:   - Sour
EV0 (8)  N/A QFP 1996 These products are not designed for use in life support appliances, devic
EV1 (42) 
EV2 (9)  ST SOP-16 00+  NMOS open drain output structure, which by receiving the HKS and HF
EV4 (2)  Load Regulation Since the IRU1075 is only a three-terminal device, it is
EV5 (4)  Panasonic 3X3-100K The unified program and data memory space of the ADSP-21991 consists of
EV6 (2)  Hynix HYMD512646(L)8-K/H/L series is unbuffered 184-pin double data rate
EV8 (9)  FEELING SOP-18 7.2mm 08+  Common output structure for standard and buffer drivers 
EV9 (8)  EPSON 94+ QFP- Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable)
EVA (755)  ADI 07+ Q1 through Q4 and also additional external output transistors can be prote
EVB (24)  mot 07+ Notes: 1. Test conditions assume signal transition times of 2 ns or less,
EVC (9)  NSI 89 Absolute Maximum Ratings indicate sustained limits beyond which damage to
EVD (6)  IXYS 06+ The DDR SIO operation is possible by supporting DDR read and write operati
EVE (4)  1735 The 5B Series represents an innovative generation of low cost, high perf
EVF (8)  100 天龙伟业 靳先生 The e1217X is an integrated circuit in CMOS silicon gate technology for a
EVG (5)  MOBULE FUJI 04+ The DSP56824 is a member of the DSP56800 core-based family of Digital Sig
EVH (1)  Panasonic DIGITAL INPUTS  DFS, Input Logic 1 Voltage  DFS, Input Logic 0
EVK (46)  . SOT-23 05+/06+ The MC68302 Integrated Multiprotocol Processor Users Manual describes the
EVL (27)  N/A N/A N/A The third overtone mode is not necessarily at exactly three times the f
EVM (703)  PANASONIC 4X4-500R 05+ The EVM1ESW30B524 is a 32-bit edge-triggered D-type flip-flop with 3-stat
EVN (82)  PANASONIC 3x3-33K 05+ Both diodes have similar barrier heights; and this is indicated by corre
EVO (1)  MOT SOP16 04+ Each macrocell can provide true input/output capability. The user can s
EVP (1)  PANASONIC N/A Link aggregation in any combination of up to 4 ports per group Meshed
EVQ (99)  © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
EVR (4)  N/A Operating Range 2-V to 5.5-V VCC Schmitt-Trigger Circuitry On A, B, and C
EVS (16)  ELECVISI This device features an internal 200KHz oscillator, un- der-voltage locko
EVT (4)  FUJI N/A An external sense resistor limits the maximum charge current as a safety
EVU (7)  Interpoints HUMMER™ Hold-Up Module Series provides a single produc
EVY (44)  vitramon vitramon dc73+ (1) LED Current Control and Resistor RLED Selection   The NJU6048 i
EW- (28)  MOT PLCC44 06+ The HS-26C32RH has an input sensitivity typically of 200mV over the comm
EW0 (6)  A powerful program sequencer controls the flow of instruction execution.
EW1 (19)  edt edt dc00 Virtex-E devices provide better performance than previous generations o
EW2 (7)  edt edt dc05 (and other parameters) will be met at the specified input power level an
EW3 (5)  The ISL6434 includes an Intel® -compatible, TTL 5-input digital-to-a
EW4 (6)  AKE 3-lead SOT 08+   The melting temperature of solder is higher than the rated temper
EW5 (10)  edt edt dc99   C Two 64-voice RISC DSP Cores   C Two High-speed CISC Control
EW6 (3)  ? . 04+ Notes: 1. CL = Load capacitance: includes jig and probe capacitance.
EW7 (2)  N/A N/A N/A 8. CPD is defined as the value of the internal equivalent capacitance whi
EWA (9)  . SOT-23 05+/06+ The devices feature single 3.0 V power supply operation for both read and
EWC (1)  The LV221A devices are dual multivibrators designed for 2-V to 5.5-V VC
EWD (11)  168 98+   Input Current, IIN   Input Capacitance, CIN2, 3 LOGIC OUTPUT
EWE (2)  . SOT-23 05+/06+ For applications requiring powerful I/O capabilities, the Z86319 provide
EWG (1)  CONEXANT NA The collision detection threshold can be shifted by applying a voltage to
EWH (1)  ew ew dc88 6. CPD is defined as the value of the internal equivalent capacitance whi
EWI (13)  INTEL BGA 06+ The Digital Receiver Front-end DRX 3960A performs the entire multistand
EWK (1)    Pin 11 is the clamp gate input pin and is driven by a TTL back po
EWL (1)  These N-Channel enhancement mode power field effect transistors are produ
EWM (4)  MOT 04+ QFP-M44P NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in
EWP (1)  STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions
EWQ (1)  Applications include transducer amplifiers, dc amplification blocks, and
EWS (114)  LAMBDA SOP The OP4008B will tune from 0 to 5 volts as shown in the adjacent plot. Fo
EWT (2)  N/A Test Conditions/Comments Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSP
EX- (6)  EX 2. This spec must be met in order to ensure that a correct power on reset
EX0 (94)  N/A op amp. The VCM node shown in the drawing is the VCM output (pin 19). T
EX1 (18)  FUJI 04+ When the die are tested at Atmel, a unique 32-bit serial number is prog
EX2 (16)  Note 12: Skew is defined as the absolute value of the difference between
EX3 (10)  PHILIPS Information provided by Conexant Systems, Inc. (Conexant) is believed to
EX4 (1)  PULSE 06+ MODULE The intended application of these devices and signaling technique is bo
EX5 (5)  PULSE Note 8: VIHCMR minimum varies 1-to-1 with VEE. VIHCMR maximum varies 1 to
EX6 (8)  ACTEL 2002 • Square RBSOA • Low Saturation Voltage • Less Total P
EX7 (1)  The wiper settings are controllable through an I2C compatible digital in
EX8 (3)  99 Hynix HYMD264G7268-K/H/L series is registered 184-pin double data rate Syn
EX9 (1)  DTMF/Pulse switchable dialer 32 digits for redial memory Pulse-to-tone (
EXA (25)  ML PLCC 02+ the device can work also with dynamic ones). Many of its electrical cha
EXB (561)  ZIP-5 The FDC10 (W) series required a minimum 10% loading on the output to maint
EXC (74)  sie sie dc78+ Transmitter Differential Variable Swing Output. Output is CML compatible.
EXD (2) 
EXE (7)  XICOR The above data is derived from fixtured measurements which include 3 paral
EXF (4)  NA 03+ The bq2014 Gas Gauge IC is in- tended for battery-pack or in-system inst
EXG (1)  • Semiconductor laser and photodetector are   integrated throug
EXI (5)  PRX 04+ The KBE00F005A is a Multi Chip Package Memory which combines 1Gbit Nand Fl
EXM (2)  SANYO HYB 02+ The Application Engineering Group is available to assist you with the app
EXO (27)  KSS DIP-8 08+ removal of EEPROM devices. DMS will also allow the system software to b
EXP (9)  32 QTC 8-bit 8051-compatible microcontroller adapts to task-at-hand: - 8, 32
EXQ (43)  N/A N/A N/A Vcc = 5V 10%, TA = 0C to 70C (Normal), unless otherwise specified. Symbol
EXR (5)  gulton gulton dc78+ The SO-8 has been modified through a customized leadframe for enhanced
EXS (13)  N/A • Sub-micron CMOS Process   C High-speed logic and Interconne
EXT (8)  大铁帽 08+ Differential output pair. LVPECL interface levels. Output enable Bank B
EY0 (3)  92  The HYM72V32636T8 Series are Dual In-line Memory Modules suitable f
EY7 (1)  The write enable input is active LOW and controls read and write operation
EY8 (1)  Soft-Start And Hiccup Capacitor Pin. During start up the voltage of this
EYB (1)  NOTES: 1. Stresses beyond those listed may cause permanent damage to the
EYC (1) 
EYD (1)  2008 n 5 Volt Read, Program, and Erase   C Minimizes system-level power
EYF (3)  PAN 2520 05+ Reference input, requires a bypass capacitor of 10 µF to AGND in or
EYG (1)  ESN (Electronic Serial Number), customer code (pro- grammed through AMD
EYH (1)  The FAN53168 is a multi-phase DC-DC controller for implementing high-cur
EYM (2)  [CAUTION]  The specifications on this databook are only given for
EYN (2)  vishay vishay dc00 Note 5: For the purpose of specifying deserializer PLL performance tDSR1
EYS (2)  TAIYO YUDEN The PI90LV047A/PI90LVB047A are quad flow-through differential line drive
EZ- (10)  OMRON The MIC5031 MOSFET driver is designed to switch an N-channel enhancemen
EZ1 (372)  SEMTECH TO263 2002 Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion ti
EZ2 (8)  NA 94+ This combination of excellent dc performance with a common-mode input vol
EZ3 (1)  ST SOT223 06+ Because of the large dynamic range for load current, a selectable gain
EZ5 (22)  The APA4863 also served well in low-voltage appli- cations , which provid
EZ6 (1)  EZKEY DIP/40 95+ accuracy on the transmitted signal frequency Stray capaci- tance can shi
EZ7 (10)  N/A DIP 1996 • TOSHIBA is continually working to improve the quality and reliabi
EZ8 (49)  ZI 05/06+   Standby as low as 55 mA (typ) Mailbox function for message passing
EZ9 (1)  ST TSO-223 05+   Information present at any register is trans- ferred to the respe
EZA (73)  PHI SOP/20 This pin has an on-chip 1.0MΩ pullup resistor. An a.c. coupled si
EZC (10)  AMI 97 Sony Ericsson has earlier announced (June 24, 2003) the decision to increa
EZE (8)  11. INV (pin 44) is used to invert polarity of the TTL compatible  
EZF (33)  N/A Input bus select / I2C clock input. The operation of this pin depends on
EZG (2)  EZCORE 06+ • High-speed access time:   8, 10, and 12 ns • CMOS l
EZJ (14)  PANASONIC 2K/R Integrated tracking capacitor Senses motion of ring magnet or ferrous t
EZM (11)  N/A The EZMPL16H (4 Pin DIP) is robust, ideal for telecom and ground fault
EZP (1)  The LDO is used to filter the ripple on CPO and to set an output voltage
EZR (1)  MX TSSOP TSSOP VPC1 is the bias control pin for the stage 1 active bias circuit. An exter
EZS (1)  The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to suppor
EZU (1)  1 QFP NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may
EZZ (1)  The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,09
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