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T.R (2)  BlueCore4-ROM Plug-n-Go has been designed to reduce the number of externa
T.T (1)  DIP 94 A six-byte command (Enter Single Pulse Program Mode) sequence to remove t
T/N (2) 
T/T (23) 
T-0 (2)  NS SOP-20 9948/SX
T0- (1)  DMT Signal A DMT signal is basically the sum of N inde- pendently QAM
T00 (33)  SSOP Intel® 82551ER [Intel® 82551QM optional] (PCM-9577F) Intel® 8
T01 (41)  Figure 2 shows that the ACE Controller contains multiple interfaces, in
T02 (21)  INNET SO 98+ Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals
T03 (21)  INNET 40L N/A For Schottky barrier diodes, thermal run-away has to be considered as in
T04 (4)    The g-cell is a mechanical structure formed from semiconductor ma
T05 (28)  ST TO The KBE00S003M is a Multi Chip Package Memory which combines 2Gbit Nand Fl
T06 (34)  98 The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerD
T07 (19)  GAON 05+ Notes: 1. Test conditions assume signal transition times of 3 ns or less,
T08 (78)  atmel atmel dc0349 A HIGH on CE0 or LOW on CE 1 for one clock cycle will power down the int
T09 (28)  TRUMPION 99 Product Family Pin Description Asynchronous 4 Page Read & Asynchrono
T0A (2)  The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 9
T0C (3)  INTEL 2007 <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot)
T0D (1)  NSC N/A 2000 Within each processing element is a set of computational units. The comp
T0F (1)    Please be aware that an important notice concerning availability,
T0I (1)  Average forward output current, at a specified current waveform (normally
T0L (2)  If VSB is below either of the two EDV thresholds, the as- sociated flag i
T0M (2)  SOP16M 2007+ There are two methods for reading out the signal from an NMOS linear ima
T0P (6)  TOP TO-220 00+   Description Luminous Intensity per LED (Digit Average)[3,4] Pe
T0R (1)  2008   This is the inverting output of the receive smoothing filter from
T0U (1)  The device is organized as a 16-bit switch. There are two 8-bit switches
T-1 (35)  MOT CDDIP14 • Optimum instruction set for controller applications   •
T1- (23)  MINI 08+ Maximum ratings are those values beyond which device damage can occur. M
T1. (8)  MINI 08+ Notes:  Repetitive rating; pulse width limited by   max. jun
T10 (312)  TECCOR 06+   The joint TLB also contains information to control the cache coher
T11 (187)  Tables 2 and 3 summarize the different behaviour and advantages of both
T12 (116)  Pulse 211   This 16-bit buffer/driver is built using advanced dual metal CMOS
T13 (47)  PULSE 0613+ Thus the first step in designing the antenna circuit is to measure the b
T14 (59)  TM Available inputs are +12V 5% and +5V 5%. Either one or both of these inpu
T15 (61)  +REG IN - is the input pin for applying power to the internal +15V regul
T16 (95)  ST TO The MK1491-06 provides more functionality in a 28 pin package by using a
T17 (21)  TOS DIP Operating Temperature, -55C to 100C Storage Temperature, -55C to 100C
T18 (59)  ST(og stok) BGA 00(hot sell)) Thermal Resistance (Typical, Note 5)JA (oC/W)   PDIP Package . . .
T19 (27)  N/A HITA 04+ Abundant flip-flops Flexible function generators On-chip ultra-fast RA
T1A (4)  PHILIPS 08+PBF • 5 Ω typical ron • Pull-up on B port • Undershoot
T1B (7)  N/A 01+ 102 The output stages switch at half the oscillator frequency, in a push/pull
T1C (7)  HMS DATA INPUTS/OUTPUTS: The I/O pins are used in the A/A Mux interface to in
T1D (2)  The LMV791 provides optimal performance in low voltage and low noise sy
T1E (7)  DIALOG ++ PLCC28 Current Address Register Each channel has a 16-bit Current Address regist
T1F (3)  Allegro Pb−Free Packages are Available 225 mW Rating on FR−4 or FR
T1L (2)  TI DIP-6 SanRex IGBT Module T1L111 is designed for high speed, high current switc
T1N (2)  MOTO TO-252 Hynix HYMD512G726(L)8M-K/H/L series is Low Profile registered 184-pin doub
T1P (11)  ST TO-220 02+ How are these devices different than the other Crystal PCI audio products
T1S (5)  NS SOP-14 SX 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
T1W (1)  NS SOP-14 SX or bidirectional data flow in bursts. An automatic power down feature, c
T-2 (1)  AGERE 03+ The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified sp
T2- (13)  MINI 08+ Built-in oscillator with variable sample rate Single external resistor
T2. (7)  MINI 08+ 专业射频微波 The Rambus Direct RDRAM™ is a general purpose high-performance mem
T20 (58)  The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage
T21 (65)  tfk tfk dc00 1. Stresses greater than those listed under Absolute Maximum Ratings may
T22 (54)  TI SSOP-56 (2) JC data values stated are derived from MIL-STD-1835B which states the
T23 (85)  RCA CAN   Features 1) Built-in bias resistors enable the configuration of an
T24 (40)  TI SMD-8 04+   Operating temperature range is C40C to +85C.   Guaranteed by
T25 (69)  ST TO- NOTES 1Burn-in is available on commercial and industrial temperature ran
T26 (39)  ISD 01+ PLCC68 One method to increase the operating frequency of an integrated circuit i
T27 (24)  铁帽 Output frequency range: 1050 MHz to 1250 MHz Divide-by-2 output 3.0 V t
T28 (46)  MOTOROLA CAN3 Gate leakage current Collector-emitter saturation voltage(Note 4) Inp
T29 (21)  MOT SOP The Si9986 is an integrated, buffered H-bridge with TTL compatible inpu
T2A (9)  PHI SMD Notes: 1. For Max. or Min. conditions, use appropriate value specified u
T2C (2)  The sensitivity of the chip is adjusted by changing the discharge current
T2D (3)  SK TO-252 07+ † Stresses beyond those listed under absolute maximum ratings may c
T2G (1)  SOP 05+ Output enable terminal: no matter in what phase MBI5170 operates, the sig
T2H (1)  sFEATURES qLow Offset VoltageVIO=4mV max qSingle Low Power SupplyVDD=1.
T2K (5)  erase operation, successive attempts to read data from the same memory
T2M (2)  Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating
T2N (1)  MOT . 08+ Drain- Source Voltage Continuous Drain Current, VGS @ -4.5V Continuous
T2P (4)  TECHWELL 07+ • Up to 10-A Output Current • 5-V Input Voltage • Wide
T2R (6)  AGERE 01+ Used as input or output fuses for surge-sensitive compo- nents, such as
T2S (1)  NS SOP-16 SX When 16/68# pin is at logic 1, it selects Intel bus interface and this in
T2X (1)  VCC and GND are the supply voltage pins for the digital control inputs
T-3 (7)  n Serial data input / output n Low dynamic current, 5 µA max. n Lo
T3- (15)  MINI 08+ Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATING
T3. (1)  The 82C37A is designed to be used with an external address latch, such
T30 (50)  HIT TQFP64 2007+ 1. Startup includes both the application of a valid input   source
T31 (31)  TOSHIBA . Precision voltage sensor Two threshold options: 2.93V or 4.63V Stable
T32 (107)  KEMET ELE The MAX104 processes analog input bandwidths that exceed 2.2GHz with 8-bit
T33 (44)  SOP 99+ If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the F
T34 (56)  amphenol amphenol dc04 The LTC®1628-SYNC is a high performance dual step- down switching reg
T35 (328)  04+ The HT6116-70 is a 2K8 bit SRAM. When the CS pin of the chip is set to lo
T36 (16)  amphenol amphenol dc04 Write Enable, active Low. Controls writing of command sequences in order
T37 (31)  ARNOLD SOP 00+ The receiver section of the WE904/905 provide all of the required receiver
T38 (22)  N/A SOT-23 N/A   It is important that the logic used to turn ON and OFF the various
T39 (48)  SI 金属帽 8431 The Hyundai HYM72V16M636AT6 Series are 16Mx64bits Synchronous DRAM Modules
T3A (5)  TOSHIBA QFP 97+ 2. Force IDL Transmit   This enhancement is an additional SCP cont
T3D (3)  SK TO-252 05+ FAN Tachometer inputs are digital inputs with an acceptable range of 0V to
T3F (4)  TOSHIBA O7+ Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
T3G (7)  TOSHIBA DIP8 07+ Requires few external parts Low distortion (total harmonic distortion =
T3K (2)  In a buck converter (the type used by all Fairchild switching controller
T3L (2)  DIP In addition, the CSPEMI306A provides a very high level of protection fo
T3P (5)  Inclusion of TI products in such applications is understood to be fully a
T3R (3)  QFP-64   Vth can be expressed as voltage between gate and source when low o
T3S (3)  DENSO 2000 The incoming bipolar PCM signal, which is attenuated and distorted by t
T3W (13)  ALCATEL(TOSHIBA) BGA 0601+ We developed this new Type 1/1.8 5M-pixel CCD to respond to mar- ket dem
T3Y (3)  PIXEIWORKS 02+ The following charts show measured performance of the PA module in low-
T-4 (4)  The MAX1534 is a high-efficiency, triple-output power supply for keep-ali
T4- (16)  MINI 08+ An active bias circuit can be implemented if the user does not wish to sa
T4/ (1)  NS SOP-14 This is an active high input pin to NM93C06 EEPROM (the device) and is g
T40 (108)  ST 06+ The DRV593 and DRV594 are high-efficiency, high-current power amplifier
T41 (59)  TO-220 Introduced in 1987/88, XC3000 is the industrys most successful family o
T42 (29)  MOTOROLA CAN3 Because of the true 4 quadrant method of output switching, the output sw
T43 (61)  ST 06+  Guaranteed by design. Not production tested.  Sample tested du
T44 (11)  ARNOLD 00+ † Stresses beyond those listed under Absolute Maximum Ratings may
T45 (19)  MOT 00+ 1. Obtaining fully specified performance from the ADS-950   require
T46 (6)  NSC SOP8 A low level on the reset (RESET) resets the internal stack pointers and s
T47 (21)  DSI n/a Wide frequency range Ð 0.01 Hz to 300 kHz Wide supply voltage range
T48 (33)  TEMIC SOP-7.2-28P 6+   Fully static operation and Tri-state outputs   TTL compatibl
T49 (2477)  KEMET 2008+ The MAX3760 evaluation kit (EV kit) simplifies evalua- tion of the MAX376
T4A (2)  This document contains information on one or more products under developm
T4D (1)  International Rectifier does not recommend the use of this product in aero
T4H (1)  NOTES 1Input bias current is specified for two different conditions. The
T4K (2)  TAIYO YUDEN 2007+PB OSCS is a system oscillator I/O pin connected to an external RC to gener
T4L (2)  Description Agilent Technologiess ATF- 501P8 is a single-voltage high l
T4N (3)  MOT . 08+ The 18TQ Schottky rectifier series has been optimized for low reverse lea
T4P (1)  EPCOS 02+ Collector C Emitter Saturation Voltage, IC=-300mA, IB=-30mA Base C Emit
T4R (1)  KEMET 01+ This document is a general product description and is subject to change wi
T4S (1)  The NC7SV19 is a 1-of-2 decoder/demultiplexer from Fairchilds Ultra Low
T4X (1)  This document is a general product description and is subject to change wi
T-5 (24)  CAN6P As a precision CMOS temperature sensor, the FM20 is cost-effective for a
T5- (3)  MINI 08+ 专业射频微波 The Hyundai HYM72V32656T8 Series are 32Mx64bits Synchronous DRAM Modules.
T50 (90)  QFP 99 250 ps propagation delay input to output 50 ps propagation delay dispers
T51 (55)  N/A TEMIC 04+ Most modules operate from clocks derived from Main Clock or a PLL clock.
T52 (210)  KEMET 2006+ Over a Dynamic Range 1000 to 1 Over a Dynamic Range 1000 to 1 Over a Dyn
T53 (45)  KEMET 2007+ l Rectangular-shaped, automatic mounting type l High tactile feedback (va
T54 (20)  [H] PLCC Notes: a. Room = 25C, Full = as determined by the operating suffix. b.
T55 (28)  LUCENT PLCC28 04+ The HMU16/HMU17 are high speed 16 x 16-bit multipliers designed to perf
T56 (34)  EXAR 2007   The SMA series is designed to protect voltage sensitive component
T57 (63)  tfk tfk dc01 FUNCTIONAL DESCRIPTION STAND-BY STATE The external capacitor,Cx, is ful
T58 (31)  TOS 04+ QFP To perform a practical return loss measurement, it is necessary to force
T59 (15)  EXAR 00+ SOP The ICS601-01 requires a minimum number of external components for proper
T5A (39)  KEC TO-220F 04+ (Continued)   • Direct power saving function : Power supply c
T5B (12)  Toshiba PLCC 07+/08+ The CY62137CV18 is a high-performance CMOS static RAM organized as 128K
T5C (4)  SK TO-251 07+ Case: SOD-123, Plastic UL Flammability Classification Rating 94V-0 Moist
T5D (1)  SK TO-252 07+ − Read, program, and erase operations   from 2.7 to 3.6 V &#
T5E (1)  TOSHIBA 9435   2.1.1 Specifications, standards, and handbooks. The following spec
T5F (13)  TOSHIBA 9503 After the software data protections 3-byte command code is given, a byte
T5G (3)  TOSHIBA  2. These limits define the range of operation for which the part wi
T5H (1)    The HCT161A/163A are programmable 4Cbit synchronous counters that
T5J (1)  TOSHIBA The Am79C901A HomePHY is a single-chip device that contains both a phys
T5K (1)  DIP-64 OSC1, OSC2 are connected to an RC network or Crystal (determined by op- t
T5L (4)  2008 or rotating priority. Bus lock allows indivisible read-mod- ify-write se
T5N (2)  TOSHIBA SSOP24 The nominal value of the RF choke L1 is 100 nH. At frequencies below 10
T5S (2)  This datasheet contains LH28F800BG-L/BGH-L specifications. Section 1 pr
T5U (4)  TOSHIBA O7+ The XRT5U87-1B46 (2850) is a dual universal asynchronous receiver and tra
T5V (4)  TOSHIBA QFP 05+ The ADM666A contains on-chip circuitry for low power supply or battery d
T5Y (1)  rising edge of the CLK pin. On the falling edge of the 8th clock the da
T5Z (1)  This terminal provides a high impedance output for the loop phase detect
T-6 (6)  MINI 08+ Power-On Reset Generator Automatic Reset Generation After Voltage Drop
T6- (2)  Layout Consideration The output capacitors must be located as close to th
T6/ (3) 
T60 (128)  vac vac dc99 BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectiv
T61 (44)  TI SOP8 5. ML66Q525B with flash memory programmable with single power supply &nbs
T62 (17)  SHARP Note A: Characteristic data has been developed from actual products teste
T63 (74)  DL 06+/07+   The T63YB-200K-10-D06 is a single-phase DC brushless motor driver
T64 (15)  1741 ST 03+ Recovered Serial Data. These ECL 100K outputs (+5V referenced) represent
T65 (31)  CHIPS QFP80 03+ Life Support Applications These NEC products are not intended for use i
T66 (23)  EXAR SOP-18 98+ † Stresses beyond those listed under absolute maximum ratings may c
T67 (18)  QFP 89+ The AT91X40 Series Microcontrollers integrate several peripherals, which
T68 (27)  TEMIC Input to the on-chip inverting oscillator amplifier To use the internal
T69 (18)  Programmable) versions are available (COP8SGx7 Family). Erasable window
T6A (31)  N/A 1478 When this pin is grounded, an internal resistor divider sets the output vo
T6B (22)  TOSHIBA QFP 00+ • Instruction set to optimize controller applications   Rich
T6C (14)  TOSHIBA QFP44 02+ CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase f
T6D (3)  TOSHIBA QFP-100 01+ Remote On/Off: An open-collector (open-drain) positive logic input that i
T6H (2)  † Package drawings, standard packing quantities, thermal data, symb
T6J (3)  SSOP-16 passes through one or more preheat zones. The preheat zones increase the
T6K (2)  TOS 2000 胶片 Time taken for PLL lock voltage to achieve 90% transition point of the co
T6M (15)  TOSH QFP60 99+ The internal circuit is composed of 2 stages including buffer output, w
T6N (7)  MOTOROLA TO-262 The special detect circuitry monitors the received analog signal to deter
T6P (3)  MOT 00+ Setting up a password is done essentially in the same way as writing data
T6S (5)  TOS QFP 2000 The SST89E5xxRD2 and SST89V5xxRD2 are members of the FlashFlex51 family
T6T (28)  TOSHIBA 0417+ QFP This terminal provides a high impedance output for the loop phase detect
T6U (1)  TOSHIBA 00+ QFP Features • International standard package   miniBLOC •
T6W (26)  4 DIP used to reduce the width of the deadband to acceptable levels, and to ma
T6X (9)  TOSHIBA QFP 2000 The external oscillator mode can also be used with the internal divider
T6Y (3)  Parameters DC Electrical Characteristics Supply Voltage Analog Supply
T-7 (90)  VTEMP LOADING The VTEMP output has very weak drive capability (40µ
T7/ (1) 
T70 (136)  IR T-Module 00+ Motorola, the Motorola logo and VMEexec are registered trademarks of Moto
T71 (76)  TI SOP8 02+ International Rectifiers R5 technology provides high performance power
T72 (282)  LUCENT PLCC-44 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC . 3. These ar
T73 (73)  TLSI 2008 UNLESS OTHERWISE NOTED this document contains PRO- DUCTION DATA informa
T74 (390)  ST SOP16S 2007+ RESET FLAG Proper operation of the RESET circuity is not guaranteed for
T75 (130)  TI CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase f
T76 (26)  LUCENT TQFP 00+ ITU-R BT.656/601 Video Input Separate H/V inputs synchronous with input
T77 (41)  92 NOTES: (1) LSB means Least Significant Bit. One LSB for the 10V input ran
T78 (16)  N/A SMD 94 selectable modes of power reduction idle mode and power-down mode are
T79 (41)  TOSHIBA QFP100 ‡ See The Texas Instruments document, PowerPAD Thermally Enhanced P
T7A (6)  TOSHIBA QFP 1995 Features • 8 LVCMOS outputs for processor and other circuitry R
T7B (1)  TOSHIBA QFP100 The information provided herein is believed to be reliable at press time.
T7C (28)  93 • ML22Q54   The ML22Q54 is a speech synthesis device with a 4-
T7D (12)  QFP Description The ACPM-7813 is a fully matched CDMA Power amplifier modul
T7E (11)  TOS 04+ QFP Vishay Siliconix maintains worldwide manufacturing capability. Products ma
T7F (1)  TOSHIBA 03+ The MAX6746CMAX6753 low-power microprocessor (µP) supervisory circu
T7H (1)  99 (1) Stresses beyond those listed under absolute maximum ratings may cause
T7J (1)  TOSHIBA 04+ (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine
T7K (25)  TOSHIBA QFP 1991 The device can readily control keys over graphical LCD panels or LEDs whe
T7L (39)  TOS BGA 04+ Operating voltage: 2.4V~3.6V Directly drives an external transistor PWM
T7N (18)  aeg aeg dc90 The Virtex-II family is a platform FPGA developed for high performance
T7X (2)  TOSHIBA SOJ 1999 It contains 6 bidirectional and digitally controlled analog switches. A
T7Y (12)  Two IR Ports Multi-Protocol Serial Communications Controllers One IrDA
T-8 (21)  LUCENT Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control Wit
T8- (6)  N/A N/A N/A The CDC913 is a high-performance clock generator with integrated dual 1-t
T80 (46)  PULSE 05+ SMD Linear LDO regulator with 4.75V output 500mA output current capability
T81 (54)  ST TO The LPV321 is available in space saving SC70-5, which is approximately
T82 (48)  ST TO-220F 04+ * CPU: VIA C3 800MHz Embedded CPU * Bus Interface: PCI-ISA Bus * Memory:
T83 (73)  ZILOG DIP-18 02+ The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-
T84 (30)  NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu
T85 (74)  AGERE DIP DESCRIPTION The BTA/BTB20 BW/CW triac family are high per- formance gl
T87 (34)  The sampling, conversion, and activation of digital output SDO are init
T88 (13)  ST 02+
T89 (161)  mhs mhs dc01 Programming of multiple T89C51CC017CTIM in parallel with dif- ferent data
T8A (4)  KEC TO-220F 04+ II, the maximum input current at maximum input voltage, is a measure of
T8C (1)  used. The device crystal connections should include pads for small capa
T8D (5)  TOSHIBA CDIP Reduced Conducted and Radiated EMI Single Resistor Control of Output Swit
T8E (3)  TOSHIBA CPU   • 32-bit RISC (FR series) , load/store architecture, 5-
T8F (13)  TOSHIBA SMD Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Au
T8K (5)  TOSHIBA BGA 0411+ The buck regulator provides a 2.5% output voltage accu- racy. It consumes
T8L (1)  ON 00+ SOP. be applications in which overall performance is being degraded due to s
T8N (1)  50 TO263 04+ body model)..2000V ESD Protection (other pins, human body model)..2000V
T8P (1)   4.3 Screening (JANTX AND JANTXV levels only). Screening shall be in
T8S (1)  N/A NSC 04+ Charge termination methods include: Voltage slope (+∆V/dt and +/- p
T8T (1)  SOP8S 2007+ FEATURES • Compliant with IrDA 1.0 Physical Layer Specificat
T8U (10)  N/A TEMIC 04+ • 0.23 µm Process Technology • Single 3.0 V read, progr
T9- (4)  MINI 08+ PMD warrants performance of its products to the specifications applicable
T90 (86)  DIP This is a dual-function pin. In the CY Standard mode, the FF function is
T91 (29)  TOS DIP • True dual-ported memory cells which allow   simultaneous re
T92 (65)  P&B 224 The component placement around the LDO should be done carefully to achie
T93 (145)  SSOP Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
T94 (27)  ELMOS Each XC9500XV device is a subsystem consisting of multi- ple Function B
T95 (10)  TI SOP8 03+ • Ultra Low On-Resistance   - rDS(ON) = 0.085Ω, VGS =
T96 (17)  N/A The chip-erase mode can be initiated by a six-byte command sequence. After
T97 (17)  AD 1450 The device also has 96 I/O cells, each of which is directly connected t
T98 (18)  TOSHIBA q Operating Voltage8 to 10 V   2q I C BUS Interface q TruSurround
T99 (21)  94 Each of the macrocells on the CY7C371 has a separate associated I/O pin.
T9A (22)  04+ Phase adjustment is available to adjust the relative sampling of the conv
T9G (1)  During an Erase/Program operation, any of the three non-busy banks may
T9M (3)  NOTE: Absolute maximum ratings are limiting values, to be applied individ
T9N (6)  MOTO TO-252 02+ dualoct received from the DQA/DQB data pins of the Channel to be loaded
T9P (9)  1000 The CPUCLK output is programmable to one of three frequencies (50 MHz, 60
T9R (1)  IDT 95+ TON (line voltage control): TON serves three functions. When CT is disch
T9X (3)  Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed.
T9Y (9)  5V Trip Point 5V Trip Point 3.3V Trip Point 3.3V Trip Point Output
T9Z (1) 
T-A (2)  TXR-L 06+   This low failure rate represents data collected from Maxims reliab
TA. (1)  Beneficial comments (recommendations, additions, deletions) and any pertin
TA0 (62)  HP/AGILENT 0102+
TA1 (448)  TOS QFP-64 The Hynix HYM71V16M655HC(L)T8 Series are 16Mx64bits Synchronous DRAM Modul
TA2 (387)  TRIPATH SMD SMD The H8S/2000 CPU can execute basic instructions in one state, and is prov
TA3 (365)  TOS 1900 DIP The DS1481 also supports overdrive communication with overdrive capable
TA4 (166)  TOSHIBA SOT-252 04+ MAX 3000A devices provide programmable speed/power optimization. SpeedCc
TA5 (103)  Note 1:   For Shut Down (SD) current to fall below 1µA requir
TA6 (67)  TOSHIBA 1780 1 When using a dual speed spindle motor floppy drive (DRVTYP pin low) thi
TA7 (1619)  TOS CAN-8P 82+ The signal on the current sense input pin is also connected to the input
TA8 (1419)  TOS 98 Note 5: The HALT mode will stop CKI from oscillating in the RC and the Cr
TA9 (35)  TAEKWANG DIP 91 Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
TAA (115)  IC Please provide the part number and revision number (located in upper right
TAB (13)  PHILIPS 金属帽 4FE9 The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of
TAC (153)  90 RF output and bias pin. Bias should be supplied to this pin through an ext
TAD (45)  92 3. JA is measured in free air with the component mounted on a high effect
TAE (23)  SIEMENS NOTE:2679 tbl 01 1. Stresses greater than those listed under ABSOLUTE MA
TAF (13)  SIEMENS SOP6 00+ The MAX 7000A architecture supports 100% transistor-to-transistor logic
TAG (41)  CAN Schottky Barrier Diode Characteristics Stripped of its package, a Schot
TAH (13)  TI DIP-40 8644 be used in conjunction with the CLOCK ENABLE (CKEN)to cascade several s
TAI (39)  TOS ZIP 2001 For a correct demodulation the signal conditioner needs appropriate inter
TAJ (2044)  AVX . 09+ Exceeding the maximum allowable power dissipation will result in excessiv
TAK (13)  MINI 08+ This document contains device specific information for the rfPIC12F675.
TAL (8)  1WR High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF
TAM (17)  BRAKE - is a pin for commanding the output bridge into a motor BRAKE mode
TAN (12)  VISHAYTFK A force of 1.0 Kg shall be applied to each terminal in the direction of th
TAQ (3)  avx avx dc95 Maximum Tri-State Enable Time  VCC = 2.0V  VCC = 4.5V  V
TAR (63)  TOSHIBA SOT-153 PhaseLink Corporation, reserves the right to make changes in its products
TAS (358)  N/A N/A N/A Trigger Voltage: The measured peak voltage across the ESD suppressor bef
TAT (7)  AVX 电容 2007+   PIN DESCRIPTION This pin controls the gate of an external MOSFET f
TAV (3)  LGE QFP44 The reliability data follows. Some of the data in this report may be gener
TAW (1)  36 O6 Note 5: This parameter is guaranteed by design but is not tested. The bus
TAX (3)  BGA   Pin 16 is the (-) clamp input pin. This pin is the inverting inpu
TAY (4)  N/A DIP 06+ *Stresses above those listed under Absolute Maximum Ratings may cause per
TAZ (31)  TOSHIBA QFP/44 01+ Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port an
T-B (1)  38 TOSHIBA 97+ RESERVED: RES pins are reserved for future device enhancements or functio
TB- (3)  530000 TCL 01+ RS is the parasitic series resistance of the diode, the sum of the bondw
TB0 (45)  DIODES 05+ Intended for voltage monitoring applications, the MIC845 can be used with
TB1 (220)  TOSHIBA DIP-56 02+ As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for
TB2 (148)  Output voltages available for the MCP1700 range from 1.2V to 5.0V. The LD
TB3 (136)  TOSHIBA 2001 This new test method represents the state-of-the-art for nondestructive
TB4 (14)  7500 06+ • Power-save pull-up resistor built-in (AL series) Frequency divid
TB5 (67)  TI 07+ The special built-in green functions allow the efficiency to be optimum
TB6 (252)  SOP 05+ The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core cloc
TB8 (4)  TOSHIBA QFP 2000 NOTES:  1. Dimension are in inches.  2. Metric equivalents are
TB9 (33)  N/A N/A N/A Note: 5. This input level is calculated from the input power delivered t
TBA (191)  ST DIP This device requires the 3-STATE control input G to be set high to plac
TBB (62)  98+ DIP International Rectifier's MUR.. series are the state of the art Ultra fast
TBC (55)  01+ A0 to A10 are address inputs. A0-A10 are used as row address inputs durin
TBD (4)  N/A N/A N/A  Stresses beyond those listed under Absolute Maximum Ratings may ca
TBE (7)  SIEMENS DIP-8 00+ (1) For Tape & Reel Packaging, add a TR suffix to the end of the Part
TBF (1)  PerkinElmer lamps are available in lengths from 5 ½ inches to ov
TBG (10)  TOSHIBA SOP38 0215+
TBJ (7)  The X1 and X2 pins are the input and output, respec- tively, of an inve
TBK (12)  TI DIP-16 98 The 28-pin, 330mil SOIC provides sockets with gold plated contacts at b
TBL (6)  TROY 128/QFP 07+/08+ 4. An optimum layout is one with all components on the same side of the
TBM (36)  TOSHIBA 07+ The ADPCM serial input register is a 5-bit shift register to store the
TBN (1)  ture. Once the end of a byte program cycle has been detected, a new acc
TBP (83)  N/A 0603TEM The 153CMQ isolated, center tap Schottky rectifier module series has be
TBR (5)  MOT 96 The THS9001 is a medium power, cascadeable, gain block optimized for high
TBS (29)  TSSOP54 NOTE: I/V curves were taken using pulse sampling techniques. This results
TBT (2)  ST ZIP-3 ZIP-3 This dual function pin serves as the SYNC and SHUTDOWN input. To synchron
TBV (1)  • IEEE 802.3u D5 repeater and management compatible • Suppor
TBY (2)  PHI TO252 03+ Digital data output pins that make up the 12-bit conversion results of
TBZ (2)  TOSHIBA 07+ Per MIL-STD-202, Method 213, Condition E Per MIL-STD-833, Method 1011, Co
TC- (27)  The SAR, timed by the clock, sequences through the conversion cycle and
TC) (1)  Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t
TC0 (131)  SCIMAREC 3X4-8P 05+ The products may contain design defects or errors known as errata, which
TC1 (1741)  MICROCHIP SSOP Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
TC2 (339)  MICROCHIP 08+PBF Note: 1. All input pulses are supplied by a generator having the followi
TC3 (399)  TOS BGA 04+ In the Byte Write mode, the Master device sends the START condition and
TC4 (1321)  TOSHIBA DIP This hermetically packaged QPL product features the latest silicon and pa
TC5 (3378)  MICROCHIP 08+PBF [Data Slicing] Threshold Capacitor (External Component): Capacitor extra
TC6 (450)  MICROCHIP 08+PBF   Voltage Rate of Change, (Rated VR, TJ = 25C)dv/dt10,000V/ms Maximu
TC7 (4955)  MICROCHIP QFP-44P 6+ The 80C186EB is a second generation CHMOS High-Integration microprocessor
TC8 (302)  TOS SOP24 03+/04+ • Instruction system best suited to controller   • Wide
TC9 (1446)  TOSHIBA Minimum Quiet Time Required between CS Rising Edge and Start of Next Con
TCA (297)  ph ph dc94 The blanking control input on the hexadecimal displays blanks (turns o
TCB (12)  The 3-state serial output for the A/D conversion result. DATA OUT is in t
TCC (85)  TELECHIP.. SOP 06+ control and communications to other components, such as Segmentation an
TCD (330)  TOSHIBA • Two Channel Quadrature   Output with Optional Index  
TCE (172)  ZILOG SOP 03+ POWER SUPPLY  Supply Voltages   AVDD   DVDD  Analo
TCF (77)  ROHM 6.3V33UF-A DUTY CYCLE DEFINITION The MXD2020E/F has two PWM duty cycle outputs (x,y
TCG (7)  TOSHIBA 01+ BB Filter BW Control Dynamic Range Adjust Dynamic Range Adjust Posit
TCH (19)  NIEC TO-263 04+ The PWR_DWN# signal is an asynchronous, active-low LVTTL input that place
TCI (2)  CDIP8 NULL NULL A LOW signal on SR overrides the Select inputs and allows the flip-flops
TCJ (35)  AVX 2007+PB The 256K bytes of Flash program memory are used to store the application
TCK (51)  TANTALUM 03+ pins 4 & 6 connected See application schematic See application schem
TCL (162)  VISHAYTFK SOP5 01+  2000 Infineon Technologies Corp. • Optoelectronics D
TCM (668)  towa towa dc91 1) If change is made to the constant of an external circuit, allow a suff
TCN (56)  TAIYO  IOLLow-level output currentVID = − 1 V,VOL = 1.5 V616mA &nbs
TCO (110)  UNKNOWN 07+ Room = 25C, Full = as determined by the operating suffix. The algebraic
TCP (72)  ROHM 2006+ DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3
TCQ (1)  ON Power Diode Module DD200HB series are designed for various rectifier circ
TCR (25)  TOSHIBA 00+ In order to reduce lock times and prevent erroneous data from being loade
TCS (506)  SAMSUNG N/A Built-in high-withstanding voltage tuning Amplifier Low power dis
TCT (58)  97 The HY51V(S)16160HG/HGL is the new generation dynamic RAM organized 1,048,
TCU (13)  NIEC 03+ Direct Correspondence of Display Data RAM to LCD Pixel Display Data RAM2,
TCV (6)  The SP8480 Series are complete monolithic data acquisition systems, featu
TCW (5)  TOS 00+ SSOP-8 Operating Range In the operating range the functions given in the circui
TCX (34)  ZIOLG SMD OO The CE transmission gate is disabled and CEIN is high impedance (disable
TCY (3)  vishay • CMOS Process Technology • 1M x 16 bit Organization •
TCZ (3)  TAKCHEONG 2005   C Internal Address and Data Latches for 64 Bytes Fast Write Cycle
TD- (21)  DDC 模块 08+ Axial and Surface Mount Power Schottky rectifier suited for Switch Mode
TD( (1)  Notes: 1Tester measures code transitions by dithering the voltage of the
TD0 (44)  HALO 08+
TD1 (198)  06+ TO-263 The TLV2352 is designed using the Texas Instruments LinCMOS™ techno
TD2 (237)  EUPEC 模块 07+特价模块 Notes: (i) For operation below 0 C the external capacitors must bave stab
TD3 (118)  EUPEC 310A,2000V,2200V,2400V,2600V 07+特价模块 Figure 1 presents a simplified, conceptual overview of the XC5200 archit
TD4 (59)  EUPEC SOP Note: The X prefix in a Motorola part number designates a Pilot Productio
TD5 (49)  INTEL DIP 98+ 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 10 Clock Outputs: D
TD6 (921)  TOSHIBA SOP 07+ NOTES: (1) Junction temperature = ambient for 25C tested specifications.
TD7 (83)  AEG SOP The AD581 is recommended for use as a reference for 8-, 10- or 12-bit D/
TD8 (142)  INTEL DIP The EL2245 and EL2445 also feature an extremely wide output voltage swi
TD9 (60) 
TDA (7432)  PHILIPS 03+ QFP NOTES:  1. Dimensions are in inches.  2. Metric equivalents ar
TDB (132)  MODULE The following are trademarks of Conexant Systems, Inc.: Conexant, the Con
TDC (136)  RAYTHEON Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
TDD (18)  PHILIPS DIP N/A † Stresses beyond those listed under absolute maximum ratings may c
TDE (108)  ST DIP DESCRIPTION The HCF4094B is a monolithic integrated circuit fabricated
TDF (67)  TOKO AS6UA25616 Intelliwatt™ active power circuitry Industrial and comm
TDG (7)  TOS The chip enable-controlled access is initiated by CE going active while
TDH (9)  N/A N/A N/A detection, and an FSK voltage comparator which provides FSK demodulatio
TDI (10)  ITT NO The Secured Sector is an extra 64 Kbyte sector capable of being permane
TDJ (1)  • After the subcode Q signal passes the CRC check, it is   ou
TDK (238)  ' 05+ Current Regulation / Light Intensity Control TheISENSEvoltageisfedintoan
TDL (3)  The AFV461 EMI filter will reduce the input line re- flected ripple cur
TDM (13)  NULL MODULE N/A n 5 Volt Read, Program, and Erase   C Minimizes system-level power
TDN (3)  ALLEGRO The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-li
TDO (10)  - - -   The Motorola AM26LS31 is a quad differential line driver intended
TDP (27)  ST Stresses beyond those listed under "absolute maximum ratings" m
TDQ (4)  Write Control (WC). This input signal is useful for protecting the entir
TDR (8)  N/A The SM5009 series are crystal oscillator module ICs that incorporate low
TDS (128)  GIGALINK 07+ Note: 1. Load and line regulation are specified at constant junction temp
TDT (25)  04+ Receive data. These outputs carry 10-bit parallel data output from the tr
TDU (9)  TDI TQFP64 04+ In DPSK mode the 73K322L modulates a serial bit stream into di-bit pairs
TDV (4)  Factor Limits Line Current Distortion To < 3% World-Wide Operation Wi
TDW (3)  MODULE This is caused partly by a slight difference in the VBEs of Q2 and Q3. I
TDX (16)  DIP模块 9645+ *1. Overcharge release voltage = Overcharge detection voltage − Ove
TDY (1)  In single pushbutton mode or when using the digital source input, as th
TDZ (6)  ROHM • Easy Gate 1 switch-off with PNP switching transis-   tors i
TE- (11)  Same package and pin assignment as mask ROM version. 1. LC877400 series
TE0 (33)  TI 01+ TO-3 Up to 37 general-purpose I/O pins (shared with on-chip peripheral I/O p
TE1 (54)  TM 06+ 500 The CY62137CV18 is a high-performance CMOS static RAM organized as 128K
TE2 (555)  INTEL TSOP 05+
TE3 (10)  MOTOROLA Module N/A Efficiency up to 86% 1500VDC Isolation MTBF > 1,000,000 Hours 2:1 Wi
TE4 (7)  TEL 04+ QFP The Nyquist sampling theorem states that band limited signals may be re
TE5 (18)  The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture
TE6 (22)  THOMSON DIP-5P 97+ Power Up and Down Recommendations. There are no restrictions on the powe
TE7 (16)  99 Forward voltage(typ.)   IF=20mA Forward voltage(max.)   IF=20
TE8 (2)  N/A N/A N/A Power Back-up pin(+). . At Li Mode, connect a 0.1u capacitor to GND. LCD
TE9 (1)  TEL DIP 06+ The TE98880/TE98880159/TE98880/TE98880259 are wide- band, 2-channel, noni
TEA (1245)  PHILIPS Specifications in standard type face are for TJ = 25˚C and those wit
TEB (22)  ALLEGRO Double Baud rate bit. When set to a 1, the baud rate is doubled when t
TEC (80)  N/A N/A N/A Caution  Exposing the device to stress above those listed in Absolu
TED (11)  N/A The receive filter is a digital filter that meets CCITT G.714 requirement
TEE (228)  NEC SMD 07+ This link option selects the source of the CONVST input. When this link
TEF (42)  ST Dual outputs, each with independent over-current protection circuitry and
TEG (4)  JRC DIP-8 01 This publication is issued to provide outline information only which (unl
TEH (1)  PHILIPS SMD16 <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot)
TEI (14)  TEI 00+ SOP8   These Hall-effect switches are designed for magnetic actuation usi
TEK (16)  TEKWISSUSA   The FCT257T is a high-speed quad 2-input multiplexer built using a
TEM (178)  NEC 10V10UF-B   The motor is directly driven by IRF511 power MOSFETS in this des
TEN (255)  traco traco dc00 Quick Reference  Slim profile, (0.6-2.0mm thick light guide), and u
TEO (1)  RFT6120 Device Features • CDMA2000 1X Mobile Station Modem chipset
TEP (83)  2008 The ADSP-21262 SHARC DSP is a member of the SIMD SHARC family of DSPs fe
TER (22)  GENRAD 2001 The LM74A is a temperature sensor, Delta-Sigma analog-to- digital conve
TES (209)  NSC *Stresses above those listed under Absolute Maximum Ratings may cause per
TET (8)  97+ Reference Voltage: This output biases to VCCC1.2V. It is used when AC-coup
TEU (1)  Analog-to-Digital Converters  − 24-Bit Linear PCM or 1-Bit Di
TEV (2)  MOT 07+ ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio
TEW (6)  FIT DIP 4 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
TEX (21)  ST BGA 99 1) Connect the electronic load (+) terminal to the   VOUT banana jac
TEZ (3)  ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO a
TF- (13)  SOP-16 98+ Choice of three bright colors Standard T-1¾ package Small mecha
TF0 (29)  N/A 04+ The bq2083−V1P2 contains 512 bytes of internal data flash memory,
TF1 (53)  N/A 0603L Buffer memory address Buffer memory address Buffer memory address Bu
TF2 (106)  CELESTICA 02+  Received Data Output, push-pull CMOS driver output capable of driv
TF3 (39)  N/A 2000 The TF301SC15 is a 6-bit digitally programmed feedback divider designed
TF4 (17)  PHI QFP44 01+ • High to low side isolation of 1000V • Common-mode dv/dt imm
TF5 (17)  OMRON 02+ BGA-352P Drain-to-Source Breakdown Voltage Gate Threshold Voltage# ➃ Gate-
TF6 (10)  sst n/a The crystal must be mounted as close to the device as possible. For max
TF7 (2)    Figure 6 shows V1, the LED drive voltage of the output of inverter
TF8 (11)  SANKEN? 05+ TO-220 One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCO
TFA (44)  TDK SOP 00+ SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18).
TFB (37)  PHI BGA The ispLSI 2096VL is a High Density Programmable Logic Device containin
TFC (28)  RICHSKY DIP 09+ The 78P7200 is a single chip line interface IC designed to work with eith
TFD (102)  VISHAY The conditional skip is activated by instruction. Once the condition is
TFE (13)  convenient upgrade from and/or compatibility to previous 4-Mbit and 8-M
TFF (3)  97+ Advance/Load Input. Used to advance the on-chip address counter or load a
TFG (3)  NOTES: 1 pin #10 = pin #19(internally connected). 2. Do not tie up Vp an
TFH (13)  ZIP-12 05+ • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) 
TFI (1)  ITT PLCC68 00+   passive LCD panels.   • Up to 4096 colors on passive LC
TFK (146)  SIE 01+ Interrupt A and B (Active-HIGH). These pins provide individual channel in
TFL (66)  SUSUMU 0402-2N2 05+ The MCF5249 is also an excellent general purpose system controller with o
TFM (314)  RECTRON 07+ The Hynix HYM71V8655AT6 Series are 8Mx64bits Synchronous DRAM Modules. The
TFN (2)  08+ The UCC1800/1/2/3/4/5 family of high-speed, low-power integrated cir- cu
TFP (40)  TI 100HTQFP 06+ with A10 defining auto precharge) to select one location out of the memor
TFR (15)  LUCENT 06-07+ † Stresses beyond those listed under absolute maximum ratings may c
TFT (9)  SSOP8 2000 The ADSP-21991 has 4K word of on-chip ROM that holds boot routines. The
TFX (1)  TEMIC NA For applications where board space is extremely critical, the TFX60018 i
TG- (12)  HALO 0721+PB 8-bit Resolution ADC Gain Adjust 1.5 GHz Full Power Input Bandwidth (-3
TG0 (39)  HALO 05+06+ The microcontroller instruction set is based on the AT architecture of th
TG1 (107)  TI QFN16 The architecture of the Direct RDRAM allows the highest sustained bandw
TG2 (58)  HALO SOP 97 The Am186ES/ESLV and Am188ES/ESLV microcontrollers have been designed t
TG3 (12)  SANREX 00+ Large area diode chip for medium current photovoltaic by- pass applicat
TG4 (30)  HALO SOP16 1995 The TMAX register is programmed using a standard SMBus Send Byte operatio
TG5 (20)  TIX CAN Input Termination Center-Tap: Each side of the differential input pair CLK
TG6 (9)  HALO 01+ SOP/16 The FB pin provides input to the inverting input of the error amplifier.
TG7 (25)  • Internal oscillator requires no external components • I2C in
TG8 (27)  INTEL QFP 03+ 2. Data labelled Typ is not to be used for design purposes but is intende
TG9 (7)  HALO The CS8920As Ethernet Media Access Control (MAC) engine is fully compli
TGA (16)  TriQuint 05+ These data selectors multiplexers contain full on-chip bina- ry decoding
TGB (1)  ROHM BGA 04+ This device features an internal 200KHz oscillator, un- der-voltage locko
TGC (2)  116 During the clamping operation, the input video signal is passed through t
TGD (5)  ADC (SSI1) Interface: Master mode only; SPI1 and   Microwir
TGF (1)  Ground pin for the PCI outputs PCI clock output. PCI clock output. P
TGI (4)  TGI STK 2004+ The device is available with an access time of 55, 60, 70, or 90 ns and
TGL (56)  gs gs dc95 Receive Data: This is a group of 4 signals, sourced from an external PMD,
TGM (6)  HALO 03+ The asynchronous mode is used for communication withasynchronousterminals
TGO (1)  FUNCTION The M63800FP has seven circuits, which are made of input inver
TGP (1)  (Load as specified in Figure 1; VCC = +2.97V to +5.5V (at the VCC pins); V
TGR (2)  SOP 02+/03 For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is reco
TGS (24)  FIGARO (LX)high-frequency The VC pin provides a connection point to the output of the error amplifi
TGT (3)  METANETICS PQFP-100 The component placement around the LDO should be done carefully to achie
TGU (22)  TRIDENT QFP160 To have a good approximation of the remaining voltages at both Vin and Vo
TGW (4)  Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected bet
TGX (1)  Interfaces to Electrical Cables/Backplane or with Optical Modules PECL V
T-H (6)  AGERE 02+ TQFP The T-HS2N (extended temperature range) and T-HS2NB (intermediate tempera
TH- (9)  module 00+ The Am29LV160B is entirely command set compatible w it h t h e J E D E
TH0 (14)  N/A N/A N/A   programmable horizontal and   vertical expansion ratio - pr
TH1 (60)  Other operating features include an on/off inhibit, output voltage adjust
TH2 (59)  07+ NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pin
TH3 (84)  N/A implement logic functions in the 500- to 800-gate-array complexity. Since
TH4 (14)  THESYS 2001 Because of the consideration for minimized power consumption, the max.
TH5 (80)  00 This monolithic integrated circuit is an adjustable 3-terminal positive
TH6 (15)  ST DIP   This is a complete series of 5 Watt Zener diodes with tight limits
TH7 (43)  MELE QFN-10 4 Note 1: The Absolute Maximum Ratings are those values beyond which the sa
TH8 (27)  TQFP Features Ÿ International standard package  miniBLOC Ÿ A
TH9 (6)  1350 DIP All Typical Values are at VCC = 5 V, Ta = 25C The algebraic convention is
THA (34)  01+ NOTES 1Temperature range B Version: C40C to +85C. 2Typical values are at
THB (24)  DELTA 95 NOTES: (1) Stresses above these ratings may cause permanent damage. Expo
THC (89)  AD 模块 08+ Input gain control for FL, FR, C, SL, SR, and SW channels (0/3.6 dB) Rec
THD (37)  TSC CDIP40 81/82 In addition to a high-speed A /D converter and versatile control capabi
THE (10)  elcut elcut dc02 Supports UXGA Resolution (Output Pixel Rates Up to 165 MHz) Digital Visu
THF (7)  Infineon TSSOP20 03+ The HYM75V32M636(L)T6 Series are 32Mx64bits Synchronous DRAM Modules. The
THG (24)  TOS SOP28W 2007+ PCI Controller Compatible with PCI 2.1 specification. Integrated PCI a
THH (1) 
THI (14)  traco traco dc99 (3) The products described in this material are intended to be used for s
THJ (7)  AVX 06+/07+ With a 16-bit CPU core that enables high-speed arithmetic computations an
THK (11)  Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserv
THL (7)  Note 1. 100KEP circuits are designed to meet the DC specifications shown
THM (40)  04+ SOP REFOUT is a 3.3V CMOS level non-modulated inverted copy of the clock at
THN (23)  AELTA SOP *0049 1.00(31.75mm) PCB Height One Row of SDRAMs on SO DIMM 144-Pin SO DIMM S
THO (4)  ZILOG 00+ 4095 A built in filter attenuates the chroma signal to prevent color burst fr
THP (19)  N/A N/A The MAX8586 single current-limited switch controls up to 1.2A to power US
THQ (2)  FSC   The IN74AC14 is identical in pinout to the LS/ALS14, HC/HCT14. Th
THR (32)  N/A SOP5.2 01+ q Operating Voltage8 to 10 V   2q I C BUS Interface q TruSurround
THS (1672)  TI 07+ IS23SC4418 contains 1024 x 8 bits of EEPROM with programmable write pro
THT (4)  4 PLL architecture Linear frequency programming Independent frequency pr
THU (3)  SHSUN DIP PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each bit on port
THV (2)  DIODE The HY51V(S)16160HG/HGL is the new generation dynamic RAM organized 1,048,
THX (13)  AELTA 9937 Calibrated directly in degrees Fahrenheit Linear a 10 0 mV F scale factor
THY (7)  SEMIKRON MODULE All local logic block outputs are brought back into the GRP so they can
THZ (22)  DELTA SMD 0121+ The extremely high maximum data rate is achieved by three internal shift
TI- (7)  MCL SMD 2000 True Dual-Port memory cells which allow simultaneous access of the same
TI0 (30)  SYNAPTICS QFP 1998 When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As
TI1 (96)  BB 05+ The following charts show measured performance of the PA module in low-
TI2 (47)  964 95+ Features D Low ON-State Resistance (10 W) D ON-State Resistance Flatness
TI3 (71)  Texas Instruments n/a The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ,
TI4 (54)  TI 07+ HY57V281620HC(L/S)T is offering fully synchronous operation referenced to
TI5 (10)  TI 08+  The HYM72V32756B(L)T8 Series are Dual In-line Memory Modules suitab
TI6 (11)  TI SOP Philips Semiconductors 51MX (Memory eXtension) core is an accelerated 80C5
TI7 (12)  06+ 550 Indirect addressing options provide addressing flexibility: base address
TI8 (17)  98 Footnotes: 1) Standard frequency stability (20,25,50ppm & others avai
TI9 (7)  N/A . The TI905BN and TI905BN are designed for applications such as microproces
TIA (7)  MINI 08+ Integrated bootstrap diode Bootstrap supply voltage to 118V DC Fast pr
TIB (313)  TI 07+ Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation
TIC (174)  Power TO-220 07+ In addition, the P8xC557E8 has two software selectable reduced power mo
TID (18)  TI DIP   These devices are designed to be used as encoder/decoder pairs in
TIE (6)  PLCC Maximum ratings are those values beyond which device damage can occur. Ma
TIF (31)  SOP16 The ispLEVER® design tool from Lattice allows large complex designs t
TIG (18)  SANYO SOP8 04+ In the MAX4455 there are two outputs involved in the generation of the OSD
TIH (2)  N/A 06+ 500 NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected w
TII (2)  DIP-30 84+ NOTE: I/V curves were taken using pulse sampling techniques. This results
TIJ (1)  1) Skew is defined as the absolute value of the difference between the ac
TIK (1)    The safe operating area curves indicate ICCVCE limits of the tran
TIL (192)  TI DIP-4 03+ OE controls the impedance of the output buffers. When OE is high, the buf
TIM (139)  TOSHIBA 2-11C1B 09+ During interrupts and subroutine calls, the return address program counte
TIN (45)  03+ The Blackfin processor instruction set has been optimized so that 16-bit
TIO (4)  00+ 470 TSSOP-8 The DAC8580 is a 16-bit, high-speed, low-noise, voltage-output DAC desi
TIP (610)  TI TO-3 07+ FEATURES * Extremely low on state voltage * No need to derate for higher
TIR (15)  TI 07+ DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -
TIS (524)  CAN4 Unless otherwise specified, the following specifications apply for AGND =
TIT (20)  N/A SOP-16 02+ If pin 3 (input ON) is continuously closed, the delay time, td, still ela
TIU (1)  N/A TI 04+ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on S
TIV (4)  COPYRIGH.. DIP-20 02+ The Digital Visual Interface Specification, DVI, is an industry standard
TIX (54)  MOT.PHILIPS CAN3 00+ Digital brightness control input. When this pin is grounded the digital b
TJ- (4)  Unidirectional low-capacitance TVS series for flexible thru-hole mounting
TJ0 (9)  MOT 00+ PLCC84 If the STBY* input (pin 8) is left open-circuit the regulator operates n
TJ1 (9)   Japan Wide   100k/200k L L H H Dont care Dont care Dont
TJ3 (3)  VISHAY VISHAY dc00 Notes: 1. ∆VF for diodes in pairs and quads in 15 mV maximum at 1
TJ4 (2)  Toshiba SOIC-4 07+/08+ The PI90LV02 and PI90LVT02 are single differential line receivers that u
TJ5 (6)  TIGER-JET 07+ Note 1: Power dissipation is 500 mW when mounted as recommended. Derate a
TJ6 (1)  Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin only Input
TJ9 (2)  98 Spartan-IIE devices deliver more gates, I/Os, and features per dollar t
TJA (97)  N/A N/A N/A   Auto & self refresh capability (8192 Cycles/64ms)   LVTT
TJC (1)  VREFL Lch Voltage Reference Output Pin, 3.75V  Normally, connected
TJI (4)  ATMEL TQFP N/A at its data outputs and the voltages tolerated at its data inputs to th
TJM (12)  PARTSNIC Connect control terminal to VIN terminal The quiescent current can be red
TJO (1)  90 The NE5534 and NE5534A are high-performance operational amplifiers combin
TJS (4)  • Input Voltage Range:   36V to 75V • 1500 VDC Isolatio
TJT (1)  TOS 98 • Solid-state potentiometer • 3-wire serial interface •
TJX (1)  Compliance with ANSI SCSI standards for class 1, class 2, class 3, and
TK- (4)  SOP En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 2: P1
TK0 (10)  TOSHIBA TO-3P 05+ The Blackfin processor instruction set has been optimized so that 16-bit
TK1 (1297)  TOKO SOT89-5 06+ Master/Slave Synchronization. When it is open, a signal synchronous with
TK2 (7)  TOKO DIP-8 The baseband filters are 5th order Chebychev and provide excellent matchin
TK3 (14)  TOSHIBA TO-220F 05+ Figure 5 shows the packet structure of the TK30A06J3/TK30A06J3. Payloads
TK4 (5)  DIP 08+ Intel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or Inte
TK5 (13)  TI QFN 2006 The CD74HC390 and HCT390 dual 4-bit decade ripple counters are high-spe
TK6 (56)  TOKO 05++ SOT-23-5 The attached spice model describes the typical electrical characteristics
TK7 (445)  N/A N/A from Normal to Freerun. The Compare Circuit then measures the phase delay
TK8 (12)  . SOP 04+   DAI incorporates two precision clock generators (PCGs), an  
TK9 (12)  DIP-8 1. The maximum operating input voltage and output current of the device w
TKA (8)  RENESAS QFP 04+ ASYNCHRONOUS READ: There are two types of asynchronous reads C AVD pulsed
TKB (16)  Nichicon SOP 120   The equations are developed to predict the time it takes the RC c
TKC (7)  N/A The HC533, HCT533, HC563, and CD74HCT563 are high-speed Octal Transpare
TKD (8)  NEC SMD 00+ Selects Positive or Negative Edge Control and High or Low output drive st
TKE (2)  SSOP16 02+ When the configuration process is finished and the device starts up in
TKF (3)  4238 TFK 90+ Byte Write Following the start signal from the master, the slave address
TKI (2)  Loss of Lock indicator output. Asserted when internal PLL is not tracking
TKM (7)  DAEWOO The standby function is provided by the STBY* control, pin 3. If pin 3
TKO (3)  N/A PHILIPS 04+ The high-speed switching of LVDS signals almost always necessitates the u
TKP (32)  Available in the Texas Instruments NanoStar™ and NanoFree™ Pa
TKR (40)  PAN/KAIMEI ELECTRONIC   Please be aware that an important notice concerning availability,
TKS (7)  SOP   The Motorola accelerometers contain an onboard 4-pole switched ca
TKT (3)  .  DVDD is the power supply for the I/O pins while CVDD is the power s
TKV (1)  ASUS QFP 02+ COMP and FB are the available external pins of the PWM converter error
TKW (3)  Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Ga
TKX (4)  TEKLOGX 07+   Please be aware that an important notice concerning availability,
T-L (1)  The UPC2721 output amplifier is a single-end push-pull ampli- fier desig
TL- (58)  99+ DIP The device fully supports live-insertion with its Ioff and power-up/ dow
TL. (1)  PECL, LVPECL, ECL, LVECL, HSTL Clock or Data Inputs. Internal 75kΩ
TL0 (1189)  TI,MOT 04+ • UL Certified No. E209204 • 600V-30A 3-phase IGBT inverter b
TL1 (530)  ti ti dc97 controller/timers, a message unit with an Intelligent Input/Output (I2O)
TL2 (352)  TI 06+ The bq29400, bq29400A, bq29401, and bq29405 are BiCMOS secondary protec
TL3 (406)  TI SOIC?(D) | 8 07+/08+ Direct interface with 5 V to 1.8 V logic levels Supports Independent, Syn
TL4 (1010)  ST TO92 07 The ISD MicroTAD-16M interrupt pin goes LOW and stays LOW when an Overfl
TL5 (310)  TI 07+ The R1RW0408D is a 4-Mbit high speed static RAM organized 512-kword 8-bi
TL6 (35)  tos dip Interrupt active low open-drain output. This output is enabled when Bit
TL7 (657)  PHI SMD 97+ Hynix HYMD216726A(L)6J-J series incorporates SPD(serial presence detect).
TL8 (176)  TOSHIBA 06+ 5000   When the frequency of V is less than that of R the 12140 behaves
TL9 (24)  2400 00+ 11.1 United States export laws and regulations prohibit the exportation o
TLA (93)  . . 03+ ANALOG I/O   8-Channel, 400kSPS High Accuracy, 12-Bit ADC   O
TLB (17)  plete control and drive circuit. It has high efficiency phase shift cho
TLC (3696)  ti ti dc04 WARRANTY / REMEDY   Honeywell warrants goods of its manufacture as
TLD (20)  TI SOP-14 01+ The HYM7V65801B Q-Series are Small Outline Dual In-line Memory Modules sui
TLE (1305)  TI 07+ A buffered output-enable (OE) input can be used to place the eight output
TLF (14)  tfk tfk dc91 CAUTION: These devices are sensitive to electrostatic discharge; follow p
TLG (48)  N/A   While in user mode, the RC4700 provides a single, uniform virtual
TLH (106)  VISHAY DIP 04+ The average output from PC3, fed to the VCO via the low-pass filter and
TLI (11)  TEXAS 96+ DIP-16P Supports 100 Mbytes/sec sustained Fibre Channel data transfer rate Init
TLJ (4)  AVX 2007+PB The H8/3644 Series has a system-on-a-chip architecture that includes such
TLK (156)  TI 07+ Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes
TLL (17)  DIP 20000 散新/原装 Carrier Detect (Active-LOW). These inputs are associated with individual
TLM (69)  PARTSNIC PF The FS6282 is a monolithic CMOS clock generator IC designed to minimize c
TLN (25)  TOSHIBA东芝 Transceiver I/O Truth Table The outputs (LED and RXD) are controlled b
TLO (61)  (1) An export permit needs to be obtained from the competent authorities
TLP (1995)  DIP 06+ If the byte pointer is set to 0, the byte pointer flag selects the least
TLQ (1)  06+ 3000 This is a data port that can be programmed to bring out internal signals
TLR (58)  †These options are available on some devices. Please see the table
TLS (263)  TEXAS 60 QFP READ: The AT29LV1024 is accessed like an EPROM. When CE and OE are low a
TLT (8)  QFP208
TLU (19)  tfk tfk dc00 BPMODE (TPS2074) or BPMODE (TPS2075) is an output that signals when the d
TLV (3744)  TEXAS 00+ Left channel positive output in BTL mode and SE mode. Supply voltage Lef
TLW (47)  AE 06+/07+   Ground referenced outputs   High PSRR   Available in sp
TLX (4)  tosh tosh dc96 Used as external reference input when internal reference is disabled (i.e
TLY (46)  tosh tosh dc01 COMPRESSED GCI MODE   In GCI compressed mode, one GCI frame consists
TLZ (75)  VISHAY LL34-2.4V The 288-Mbit Direct Rambus DRAMs (RDRAM) are extremely high-speed
T-M (2)  N/A The second is the programmable 16- or 32-bit-wide DRAM interface that a
TM- (49)  N/A   Switching behavior is most easily modeled and predicted by recogn
TM0 (11)  95 8-Bit Resolution 20 MHz Sampling Rate DNL = +1/2 LSB, INL = +1 LSB (typ)
TM1 (158)  ST 07+ additional logic Full synchronous operation on both ports C 4ns setup to
TM2 (180)  RT pin provides oscillator switching frequency adujstment. By connecting
TM3 (82)  MITSUBSH 04+ Single chip, 8-port Gigabit Layer 2/3/4 switch/router High level of in
TM4 (123)  CHIPS BGA N/A (6) Output Driver Control Function   By setting HALTB pin to L, hig
TM5 (135)  AT&T 2007 The available range of SPD series pressure sensors allows for a wide rang
TM6 (28)  REAL 99+ QFP AfT = exp((Ea/k)*(1/Tu - 1/Ts)) = tu/ts AfT = Acceleration factor due to
TM7 (25)  A general-purpose data register file is contained in each processing ele
TM8 (79)  TIGEM The PTN78020A is a series of high-efficiency buck-boost-integrated switch
TM9 (86)  1850 If VPBDIV is non-zero, write all zeroes to VPBDIV before reading or writin
TMA (41)  TI DIP16 04+ 4.5VC5.5V operation CMOS SRAM for optimum speed and power Low active pow
TMB (47)  sgs sgs dc99 • C compiler optimized architecture/instruction set:   - Sour
TMC (755) 
TMD (218)  TI - Low current consumption:   In operation: 100µA max.  
TME (27)  0 0 0 GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic
TMF (55)  AUK 00+ Note 1: Absolute maximum ratings are DC values beyond which the device m
TMG (87)  SANREX TO-220AB2 04+ Control of the device is via a simple high speed serial bus, compatible wi
TMH (26)  01+ QFP Six and eight channels of EMI filtering Utilizes Praetorian™ induc
TMI (4)  TI SOP Host HCI Transport (UART) The high speed UART interface provides the phy
TMJ (5)  EUTECTIC PBGA N/A The 2 decoders are a series of CMOS LSIs for remote control system appli
TMK (263)  TAIYO . 09+ An active LOW reset input allows the PCA9548A to recover from a situation
TMM (436)  ST SDIP-42 N/A Test Procedure 100% production tested and QA sample tested per QA test p
TMN (3)  02+ 16 This is the active high output drive signal for the (first) phase A win
TMO (39)  N/A N/A N/A Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
TMP (4922)  QFP 95 Radiation Hardened up to 1 x 10 6 Rads (Si) Single Event Burnout (SEB)
TMQ (1)  DSP QFN 2006 The TPS6021x circuits consist of an oscillator, a voltage reference, an i
TMR (34)  TOSHIBA QFP 0428+ The STR73xF requires an external 4.5 to 5.5V power supply. There are two
TMS (4219)  N/A N/A N/A SYNC is a positive edge triggered input with a threshold of 1.5V. SYNC sho
TMT (8)  DSP N/A 2007 Like all members of the FLASH370i family, the CY7C371i is rich in I/O res
TMU (2)  Any commands written to the chip during the embedded programming cycle
TMV (29)  07+ The Fairchild Switch FSTU3253 is a dual 4:1 high-speed CMOS TTL-compatib
TMW (1)  MARUBUN 00+ QFP-M64P DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3
TMX (371)  TI BGA 05+ Parameters Supply Voltage VPRF, VPS2 DSOP IBBP, IBBM, QBBP, QBBM RFOP,
TMY (2)  PWI SOP-8 2004 Relative accuracy g0 19% error maximum (DAC0808) Full scale current match
TMZ (4)  N/A 05+ Information in this document is provided in connection with Skyworks Solut
T-N (5)  Processor Socket Chipset System memory (GB) DIMM slots Flash EPROM Sy
TN- (6)  NA 03+ 2.1 Subject to the conditions herein and upon initial use of the AMBE-200
TN/ (1)  † Notice: Stresses above those listed under Maximum Ratings may ca
TN0 (84)  VISHAY SOT-23 07+(ROHS) The 7640 group, an enhanced family of CMOS 8-bit microcontrollers, offers
TN1 (70)  MITSUBISHI Beneficial comments (recommendations, additions, deletions) and any perti
TN2 (191)  N/A Input voltage range: 2.7V to 6.0V Dual, independent 150mA LDOs Error f
TN3 (13)  N One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL On
TN4 (28)  袋装 The internal circuit is composed of 4 stages including buffer output, wh
TN5 (36)  sgs sgs dc80+ CIS signal is level shifted to VRB in order to use the full range of the
TN6 (41)  FSC TO-226/TO-92L 3 Information furnished is believed to be accurate and reliable. However, S
TN7 (7)  Functional improvements have also been implemented in this family. The U
TN8 (231)  INTEL PLCC 08+
TNA (5)  N/A SANYO 04+ The information, diagrams, and other data in this manual are correct and
TNB (3)    2.1 General. The documents listed in this section are specified in
TNC (5)  Intel 06+ 1000 Each work position in the register is clocked by a control flip- &
TND (73)  ALLEGRO DIP 06+ The voltage-controlled oscillator (VCO) receives the filtered error signal
TNE (345)  TEX QFP Serial-test information is conveyed by means of a 4-wire test bus, or TAP
TNF (1)  Note 4 For a power supply of 5V g10% the worst case output voltages (VOH a
TNI (1)  The RM3183 is a dual line receiver designed to meet all requirements of
TNK (2)  POWER tions under no signal (open circuit) conditions In addition in the singl
TNL (6)  N n/a   The SY10EP89V is a differential fanout gate specifically designed
TNM (1)  N/A 0603X510P8R Feedback Voltage and Short Circuit Detection pin. It is the inverting inp
TNO (2)  The recommended input capacitance is determined by 350 milli-amperes (rm
TNP (182)  TOSHIBA 05+ DESCRIPTION The ACT02 is an advanced high-speed CMOS QUAD 2-INPUT NOR
TNQ (1)  simi simi dc98 For optimum thermal performance in a natural convection application, the
TNR (50)  NIPPON SOT 05+ The RC5051 is a programmable synchronous DC-DC controller IC. When desig
TNS (5)  05-07+ This parameter has to be as low as possible in order to reduce switchin
TNT (28)  00+01 PBGA For Schottky barrier diodes, thermal run-away has to be considered as in
TNU (1)  is sampled at the reference frequency to give the fine error signal, PDA
TNV (2)  The MPC7455 and MPC7445 are implementations of the PowerPC™ microp
TNW (1)  mains high transmit data (TXD) is encoded out to the trans- mit-driver p
TNX (3)  PHILIPS 06-07+ be applications in which overall performance is being degraded due to s
TNY (139)  POWER 04+ SYMBOL PARAMETER Gate Driver IGONGATE Pin Current IGOFFGATE Pin Current
TO- (12)  MINI 08+ This is Preliminary document release. All specifications are subject to ch
TO1 (6)  VIS SOP 1999   The ISP2200A firmware implements a multitasking host adapter that
TO2 (14)  SIG 8427 The information provided herein is believed to be reliable at press time.
TO3 (11)  N/A INNET 04+ reverse bias leakage currents, and are typically less than 1pA at room t
TO4 (5)  N/A 2502   Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS
TO5 (4)  MOTOROLA TO-61 Four dedicated test pins are used to observe and control the operation of
TO6 (2)  SOP14 06+ Note 8: Maximum output current is tested with a load of 3 mH, VCC1 = +15V
TO7 (7)  SSOP-20 99+ The baseband inputs in Cartesian I and Q format control the amplitude an
TO8 (7)  T SOP16S 2007+ The bq2050H determines battery capacity by moni- toring the amount of cur
TO9 (9)  DIP 93 Direct interface with 5 V to 1.8 V logic levels Supports Independent, Syn
TOA (17)  mot mot dc94 Recommended Application Circuit Components  ComponentRecommended Val
TOB (12)  SAMSUNG The 16K EEPROM devices require an 8-bit device ad- dress word following a
TOC (17)  07+ a. HYB: designator for memory components   25D: DDR-I SDRAMs at Vdd
TOD (11)  OASIS N/A The ATTOD-326HBB is accessed like a Static RAM for the read or write cyc
TOF (10)  1850 2. Regularly and continuously improve the performance of our products, pr
TOG (5)  kitagawa kitagawa dc06 The usual method for implementing the low-battery warning featured in most
TOH (9)  N The W29EE512 includes a data polling feature to indicate the end of a prog
TOI (13)  02+ MSOP8 On a single 5V supply, the LT1990 has an adjustable 85V input range, 70dB
TOK (1)  DIP   PAGE operations allow faster data operations (READ, WRITE or READ
TOL (35)  TRACO 06+ C Free High performance Development environment   (IDE) based on Vi
TOM (28)  NEC TQFP 01+ The Serializer transmits serialized data and clock bits (10+2 bits) from
TON (4)  • DigitalClarity™ CMOS Imaging Technology • System-On-
TOO (6)  5452 SSOPB 2003 Reading from the device is accomplished by enabling the chip (CE1, CE2,
TOP (364)  728 POWER 00+ KEY FEATURES (continued) Integrated Power-On-Reset (POR) Generator Flex
TOR (40)  MAX TSOP   •PCprogram counter register   •SRStatus register
TOS (27)  OASIS 0403+ The FMS6346 provides an internal diode clamp to support AC- coupled inpu
TOT (43)  TOSHIBA 0343 Notes: 1. In accordance with the given electro-optical characteristics,
TOU (8)  SAMSUNG 01+ The DS40MB200 is a dual signal conditioning 2:1 multi- plexer and 1:2 f
TP- (34)  N/A DIP42 04+ • 3V, single power supply operation - Full voltage range: 2.7-3.6
TP/ (1) 
TP0 (127)  SILICONI CAN3 † Stresses beyond those listed under absolute maximum ratings may c
TP1 (179)  MAX n/a 99   Typically, the MSK 3554(B) has an input offset voltage of less th
TP2 (131)  SUPERTEX SOT-89 02+ In normal application the RF input is interfaced to the selected mixer osc
TP3 (435)  DIP-16 N/A A typical application of the TV-SAM is a real-time interfield image proce
TP4 (30)  SSOP Discontinuous mode operation provides high efficiency operation at light
TP5 (117)  SN SOP16 A Servo-Tek DC tachometer generator provides a convenient and economica
TP6 (50)  TOPRO QFP 06+ Included in both the ISAnet evaluation kit and the software/ documentati
TP7 (19)  TI The AT91X40 Series Microcontrollers feature an External Bus Interface (EB
TP8 (146)  90 This would allow the system to always power-up to a preset value stored
TP9 (11)  ST 01+ 3 Continuous Drain Current, V GS @ 4.5V Continuous Drain Current, V GS @
TPA (820)  TI MLP   Full-Scale Gain Error   Bipolar Mode Gain Error   Bipol
TPB (24)  sgs sgs dc01 NOTES: 1. Stresses beyond those listed may cause permanent damage to the
TPC (457)  NEC 02+ The XC7336 can be used in systems with two different supply voltages: 3
TPD (118)  TOSHIBA 98 Data out is the same polarity as data in. The output is in the high-imped
TPE (1)  SANYO SOT-563 05+ Stresses above those listed under Absolute Maximum Ratings may cause perm
TPF (5)  The high-resolution (HR) SHARE feature allows even HR pins to share the
TPG (8)  QFP 98 Also included in the measurement routine is logic to handle reverse-curr
TPH (5)  C 512K-Bit Internal Program/Cache    (16K 32-Bit Instructions)
TPI (287)  1/ Parameter guaranteed by line and load regulation tests. 2/ Bandwidth
TPJ (3)  OMRON 02+ SOP Operational Modes Open Mode Scan Mode Windowing the Video Field Temp
TPK (1)  TPK 04/05+ Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem
TPL (21)  TEPA 300 Through dynamic, symmetric-mutual authentication, data encryption, and th
TPM (106)  AVX 2007+PB An Intel 8254 timer-counter (or functionally equivalent device) generates
TPN (9)  ST 99 Available inputs are +12V 5% and +5V 5%. Either one or both of these inpu
TPO (9)  SILICONIX 23 The IR2136/IR21362/IR21363/IR21365/IR21366/IR21367/IR21368(J&S) are h
TPP (38)  TEXAS SOT-153 Hynix HYMD264726B(L)8-M/K/H/L series incorporates SPD(serial presence dete
TPQ (23)  ALLEGRO . accompanying wiring and circuits must be kept insulated and dry to avoid
TPR (15)  9751 8 Note: Absolute maximum ratings are DC values beyond which the device may
TPS (8628)  TI 07+ • Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGUR
TPT (7)  DIP 1997 DEVICE OPERATION The operating modes of the M27C256B are listed in the
TPU (30)  ITT DIP • Platinum Tri-Metal System   High Temperature Stability R
TPV (33)  rf n/a See the Texas Instruments document, PowerPAD™Thermally Enhanced Pac
TPW (12)  MURATA SMD 08年环保 Operating voltage: 2.4V~3.6V Directly drives an external transistor PWM
TPX (2)  TEXAS DIP64 98 Designers using the THS4271 are rewarded with higher dynamic range over
TPZ (3)  QFP 0032+ VCS2 is an external control voltage input that controls the peak-to-peak
TQ- (4)  TRIQUINT 0522+ In dual power supply applications the ISL6227 monitors the output voltage
TQ0 (3)  N/A 01+ This is Preliminary document release. All specifications are subject to ch
TQ1 (10)  The input stage contains an Automatic Gain Control (AGC) amplifier to amp
TQ2 (102)  NAIS DIP-10 02+ Time taken for PLL lock voltage to achieve 90% transition point of the co
TQ3 (6)  TRIQUINT SOT23-8 Selectable bias modes that optimize efficiency for different output pow
TQ4 (19)  PAN DIP 03+ Inclusion of TI products in such applications is understood to be fully a
TQ5 (18)  TRIQUINST 03+ Collector-to-Emitter Breakdown Voltage Continuous Collector Current (Fi
TQ6 (1)  TQS SOP 99+   • 0.13µ CMOS design allows industrys lowest power &nbs
TQ7 (10)  TSSOP 00+ Tiny SOT−353 and SOT−553 Packages 2.7 ns TPD at 5 V (typ) So
TQ8 (22)  3 TRIQUINT OO ADS: Adaptive Delay Set. This function sets the ratio be- tween the maxi
TQ9 (39)  N/A N/A N/A The device supports low-power standby operation. When the reset input (RS
TQA (3)  QFP   This low failure rate represents data collected from Maxims reliab
TQC (1)  Input voltages exceeding the input overvoltage shutdown specificatio
TQD (7)  stock The offset adder and the reverse-carry adder are in parallel and share co
TQF (17)  SIEMENS 08+ o 8-Channel Single-Ended or 4-Channel   Differential Inputs o Sing
TQG (1)  Notes: 1. For Max. or Min. conditions, use appropriate value specified u
TQL (2)  TriQint DFN2015-6 06+ System Considerations The power switching characteristics of Advanced C
TQM (23)  Triquint QFN-12 06+ • High performance ferrite core is used in this epoxy   confor
TQN (7)  Allows Safe Board Insertion and Removal from a Live Backplane Adjustable
TQP (9)  TRIQUNT 03+ • Plastic package has Underwriters Laboratory   Flammability
TQS (34)  TRIQUINT 05+ The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced
TQW (3)  SVCC 模块 模块 • Three channel video reconstruction filters • YUV/RGB
TQX (2)  Max. UnitsConditions CCCSVDS = 50V, ID = 29A 89ID = 29A  32nC VDS
TQY (2)  TELEFUNCEN DIP-6 99 The nominal photosensitive area is made up of 2048 x 2048 useful pixels s
TR- (29)  10-W/Channel Into an 16-Ω Load From a 17-V Supply Up to 92% Effici
TR. (1)  LITTELFUSE 2512-2.5A 05+ The center-pin configuration reduces lead inductance when compared to the
TR/ (21)  reducing the video output level is to incorporate a dual tuned circuit i
TR0 (35)  AGERE BGA The Si9712 operates off the 5-V supply and has built-in level shifting f
TR1 (88)  COOPER 1808-7A Chroma Output/Green Output A 75 Ω termination resistor with short t
TR2 (94)  Hewlett-Packards HSMS-2850 family of zero bias Schottky detector diodes
TR3 (55)  RFM CLCC 9949+ Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Pack
TR4 (28)  Infineon   The 33099 is designed to regulate the output voltage in diode-rect
TR5 (21)  Composite Video Output A 75 Ω termination resistor with short trace
TR6 (47)  The reference signal is at 1700 Hz, (the same frequency for BELL 202 and
TR7 (11)  ROHM SOT-323 05+ High-Performance Crossbar Switch. A high-performance crossbar switch acts
TR8 (39)  N/A SOP-8 00+   Designed for use in solid state relays, MPU interface, TTL logic a
TR9 (37)  N/A DIP 06+ The TS831 ultra low power integrated circuit incor- porates a high stab
TRA (43)  TOSHIBA SOT-153 2007 MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to t
TRB (6)  TI 03+ Introduction The IRU1075 adjustable Low Dropout (LDO) regulator is a thr
TRC (37)  TRC DIP 1997 Notes: (1) Clip mounting (on case), where lead does not overlap heatsink
TRD (9)  ST 00+ QFP Application areas include transducer amplifiers, DC gain blocks and all t
TRE (7)  WISEVIEW 06-07+ Edition 02.96 Published by Siemens AG, Bereich Halbleiter, Marketing- K
TRF (278)  04+ Output enable puts data outputs into high impedance state Easily expandab
TRG (6)  4X4-10K To allow for dc coupling to ADCs, its unique output common-mode control
TRH (5)  AGERE BGA Pb 05+
TRI (24)  ST BGA up to 133 MHz in .25µ (173 Dhrystone MIPS) 1.3 Dhrystone MIPS per
TRJ (5)  * ESD applied to input / output pins with respect to GND, one at a time.
TRK (8)  1850 The internal circuit is composed of 3 stages including buffer output, wh
TRL (7)  SOT-252   Temperature range is −15C to +105C, typical at 25C.  
TRM (25)  JRC SOIC-16 07+/08+ Resale of TI products or services with statements different from or beyon
TRN (27)  SK The XC6203E series are highly precise, low power consumption, positive v
TRO (2)  † Stresses beyond those listed under absolute maximum ratings may c
TRP (16)  ST DIP 00+ The ADS5545 is a high performance 14-bit 170-MSPS ADC. Using an internal
TRQ (1)  N/A The online help system displays online, context-sensitive help for the u
TRR (3)  Low-power CMOS technology ORG pin to select word size for 46C version
TRS (173)  TI 08+ NOTES 1Input bias current is specified for two different conditions. The
TRT (43)  GI The TRT220BE features a 50µA low-power standby mode for compliance
TRU (136)  N/A AT&T 04+ The HDO is a CMOS output structure. Its output is toggle- controlled by
TRV (14)  Note 1: Absolute maximum ratings are DC values beyond which the device m
TRW (72)  TRW *Serial Port: 16C550 UART-compatible RS-232/422/485 x 1  and RS-232
TRX (8)  AT QFP-48 00   CAUTION: These devices are sensitive to electrostatic discharge; f
TRY (2) 
TRZ (2)  The DS1258W executes a read cycle whenever WE (Write Enable) is inactive (
T-S (11)  ST The MM74HC04 is a triple buffered inverter. It has high noise immunity
TS- (28)  07+/08+ 3. USB control   The family include USB controller which compliant
TS0 (54)  N/A SOP8S 06+ EPSEN is used in conjunction with Port 5 and Port 6 program memory opera
TS1 (199)  CP CLARE SOP8 07+ Absolute maximum ratings indicate sustained limits beyond which damage to
TS2 (302)  DIP BENEFITS High efficiency EMI filtering (-40db @ 900MHz) Low line capa
TS3 (323)  ST SOT23-5 N/A International Airport Industrial Park • Mailing Address: PO Box 1140
TS4 (219)  ST 06+ TSSOP Note A: All Characteristic data in the above graphs has been developed fr
TS5 (248)  TRISTAR 02 NOTES:1. Maximum voltage must be adjusted for power dissipation and junct
TS6 (166)  ST PLCC52 Operating voltage: +5.0V Programming voltage C VPP=12.2V0.2V C VCC=5.8V
TS7 (101)  ST PLCC52 06+ DC CHARACTERISTICS RHEOSTAT MODE  Resolution  Resistor Differ
TS8 (504)  ATMEL PLCC-44 02+ Supply voltagePin 1 Input voltagePin 2, 3, 4, 7, 9, 14, 15 Output curre
TS9 (226)  ST SOP8 00+ Vcc = 2.3V~2.7V, TA= 0C to 70C/ -40C to 85C, unless otherwise specified &
TSA (197)  PHILIPS TSSOP TSSOP To accelerate the product development cycle, Broadcom can support the de
TSB (290)  TI TQFP-80 03+ The driver controls the gate voltage of the power switch. To limit large
TSC (754)  TI 07+ As judged from expression (1), the turn-off time toff is affected by coll
TSD (127)  OTAX 4353 Low Power Dissipation I2CCBus Format (2Cwire type; SDA, SCL) Data Transf
TSE (5)  TI O7+ ON state resistance ON state resistance Tj = 150oC Vcc to Vout active
TSF (44)  TEMEX 2003   The TSF0455-04 is a high-withstanding-voltage photo-interrupter fo
TSG (48)  MOT 05-07+ © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
TSH (190)  TRACO 07+ The function of the Data Output Register can be controlled by the user v
TSI (49)  TI warrants pe rformance of its se miconductor products to the spe cifica
TSJ (3)  sanyo sanyo dc98 Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devi
TSK (26)  ST DIP20 99+ The TSK0915F is a 16-bit buffer/line driver designed for driving high cap
TSL (196)  TDK 06NOPB Voltages (typically 1% of its specified value) while the Bipolar output
TSM (665)  ST SOP-20 02+   Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (t
TSN (16)  TO-220 02+ This monolithic device contains a sawtooth oscillator, error amplifier, a
TSO (208)  VISHAY Up to eight devices (two for the MSOP package) may be connected to the
TSP (81)  TI
TSQ (1)  SANYO 04+ A CMOS pin can be used as Input or Output mode. To use these pins as outpu
TSR (85)  N/A Zener Voltage Range: 6.8V to 200V Hermetically sealed DO-13 metal package
TSS (150)  TEMIC SOP 01+ Frequency planning is straightforward for single-conversion applications
TST (55)  tfk tfk dc92 The function generator can OR its inputs, widening the OR function to a
TSU (112)  NIEC TO-263 04+ NOTE 1: Dissipation rating tables and figures are provided for maintenanc
TSV (49)  N/A Electrical & Optical Specifications Specifications (Min. and Max. va
TSW (365)  SAMTEL 08+ bidirectional interface between microprocessors and/or buses with synchro-
TSX (39)  ST 91 DIP DTACK signalThe external input data acknowledge signal. When using the ex
TSY (1)  LUCENT BGA The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K
TSZ (3)  TOSHIBA MODULE N/A The Spartan series uses a standard FPGA structure as shown in Figure 1,
T-T (1)  SWIRESAMPLE TQFP-100 00 Stability The IRU1011-33 requires the use of an output capacitor as part
TT- (10)  The Programmable Interconnect Matrix (PIM) connects the four logic blocks
TT0 (6)  SOP24 06+ Honeywells enhanced SOI RICMOS™ IV (Radiation Insen- sitive CMOS)
TT1 (217)  1850 Notes: 1. For codes not listed in the figure above, please refer to the
TT2 (185)  TO-3P *Stresses above those listed under Absolute Maximum Ratings may cause per
TT3 (53)  EUPEC MODULE N/A The Spartan™ and the Spartan-XL families are a high-vol- ume produ
TT4 (76)  EUPEC Module N/A As a result of the high precision and low-noise characteristics of the O
TT5 (105)  N/A N/A N/A
TT6 (68)  1170 These CMOS counters consist of a 4-digit counter an inter- nal output la
TT7 (17)  Notes: 1. Test conditions assume signal transition times of 3 ns or less
TT8 (44)  QFN-48P 6+ An on-chip RF oscillator is enabled if OSCEN = 'High', and its output sign
TT9 (69)  Eupec n Mask optional for built-in RC oscillator with an   external resis
TTA (4)  N/A DIP 95+ Similarly, an ideal 3.3V capacitive tripler generates 9.9V. The desired o
TTB (46)  1850 (1) The algebraic convention, in which the least positive (most negative)
TTC (41)  N/A NTC-50R DIP 2) Eon is the turn-on losses when a typical diode is used in the test cir
TTD (15)  PHIL 652 Power supply sensitivity is a measure of the effect of a power supply ch
TTE (4)  STM DIP-16 03+ The AT89S2051/S4051 is a low-voltage, high-performance CMOS 8-bit microco
TTF (2)  N/A The IRU1015 keeps a constant 1.25V between the out- put pin and the adjus
TTH (4)  Infineon 07+ Device erasure occurs by executing the erase com- mand sequence. This i
TTI (9)  TPW 0 Clothes irons and curling irons are high powered appli- ances that can
TTJ (1)  93 When the configuration process is finished and the device starts up in
TTK (6)  400 06+ 500
TTL (31)  ec2 ec2 dc87 The output capacitor is part of the regulators frequency compen- sation
TTM (20)  JAT 8脚 05+ This pin is high if the PLL lock definition is valid. PLL lock definition
TTN (2)  MOT ZIP 93 The following specification apply for V+ = +3.0 VDC to +3.6 VDC, unless
TTO (10)    PIN DESCRIPTION This pin controls the gate of an external MOSFET f
TTP (5)  仙童 TO-220 05+ NOTES: 1. S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns.
TTQ (3)  MOT ZIP 93 Notes:  5. Test conditions assume signal transition time of 3 ns or
TTR (3)  TONTEK N/A SOP18 For the most current package and ordering information, see the Package Op
TTS (39)  706 00+ The Direct Rambus RIMM module consists of 144 Mbit Direct Rambus DRAM (Di
TTT (5)  N/A ESS 04+  4.4.3 Group C inspection, Group C inspection shall be conducted in
TTV (1)  EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of e
TTW (27)  EUPEC SOP Notes: 1. All InGaN LEDs represented here are IEC825 Class 2. See Applic
TTY (3)  SAGEM 模块 04+   Operating voltage range: 4.5V to 5.5V   CMOS technology for
TTZ (1)  TFK These devices can be used as two 8-bit transceivers or one 16-bit transce
TU- (1)  *Note: Stresses above those listed under Absolute Maximum Ratings may caus
TU0 (5)  HM SIP The Status operation determines if an Erase or Program operation is in pro
TU1 (10)  solitron solitron dc77+   This 18-bit universal bus transceiver is built using advanced dual
TU2 (28)  N/A N/A N/A • FullCduplex capability • External loopback mode allows testin
TU3 (3)  21 TOSHIBA 02+ The MAX8546 operates at 300kHz. The MAX8546 is compatible with low-cost al
TU4 (5)  TOSHIBA Simultaneous Read/Write operations   Data can be continuously read
TU5 (3)  01 The 64K bytes of flash EEPROM program memory are used to store the applic
TU6 (3)  N/A DIP 05+ Caution: Stresses beyond those listed under Absolute Maximum Ratings may
TU7 (1)    The micro-controller system of commands complies with the system o
TU8 (1)  Low Reverse Current Low Stored Charge, Majority Carrier Conduction Low
TU9 (1)  After the software data protections three-byte command code is given, a b
TUA (127)  Infineon The 128 words of data must be loaded into each sector. Any word that is
TUB (5)  TI 07+ Power down protection is provided on all inputs and outputs and 0 to 7V
TUC (6)  Local is used to describe IEEE Std. 1149.1 compliant scan rings and the T
TUD (2)  Full piconet support. On board 4Mbit or 8Mbit external Flash. Very low p
TUF (36)  MINI 08+ The CAN-transceiver TLE 6250 is a monolithic integrated circuit that is a
TUG (2)  Note 17: Skew is defined as the absolute value of the difference between
TUN (11)  PHILIPS 00+ 97 The normalized values read from the right side of the curve in Figure 5
TUO (2)  VTI The BA178!!T and BA178!!FP series are 3pin fixed positive output voltage
TUP (2)  ST 02+ 102 PARAMETER Reference Voltage Fb Voltage Fb Voltage Line Regulation UVLO
TUR (13)  N/A 00+ 400 The CE pin is taken LOW to enable all Playback and Record operations. The
TUS (94)  TI 08+ Notes 1. Test voltage must be applied within dv/dt rating. 2. All devic
TUT (2)  AMIS O7+ Full Scale Range (FSR) is 10V. Guaranteed but not production tested. D
TUV (4)  PHI-COMP DIP 05+   Integral Nonlinearity (INL)2   Offset Error (Unipolar, Bipol
TUW (2)  Regulation is measured at constant junction temperature using low duty cy
TUX (1)  • DLL aligns DQ and DQS transitions with CK   transitions 
TV- (9)  • High speed CMOS logic hex non-inverting buffers • RAD-PAK&
TV/ (1) 
TV0 (35)  JAPAN 2005 − Provide software confirmation of completion   of program or
TV1 (20)  T . The control signals for the configuration memory device (CE, RESET/OE and
TV2 (14)  ST 07+ The resulting voltage is buffered and fed back to the TV201 input through
TV3 (1)  Note 5: All LM74A parts will function over the V+ supply voltage range of
TV5 (15)  div div dc60+ The HYM72V64636T8 Series are 64Mx64bits Synchronous DRAM Modules. The modu
TV6 (2)  ST N/A Frequency Mode Select. This three-level input selects the frequency range
TV7 (6)  TOSHIBA TFBGA 2004 The LCX16373 contains sixteen D-type latches with 3-STATE standard outp
TV8 (8)  ICM LCC48 05+ The reference is postpackage-trimmed to increase the output accuracy. The
TV9 (3)  DIP-40 95 Output Current 700 mA (Continuous per Output) Shoot-Through Current Prote
TVA (44)  N/A N/A N/A   Low Voltage Differential Signaling (LVDS) is becoming a very popu
TVB (42)  ST PQFP 96+ NanoStar and NanoFree Packages Supports 5-V VCC Operation
TVC (56)  TI TSSOP48 01+ This single-pole, double-throw reflective switch consumes less than 50uA
TVD (3)  SGS-THOMSON DIP 1999 VGG = the gate drive voltage, which varies from zero to VGG RG = the gat
TVE (20)  SOP20 05+ Deep Power Down Mode is a additional operating mode for Low Power SDRAM.
TVG (26)  TVG QFP 06+ Infineon Technologies Components may only be used in life-support devices
TVH (2)  N/A SMD 01+   The QS3390 provides a 16:8 multiplexer logic switch. The low ON r
TVK (2)  MULTEK 08+ Bild / Fig. 5 B2 - Zweiplus-Brckenschaltung / Two-pulse bridge circuit H
TVL (2)  TI 01+ The TVL2217-33PWR is a fully integrated integer-N synthesizer and voltag
TVM (3)    To keep the RC4700s high-performance pipeline full and operating
TVP (151)  TQFP80 08+ The TVP5145PFP is a high-performance, single-chip, host-based modem solut
TVR (29)  SOIC- 07+/08+   Typical DAC matching is 0.7 LSB across all codes. Accuracy of +0.
TVS (70)  NEC/Panasonic PQFQ-80 97 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macroce
TVT (1)  div div dc79+ This is an analog output which can be used as a reference source and/or
TVU (7)  ASI (LX)high-frequency Notes: 1. Permanent damage may occur if any of these limits are exceeded.
TVV (1)  ASI (LX)high-frequency   Simplifies Circuit Design   Reduces Board Space   Reduc
TVW (2)  NOTES 1JA is specified for worst-case conditions, i.e., JA is specified f
TVX (59)  NICHICON 2007+ Note:  4. AC characteristics (except High-Z) for all 8-ns parts are
TVZ (2)  slave devices in the I 2C protocol with all memory operations synchroni
TW- (45)  ZIOLG DIP The RESET/OE input of all PROMs is best driven by the INIT output of th
TW0 (19)  N/A N/A N/A Once the deserializer has synchronized to the serializer, the LOCK pin tr
TW1 (17)  0115+ Beneficial comments (recommendations, additions, deletions) and any perti
TW2 (31)  samtec samtec dc02 • 10-bit Analog-to-Digital Converter module (A/D)   with: &nb
TW3 (6)  100 02+ Device operations are selected by entering standard JEDEC 8-bit command c
TW4 (5)  samtec samtec dc02+ The HYB39S512400/800/160AT(L) are four bank Synchronous DRAMs organized a
TW5 (1)    The TW5104 is a low skew 2/4, 4/5/6 clock generation chip designe
TW6 (7)  SOP 95 LINE BUILD-OUT: The Line Build-Out function controls the amplitude in DS
TW8 (17)  INTEL BGA2727 99+ Intended for voltage monitoring applications, the MIC845 can be used with
TW9 (44)  TECH 03+ QFP The following specifications apply for VIN= 14V; VSHUTDOWN = Open; ILOAD
TWA (3)  98 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM &nb
TWB (2)  00+ *) The terminating impedances depend on parasitics and q-values of matchin
TWC (1)  PHILIPS 2008 The D-Pak is designed for surface mounting using vapor phase, infrared, o
TWE (1)  TWE 40 DIP/18 This document is a general product description and is subject to change wi
TWG (4)  1 AMIS Stanford Microdevices TWGA-NAA is a high performance SiGe Heterojunction
TWH (9)  The first generation of LCA devices, the XC2000 family, was introduced
TWI (24)  ST 06+ 500 Conditions IO33 Pad Library Provides Interface to 3V Environment Oscilla
TWK (1)  HOSIDEN QFP N/A All thermal impedance data is approximate for static air conditions at 1
TWL (94)  TI 04+   C High-performance 32-bit RISC Architecture   C High-density
TWM (10)  ZILOG   Figure 4 illustrates the differential or gauge configuration in t
TWN (5)  TWN 06+ 4500 The eight latches of the BCT373 devices are transparent D-type latches. W
TWP (9)  TI No license, express or implied, by estoppel or otherwise, to any intellec
TWR (19)  ESILICON BGA 0547+ In most application, the VGS (Gate-Source Turn-on voltage) of the MOSFET
TWS (10)   The Hynix HYM76V8735HGT8 Series are Dual In-line Memory Modules sui
TWT (3)  PHILIPS 2008 The MCF5275 family delivers a new level of performance and integration
TWU (1)  100 02+ VDETDetection Voltage Compliance RDETMINMinimum Valid Signature Resistanc
TWW (7)  The driver is designed for up to 60 mA of sink or source current. The dri
TX- (10)  SONY 3 The HT36A0 is an 8-bit high performance RISC-like microcontroller specifi
TX0 (21)  NS SOP-28 9930/SX Right channel serial data input. Both LDATA and RDATA are assumed to be M
TX1 (101)  Pulse A A The SAW resonator is bidirectional and may be in- stalled with either ori
TX2 (158)  NAIS Original Packing 08+   The PTH03060W non-isolated power module is small in size but big
TX3 (20)  93 The Harris CD74HC688 and CD74HCT688 are 8-bit magnitude comparators des
TX4 (39)  TEMIC DIP-6 00+ Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted
TX5 (8)  WANJIE SOP The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O incorporates a n
TX6 (6)  RMC The control amplifier compares a reference voltage to a voltage that is p
TX7 (2)  00+ N/A 0   Ultra Low VF   1st in Marketplace with a 10 VR Schottky Recti
TX8 (2)  ST DIP 91 The LS323 is an 8-bit universal shift storage register with TRI-STATE ou
TX9 (18)  MINI 08+ 专业射频微波 Select the desire reference voltage to be detected by serial data from th
TXA (11)  N/A N/A 06+ output drivers have a separate VCCIO power supply which is independent
TXB (16)  TI STK 06+/07+ Low profile (4.5mm max. height) SMD type. Unshielded. Self-leads, suitab
TXC (249)  N/A TRANSWITCH 04+ The MAX3311E/MAX3313E internal power supply has a single inverting charge
TXD (34)  NAIS RELAY 07+ The EM128L08 is an integrated memory device containing a low power 1 Mbit
TXE (1)  The processors divide/multiply function contains all the instructions of
TXF (1)  Life Support Applications These NEC products are not intended for use i
TXH (2)  QFP-44 02+ Group C sample selection. Samples for subgroups in group C
TXI (1)  N/A 96 145 Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supp
TXK (2)  Pan 363 01+ [CAUTION]  The specifications on this databook are only given for
TXL (14)  These octal transparent D-type latches feature 3-state outputs designed s
TXM (3)  MOT SMD 05+ Multistandard satellite sound IF device consisting of a mixer and a volta
TXN (29)  DSI n/a • Double data rate architecture: two data transfers   per clo
TXO (10)  00 H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelev
TXP (4)  SOP The REF inputs can be changed dynamically. When changing from one refere
TXR (4)  The DU (Dont Use) pin does not contribute to the normal operation of th
TXS (38)  nais nais dc99 The TXS2SAL212VZ/TXS2SAL212VZ9 controllers provide a complete power-manag
TXT (3)  LEVELONE VIN = 5V VIN = 3V RL = 10Ω each output RL = 10Ω each output
TXU (1)  • Gain calibration, to compensate for gain errors   (in Kv and
TXX (3)  SILICONIX 99+ 1,048,576-word 16-bit/2,097,152-word 8-bit electrically switchable c
TY- (19)  Stresses beyond those listed under absolute maximum ratings may cause per
TY0 (4)  TOSHIBA 03+ Since the S/S pin does not have an internal pull-up resistor, an external
TY1 (11)  Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 a
TY2 (39)  SOP14 06+ The FS6282 is a monolithic CMOS clock generator IC designed to minimize c
TY3 (29)    (Note 9) (Continued) The following specifications apply for VA =
TY4 (30)  MOT .   1.1 Scope. This specification covers the performance requirements
TY5 (14)  MC 07+ The sensor turns to high current consumption with the magnetic south po
TY7 (8)  ON DIP 03+   The versatile features of the two gate devices will be demonstrat
TY8 (10)  TOSHIBA BGA N/A The AC/ACT161 count in modulo-16 binary sequence. From state 15 (HHHH)
TY9 (46)  TOSHIBA 2005 of a program or erase operation can be detected and any error condition
TYA (29)  N/A N/A N/A FEATURES  • Two 10-bit Nonvolatile DACs   − INL 1
TYB (2)  Description These new devices employ advanced HEXFET® power MOSFET
TYC (5)  DIP 98
TYD (14)  TOSHIBA PLCC44 92+ Stresses beyond those listed under Absolute Maximum Ratings may cause perm
TYF (2)  sgs sgs dc91 • The reference divider divisor is calculated as follows when a 12.
TYK (1)  To transmit optical data via fiber cables, signals must be converted from
TYM (1)  These PIN/NIP diode chips are specifically designed for hybrid applicati
TYN (127)  DSI n/a The ILC7071 is an 100mA, Low Noise, Low Dropout (LDO) linear regulator,
TYP (55)  ON 0215+ Voltages (typically 1% of its specified value) while the Bipolar output
TYS (5)  ST TO-   Swap Drives A and B   Non-Burst Mode DMA Option   Det
TYT (1)  ST TO-220 04+ For applications without standby or suspend modes, lower values of R1 a
TYY (1)  † Stresses beyond those listed under absolute maximum ratings may c
TYZ (2)  2007PB † Stresses beyond those listed under absolute maximum ratings may c
TZ- (1)  VIN: Supplies the current to the collector of the output power transistor
TZ0 (51)  MURATA 07+ DIP DSP CORE FEATURES 6.25 ns Instruction Cycle Time (Internal), for up to
TZ1 (12)  QFP 01+  with a single bar completely filling the primary hole. •In or
TZ2 (9)  • Floating High Side Driver with boot-strap Power   supply alo
TZ3 (16)  PHI SOP-3.9-8P 06+ Upon power up, the chipset link can be initialized via a synchronization
TZ4 (28)  EUPEC SOP The OPA860 is a versatile monolithic component designed for wide-bandwi
TZ5 (13)  EUPEC 模块 07+特价模块 NOTES: 1. Designators in TYPE: P: power supply and ground, DI: digital in
TZ6 (11)  Each device has 2 rows for identification. The first row designates the d
TZ7 (3)    Proper and sufficient power supply bypassing is crucial to
TZ8 (7)  Data flow is controlled by the direction-control (DIR) and output-enable
TZ9 (1)    HyperPHY channels can be used as the serial backplane interface b
TZA (135)  PHILIPS 00+ TQFP These bits are for programming the PLLs internal R register. This access
TZB (159)  MURATA 4X4-25P 05+ Between t7 and t8, the converter reaches its peak current limit which i
TZC (33)  MURATA 3*4 6P PB-FREE 08+ The LXT974/975 provides three separate LED drivers for each of the four P
TZH (1)  SD is a serial bi-directional data bus which is used to transfer address
TZJ (3)  N/A (7) Standby Control Function   By setting STBYB pin to L, the NJU87
TZL (2)  the subsequent positive clock edge will return the output to the active s
TZM (470)  VISHAY   The QS3VH257 HotSwitch Quad 2:1 multiplexer/demultiplexer is a hig
TZP (3)  • Low leakage, low zener impedance and maximum power dissipation of
TZQ (5)  AE 06+/07+ • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1:
TZR (6)  The actual implementation of this technique produces a waveform that has
TZS (13)  This IC functions in a variety of CPU systems and other logic systems, to
TZT (2)  Current Output, Sourcing Current Output, Sinking Closed-Loop Output I
TZV (39)  MURATA 26580   The LX8819 is a dual channel positive-voltage linear regulator. T
TZW (1)  MURATA SOT 05+PB Notes: 1. The luminous intensity IV is measured at the peak of the spati
TZX (152)  TFK Unless noted otherwise, all measurements are made with the filter install
TZY (22)  N/A 2x2 500 Volt Motor Supply Voltage 10 Amp Output Switch Capability 100% Duty
TZZ (1)  ST BGA 98 In addition to the standard output configuration, the outputs of the is
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