Welcome to Seekchip.com    HOME
    Quick search: 0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y ZALL
  Mfg pack D/C Descrpion
L.P (2)  N/A Notes:  2. VIL (min.) = C2.0V and VIH(max) = VCC + 0.5V for pulse
L/0 (5) 
L/3 (1) 
L0. (2)  SUPPLY VOLTAGE C VCC = 3V to 3.6V for Program, Erase and   Read Op
L00 (40)  NSC Solderability: 90% coverage after 5 second dip in 235C solder following
L01 (54)  NATIONAL 2008 The MT8931C Subscriber Network Interface Circuit (SNIC) is a multifunctio
L02 (23)  PHILIPS QFP-64 00+ © 1998 MX•COM Inc.www.mxcom.com Tele: 800 638-5577 336 744-5050
L03 (19)  05+   The Intersil ISL3871 Wireless LAN   Integrated Medium Acces
L04 (22)    functional operation of the device at these or any other condition
L05 (23)  NSC   BBE High Pass Filter Output (Ach)   BBE Low Pass Filter Outp
L06 (75)  AVX 0603-4R7D 96+   Figure 4 illustrates the differential or gauge configuration in t
L07 (7)  Hynix HYMD264G726B(L)4-M/K/H/L series incorporates SPD(serial presence det
L08 (129)  N/A 0805L The L0805120JEWT is a Direct Digital Synthesizer (DDS) featuring a 14-bi
L09 (41)  PHILIPS QFP44 RSI Receive ADPCM serial data input. A serial data bit stream of 4- to
L0C (4)  NS SOP8 00+ o PCI-X version 1.0a compliant o 64-bit wide data bus o Operational m
L0D (2)  99+ SSOP The HSMP-380X and HSMP-381X series are specifically designed for low di
L0G (1)  The HT6P20A/B/D detects the logic state of the internal programmed address
L0I (1)  Parameter tests can be made using the test circuit shown. Select the de
L0K (2)  LP2985AIM5X-2.8 NATIONAL SOT23-5 † Component qualification in accordance with JEDEC and industry &n
L0P (1)  In normal operation, each received message of valid format is evaluated
L0R (2)    CNC7S101 is an AC input compatible optoisolator in which two GaAs
L0S (1)  04+ NSC 6 This document is a general product description and is subject to change w
L0T (3)  00+ NS 455 When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, rel
L0U (1)  LP2985IM5X-5.0 National MF05A • Learn C Learning involves the receiver calculating   the tra
L0Z (1)  The SN74CBT3125C is organized as four 1-bit bus switches with separate ou
L-1 (39)  N/A N/A N/A These circuits are completely compatible with most TTL families. Inputs a
L10 (185)  NIKOS TO263 02+ The device operates from a 32 kHz crystal with an on-chip PLL generating
L11 (71)  NIKO TO223-4 2002+   4.3 Screening (JANTX level only). Screening shall be in accordance
L12 (53)  SHARP SOP-4 02+ Temperature  Operating5 ~ 55 C  Non-operating-40 ~ 70 C &nbs
L13 (71)  铁帽 07+ Key features include an 8-bit memory mapped architecture, a 16-bit time
L14 (56)  MOTOROLA CAN3 The LM123 is a three-terminal positive regulator with a pre- set 5V outp
L15 (43)  SONY 00+ The USB descriptors and keyboard matrix can be customized via an optional
L16 (49)  ST Low line operation occurs when the input voltage drops to a range betwee
L17 (29)  FUJI 03+ Serial configuration control input. This inputs controls the loading of
L18 (17)  FUJ QFP four channels of the L1805. The device also provides 7 signaling pins pe
L19 (24)  TI 02+ The oscillator frequency (fosc) can be set between 20 kHz and 500 kHz by
L1A (436)  LSI 01+ PLCC-28 Standard '245-Type Pinout Output Voltage Translation Tracks VCC Supports
L1B (31)  LSI . SECTOR PROGRAMMING LOCKOUT: Each sector has a programming lockout featur
L1C (1)  LSILOGIC N/A 93+   Clock output with programmable frequency (up to 48 MHz)   Co
L1F (5)  NA 02+ Offset Correct pin. A low-to-high transition on this pin initiates an in
L1M (5)  N/A ones and six zeros switching at the input clock rate. The transmission of
L1N (1)  N/A module 2005+ VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise specified. The VIN, VTH and
L1S (4)  This is to advise Samsung customers that in accordance with certain terms
L1T (1)  ST 05+ SOP-16 As with all shunt voltage references, an external bias resistor (RBIAS)
L-2 (15)  Kingbright 07+ 105 Stresses above these ratings may cause permanent damage. Exposure to abso
L2- (4)  DL 06+/07+   The 833C/W for the SOT-563 package assumes the use of the recomme
L20 (112)  LF(TEC) TO-251 06+ Hynix HYMD264G726A(L)8M-M/K/H/L series is Low Profile registered 184-pin
L21 (20)  INTEL DIP-24 07+/08+ Most low-end keyless entry transmitters are given a fixed identification
L22 (28)  OKI PLCC 03+ APPLICATIONS Ambient Temperature Monitoring (AD7816)   Thermostat
L23 (20)  TECCOR 5000 Maximum Average Forward Rectified Current @TA = 50 (Note 1) Peak Forwar
L24 (24)  INTEL The Ultra37000 devices operate with a 5V supply and can support 5V or 3
L25 (13)  N/A
L26 (18)  N/A CONEXANT 04+ The L2600 is a general-purpose buffer amplifier that offers high dynami
L27 (42)  CONEXANT QFP1420-128 99+ Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V
L28 (25)  UTC SOP8 08+ 2. The standby control input is Not compatible with TTL or   othe
L29 (149)  UTC SOP-8 05+ en = Noise Voltage of the Transistor referred to the input. (Figure 3) &
L2A (551)  LSI BGA Most low-end keyless entry transmitters are given a fixed identification
L2B (144)  LSILOGIC TQFP-208 2001 This real-time input is available as a general purpose logic input port w
L2C (45)  LSI BGA N/A The AV9155 is a low cost frequency generator designed spe- cifically for
L2D (18)  TWIN BGA  750mW BTL Stereo Speaker Amplifier  65mW Stereo Headphone Ampl
L2E (13)  EPSON TQFP 2002 PWGD (Pin 6) - Power Good pin. This is an open drain output, which is ty
L2F (3)  HUGHES BGA 01+ Stresses beyond those listed under "absolute maximum ratings may cau
L2G (1)  SCM 06+ 20945 APPLICATION NOTES   POWER CONSIDERATIONS   Each output has an
L2H (2)  LSI 01+ BGA The ISL6227 dual PWM controller delivers high efficiency precision voltag
L2K (6)  N/A The L2K212BJ105KD-T0 is an npn silicon planar epitaxial transistor, int
L2L (1)  The rise and fall time (tr, tf) of the lamp voltage can be limited to red
L2M (2)  NS The LM140 monolithic 3-terminal positive voltage regulators employ intern
L2N (11)  CISCO 2007 Small Compact Surface Mountable Package with JCBend Leads Rectangular P
L2S (9)  MOTOROAL SOT-23 The subject of pricing for the specified devices under notice of phase-out
L2X (8)  LF(TEC) DO-214 06+ 256K x 36, 512K x 18 memory configurations Supports high performance syst
L2Y (1)  13 02+ LT Low power consumption and flexible power management allow selective shutd
L2Z (3)  EPSON SSOP 2003 The small form factor and simple interface make the DataFlash Card ideal
L-3 (16)  KINGBRIGHT 04+ VCMP=VRef-0.1V,vTXIn=0V VCMP=VRef+0.1V,vRXIn=0V VtxDetIn=VRef+0.1V VRxI
L30 (86)  N/A N/A N/A Note: All devices contains Access.bus (ACB), Clock and Re- set, MICROWIR
L31 (29)  ST 06+ 500 Notes:  1. The voltage on any input or I/O pin cannot exceed the po
L32 (40)  SOP14 06+ The HYM72V12C736B(L)S4 Series are 128Mx72bits ECC Synchronous DRAM Modules
L33 (15)  UTC SOT89 08+ The 56F802 is a member of the 56800 core-based family of processors. It c
L34 (32)  N/A PLCC 06+ ACPI-PCI Bus Power Management Interface Specification Rev 1.1 Compliant
L35 (25)  INTEL 99+ QFP2828-160 • 18V to 36V Input Voltage Range • Programmable Output Volta
L36 (7)  N/A N/A N/A ** Required for stability. Must be rated for 10 µF minimum over int
L37 (9)  MSC TO252 2.0% output accuracy (25˚C) Low dropout voltage: 250 mV @ 500mA (t
L38 (27)  ST 9814/ Voltage Control Oscillator (bit LCD= 0). This pin is used to control the
L39 (94)  ROCKWELL PLCC-84 07+ The serial audio port consists of a shift clock (SCLK pin), a left/right
L3B (1)  LSI QFP The Power-On Reset (POR) ensures that the Y outputs (Y9CY13) stay in the
L3E (19)  00+ These chips, when properly assembled, display characteristics similar to
L3H (2)  96+ NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
L3J (1)  Each product in the FSDx321 (x for H, L) family consists of an integrat
L3M (1)  NSC SOP16 Hynix HYMD232646A(L)8-M/K/H/L series incorporates SPD(serial presence dete
L3N (1)  ST QFN 06+ PSoC Designer sets up power-on initialization tables for selected PSoC
L3Q (1)  PCS 2008 pins appear in the upper center of Figure 2:. They are used to write and
L3W (2)  Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
L-4 (5)  AGERE BGA The HC534, HCT534, HC564, and HCT564 are positive edge triggered flip-f
L4- (2)  1. Renesas Technology Corp. puts the maximum effort into making semicondu
L40 (82)  LF(TEC) TO-252 06+ 1. One output at a time for a maximum duration of one second. Vout = 0.5V
L41 (29)  117 MICREL 05+ Note: Agilent Technologies encoders are not recommended for use in s
L42 (40)  AMI 00+  The Hynix HYM76V16655HGT8 Series are Dual In-line Memory Modules su
L43 (29)  NIKO-SEN SOT-23 A doubled buffered serial data interface offers high-speed, 3-wire, SPI
L44 (8)  NS Reference Inputs The voltage differential between the VL and VH inputs
L45 (7)  CS DIP Intersil products are sold by description only. Intersil Corporation reser
L46 (11)  2007 † Stresses beyond those listed under absolute maximum ratings may c
L47 (14)  500 DIP Smoke Detection Circuit C The smoke comparator compares the ionization cha
L48 (68)  NATIONAL BGA 03+ Features • Wide frequency rangeC15.0MHz to 250.0MHz • User s
L49 (448)  97+ SOP-16 The PSoC™ family consists of many Mixed Signal Array with On-Chip
L4A (159)  LSILOGIC QFP 07+/08+ Bidirectional 4-bit input/output ports. Schmitt trigger input and CMOS ou
L4B (11)  LSILOGIC 01+ PLCC84 • Development tool support   The current LonBuilder®and No
L4C (12)  LSI 2007 Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Ga
L4F (1)  HITACHI SOP-14 Xilinx reserves the right to make changes, at any time, in order to impr
L4H (1)  The FSK modulator produces a frequency modulated analog output signal usi
L4M (1)  03+ QFP • Viewing Angles Match   Traffic Management Sign   Requ
L4N (5)  LF(TEC) DO-214 06+   The following discussion refers to the schematic in figure 2 belo
L4P (4)  ANDREW SOP TEMPERATURE COMPENSATION   Figure 2 shows the typical output charac
L4X (8)  LF(TEC) DO-214 06+ The L4X3RP is an audio power amplifier capable of deliver- ing 1.5W (ty
L-5 (7)  Housed in a small 24-pin DDIP or SMT (gull-wing) package, the functional
L50 (49)  ST Reading lights (car, bus, aircraft) Portable (flashlight, bicycle) Mini
L51 (26)  Notes: 1. For conditions show as Max. or Min., use appropriate value spe
L52 (10)  UTC SOT-26 08+ Analog Ground. All input signals and the VDD supply voltage must be refe
L53 (61)  kingbright kingbright dc03 Parallel to Serial Conversion   In OC3 mode, converts a 4Cbit (Nibb
L54 (21)  INTEI 94+ PLCC-M44P V+ - Is the power connection for the top of the output bridge. These pin
L55 (35)  INTEI 94+ PLCC-M44P Liefermöglichkeiten und technische Änderun- gen vorbehalten.
L56 (16)  IOR 05+ SOT-263 The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of
L57 (5)  ST DIP DIP   The melting temperature of solder is higher than the rated temper
L58 (11)  LEGERITY QFP64 The HCT646 consist of bus-transceiver circuits with 3-state outputs, D-
L59 (58)  PTC SOP8 02/03+ Wide frequency range Ð 0.01 Hz to 300 kHz Wide supply voltage range
L5A (352)  LSI QFP144 The Atmel cell (Figure 4) is simple and small and yet can be programmed
L5B (31)  EMC2 QFP 02+ When an external clock is desired, a clock pulse of ap- proximately 3V
L5C (6)  LSI BGA 99 There are six basic serial interface timing modes that can be used with t
L5H (2)  1. Typical sensitivity data is based on a 10-3 bit error rate (BER), usin
L5N (7)  ST 04+ PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic 1
L5P (3)  The device enters the pulse-skip mode when the load current drops below t
L5T (1)  Input bus select / I2C clock input. The operation of this pin depends on
L5Y (2)  where VDEL is in Volts, and RDEL is in Ohms and tDELAY is in seconds. D
L-6 (1)  Inputs containing embedded GRS (Fairchild Video Input Processors), TRS w
L60 (104)  LF(TEC) TO-202 06+ The L6004F51 is an Erasable Programmable Logic Device (EPLD) in which CMO
L61 (23)  QFN When the CAT24FC02 begins a READ mode, it transmits 8 bits of data, rel
L62 (266)  ST 7.2mm • Compact Solid-State   Bidirectional Switch • Normal
L63 (120)  ST TQFP100 Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devi
L64 (195)    The following discussion refers to the schematic below. A FET cur
L65 (145)  STMicroelectronics DIP-16P 2005 • Branch prediction and a 128-entry branch target buffer   (B
L66 (33)  MICROCHIP TSSOP8 Note: 1. All input pulses are supplied by a generator having the followi
L67 (74)  ST 07+ • F2MC-8L CPU core   Instruction set optimized for controller
L68 (9)  ROCKWELL QFP 05+ Since G6 and G7 are input only pins any attempt by the user to configure
L69 (89)  ST SOP 0538+ The Hyundai HYM71V633201 H-Series are 32Mx64bits Synchronous DRAM Modules.
L6A (4)  QFP All rights, including rights created by patent grant or registration of a
L6H (2)  FEATURES l Low power loss, high efficiency l Low forward voltage drop l
L6N (7)  LF(TEC) DO-214 06+ ON Semiconductor andare registered trademarks of Semiconductor Components
L6P (2)  1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 14
L6T (1)  LT SOP-8 03+ All Ports Fast Switching High On-Off Output-Voltage Ratio Low Crosstalk
L6X (8)  LF(TEC) TO-92 06+ Notes:  5. Test conditions assume signal transition time of 5 ns or
L-7 (1)  8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 25
L70 (54)  OKI QFP 07+ A Read Command will interrupt a burst write operation on the same clock cy
L72 (35)  LinkUp BGA-280P 0035+   Please be aware that an important notice concerning availability,
L73 (11)  OKI PLCC 96+ Noise on the transmission media is rejected by the receiver squelch cir
L74 (11)  ST For applications that require no external memory or temporarily no exte
L75 (77)  LUCENT SOP16 00+   The RC4700 also incorporates a two-entry instruction TLB. Each en
L76 (4)  ST 100 Note 6: This parameter is guaranteed by design but is not tested. The bus
L77 (33)  Fifth Generation HEXFETs from International Rectifier utilize advanced p
L78 (717)  ST TO- © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
L79 (155)  ST 03+ Note 5 The shortest allowable SK clock period e 1 fSK (as shown under the
L7A (175)  LSI QFP100 02+ The individual iButtons that comprise the keypad can be arranged as desire
L7B (5)  7 ST 03+ *Fully integrated with compact 16-pin dip *All necessary functions includ
L7C (61)  LOGIC • LPC Interface Flash   C SST49LF080A: 1024K x8 (8 Mbit) 
L7D (1)  OKI QFP/64 VCCI is the VCC associated with the input port. VCCO is the VCC associat
L7H (2)  © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
L7P (1)  Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Sourc
L7S (3)  96+ (Before using this chip, take a look at the following description note, it
L-8 (3)  The DS2751 performs temperature, voltage, and current measurement to a res
L8- (1)  SOP 07+ This document may not, in whole or in part be copied, photocopied, reprod
L80 (73)  LSI PLCC PLCC The module contains watchdog circuitry which monitors input voltage, ope
L81 (33)  LITEON 9463 - Updated SPI electrical characteristics. - Updated Derivative Differen
L82 (12)  STMicroelectronics 2006 DESCRIPTION Using the latest high voltage technology based on a patente
L83 (19)  ST addition to the LE and OE pins the AC ACT843 has a Clear (CLR) pin and a
L84 (30)  UTC SSOP-16 08+ BP_DIS is used to enable or disable the autoswitching function between bu
L85 (49)  The MAX6806 voltage detector features an active-low, push-pull RESET outp
L86 (10)  UTC SSOP-20 08+ The L8600 drives dual synchronous N-channel MOSFETs and achieves high eff
L87 (11)  00+ HXXXXZ  High voltage level  High voltage level one set-up time
L88 (47)  SANYO 00+ 1A, 1B, 1C = SPST N.O., SPST N.C., SPDT 2A, 2B, 2C = DPST N.O., DPST N.C.
L89 (3)  PHILIPS PLCC20 06+ In the XGMII 9-bit mode, the unencoded data are latched in the DDR input
L8A (73)  LSI 98+ The Fairchild Switch FST32253 is a dual 4:1 high-speed CMOS TTL-compatib
L8B (1)  HP BGA 05+ and the reset recovery will take a maximum ot tPLQ7V. The memory will r
L8C (6)  LOGIC Note: 1.Year date code. 2. 2-digit work week. 3. Factory code shall be
L8H (2)  The MAX3873A is implemented in Maxim's second-generation SiGe process and
L8S (1)  NSC 95+ • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interf
L-9 (23)  NS DIP 04+ Hynix HYMD232646(L)8-K/H/L series incorporates SPD(serial presence detect)
L9- (2)  OLI 03+ QFP1420-100 When a valid DTMF signal burst is present, ESt or DStD will go high. The
L90 (29)  SOT-23 ON 05+ CASE: Void-free transfer molded thermosetting epoxy body meeting UL94V-0
L91 (83)  OKI 06+ This new generation of TRENCH MOSFETs from Zetex utilizes a unique struct
L92 (48)  LUCENT PLCC 00+   The LX2201 Linear Battery Charger is a multi-state (2 stage) Li-
L93 (152)  8051 core, 12MHz operating frequency with double CPU clock option, 3.3V po
L94 (32)  ST TO-220 Furthermore, this circuit block compares the input signal to a threshold,
L95 (15)  AGERE 2008  4.4.3 Group C inspection. Group C inspection shall be conducted in
L96 (48)  sgs sgs dc02 The L9602013TR checks battery status to warn of potential data loss. Each
L97 (25)  ST (5) When designing your equipment, comply with the guaranteed values, in
L98 (61)  94 25 mV (or less) For normal line resistances data may be recovered from l
L99 (45)  SOP 03+/04 • Dual Voltage Detection and Reset Assertion   Low Vcc Monitor
L9A (6)  N/A QFP 98+ The 3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
L9B (7)  SONY 96+ Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups T
L9C (1)  SONY COMPUTER QFP After each 24-hour period has elapsed, the battery is connected to an inte
L9N (2)  ST QFN 05+ In addition to the data sheet changes made above due to product enhanceme
L-A (2)  AGERE QFP 06+ IEEE 1284 defines three interface connectors: • 1284 A is a 25-pi
LA- (82)  ROHM 3. Values for two Turn-On loss conditions are shown for the convenience o
LA/ (2)  SANYO DIP 93 When VCC is between 0 and 1.2 V, the device is in the high-impedance stat
LA0 (11)  SANYO 2000 SSOP The CN8223 is based on the Bt8222 device. The only change from the Bt822
LA1 (379)  SANYO electrical stability and low thermal resistance. The module operates fro
LA2 (121)  SANYO DIP-36 04+ An output-enable (OE) input places the eight outputs in either a normal l
LA3 (141)  SANYO DIP N/A Control signals for the I/O cell registers are generated using an extra
LA4 (373)  SAN IC (SIL-13) - RoHS conform 2. Regularly and continuously improve the performance of our products, pr
LA5 (242)  SANYO SIP O.S. Output The O.S. output is an open-drain output and does not have an
LA6 (337)  4238 O4   Please be aware that an important notice concerning availability,
LA7 (1330)  SANYO QFP 1999 Absolute Maximum Ratings indicate sustained limits beyond which damage to
LA8 (137)  SANYO SSOP 1999 The MLX90247family sensors are thermopile sensors IC which detects very
LA9 (105)  SANYD SOP SOP Synchronous operation is possible only in the QAM or DPSK modes. Operatio
LAA (90)  The LTC6900 operates with a single 2.7V to 5.5V power supply and provides
LAB (16)  OMRON 04+ DIP Description The HCPL-181 contains a light emitting diode optically cou
LAC (11)  OSRAMOPTO The MAX5069A evaluation kit (EV kit) is a fully assembled and tested circ
LAD (13)  OMRON 原装 08+ ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Perfor
LAE (18)  OSRAM 1210-R 05+ Each FIFO configuration is capable of writing, reading and retaining st
LAF (7)  NSC Note 3: The maximum power dissipation must be derated at elevated tempera
LAG (64)  NOTE: EP circuits are designed to meet the DC specifications shown in the
LAH (6)  N/A Stresses above those listed under Absolute Maximum Ratings may cause perm
LAI (4)  13 • Wide supply voltage range: Vcc = 2.2 to 5.5 V • Including cl
LAJ (6)  115 linear O5 TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inpu
LAK (1)  INTEL BGA PB 05+ The output of the variable gain amplifier is compared to a threshold valu
LAL (84)  LINKCOM SMD 2005 Maximum ratings are those values beyond which device damage can occur. M
LAM (7)  LSI 99+ Sirenza Microdevices SBB-5089 is a high performance InGaP HBT MMIC amplif
LAO (1)  SANYO 20 In practice, VCC1 and the supply side of the choke on VCC2 will be tied t
LAP (15)  SANYO   The MC1741C was designed for use as a summing amplifier, integrat
LAR (5)  NSC BB Filter BW Control Dynamic Range Adjust Dynamic Range Adjust Posit
LAS (127)  四脚铁帽 08+ tors, providing positive supply for high-side gate drivers. The bootstra
LAT (38)  MINI 08+ The ADR512 is a 1.2 V precision shunt voltage reference. It is designed
LAU (4)  On the subsequent clock rise the data lines are automatically three-state
LAV (13)  04+ NSC 4500 The H11GX series are photodarlington-type optically coupled optocouplers.
LAW (5)  N/A N/A N/A Bidirectional Address/Data Bus: electrically and logically compatible to
LAX (4)  COILCRAFT N/A The analog outputs are designed to directly drive a dual 50 or 75 ohm lo
LAY (7)  LP2985IM5X-1.8 National SOT23-5 Factor port regardless of whether the host equipment is operating or
LAZ (1)  CONEXANT BGA N/A 2 QUALIFICATION PLAN 2.1 Test vehicle description 2.2 Process qualificat
L-B (7)  AGERE QFP 05+
LB- (81)  LANKom Internal level translators allow controllers operating with supplies as l
LB. (3)  SOP The ADS1208 is a 2nd-order ∆Ó (delta-sigma) modu- lator op
LB0 (10)  ROHIM 08+ The device is enabled when the EN pin is connected to a low-level input v
LB1 (934)  © Cypress Semiconductor Corporation, 2003. The information contained
LB2 (41)  TA/YO YUDEN 805   The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The I
LB3 (22)  AD SOT25 6+   The RC4700 floating-point execution units support single and doubl
LB4 (12)  AD SOT25 6+
LB5 (8)  Widebus E Family Output Ports Have Equivalent 25-Ω Series Resistor
LB6 (22)  05+ The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data a
LB7 (11)  LB SOP-8 N/A Hynix HYMD264G726(L)8M-K/H/L series is Low Profile registered 184-pin doub
LB8 (85)  SANYO 92 SSOP-24 Notes: 1. Test conditions assume signal transition times of 5 ns or less
LB9 (6)  LB SOP-8 N/A The 16/8 bit SRAM interface with local DMAs help sys- tem developers to
LBA (78)  15 CPCLARE 01+ RF Integrated Corp. believes the information provided is reliable at pres
LBB (40)  CLARE DIP 02+ Note 1: Specifications at TA +25C are guaranteed by production testing. S
LBC (28)  N/A 0805L Operating voltage: +3.3V Programming voltage CVPP=12.5V0.2V CVCC=6.0V0.
LBD (15)  ROHM 0403+ for individual units, within the specified maximum and minimum limit
LBE (5)  OSRAMOPTO Increased number of interconnect resources. All CLB inputs and outputs
LBF (2)  MICREL 06+ V+ (Pin 8): Positive Power Supply. This supply must be kept free from noi
LBG (6)  INFINEON BGA1717 02+ VBIAS (VCC, VBS) = 12V, CL = 1000 pF, and TA = 25C unless otherwise specif
LBH (14)  JAT 603 04+ Notes:  5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
LBI (2)  TI. 00+ SOP. Chip enable, when at a high level allows normal operation. When at a low
LBK (7)    Serial data at 2048 kbit/s is received at the eight ST-BUS inputs
LBL (30)  LITEON Member of the Texas Instruments Widebus™ Family Supports SSTL_3 Si
LBM (21)  N/A The device has two supply voltages. VCC is designed for 3-V to 3.6-V ope
LBN (10)  N/A N/A N/A The UC1854 uses average current-mode control to accomplish fixed- freque
LBO (3)  2008 Internally there are four DACs and associated with each are two register
LBP (4)  00+ TO263-5P Enhanced 2D Graphics Controller Supports pixel depths of 8, 16, 24 and 3
LBQ (3)  OSRAMOPTO 0603-B  • Asynchronous/Isosynchronous Modes C Standard CAN Controller
LBR (28)  LUCENT 9500 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
LBS (14)  N/A N/A N/A Resolution bit - writing a zero to this bit chooses 7-bit counter resolut
LBT (33)  TI 00+ QFP Hynix HYMD232646B(L)8-M/K/H/L series incorporates SPD(serial presence dete
LBV (6)  LT 原管 0531+ The device supports low-power standby operation. When RESET is low, the d
LBW (3)  295 05+ LT The 373 consists of eight D-type transparent latches with 3-state true
LBX (4)  2 05+ LTC   Applications • Rugged with UltraFast Performance • Be
LBY (3)  LP2982AIM5X-2.6 National SOT23-5 The published capacitance data is difficult to use for calculat- ing ris
LBZ (10)  1 0602+ LT Multiple devices can be concatenated by using the CEO output to drive t
L-C (15)  PARA 04+ The references for the four DACs are derived from one reference pin. The
LC- (31)  ROHM 0403+ CyClocksRT is used to generate P, Q, and divider values used in serial pr
LC0 (74)  TI TSSOP-14 N/A /EOP /End of Process (Input, active Low). To terminate a DMA transfer, th
LC1 (124)  SANYO DIP 06+ *1. Overcharge release voltage = Overcharge detection voltage − Ove
LC2 (163)  TI TSOP16 07+ The LC257CLC257 family is supported by a full-featured macro assembler,
LC3 (573)  95 TOSHIBA is continually working to improve the quality and reliability of
LC4 (801)  LATTICE 06 C Data input, address, byte enable and control registers C Self-timed wri
LC5 (276)  LEDTECH AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at
LC6 (468)  SANYO DIP-30 1992 The LC6543H-4378 is well suited for embedded systems and portable devices
LC7 (1739)  SAYNO SIP 06+ The SN74ALVCF162835 has series damping resistors in the device output s
LC8 (1380)  97 The product information and the selection guides facilitate selection of
LC9 (196)  99 QFP The LC9885/WD185 is manufactured with Winbond high performance CMOS WinFla
LCA (199)  † Stresses beyond those listed under absolute maximum ratings may c
LCB (84)  N/A 1206 Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7
LCC (35)  CPClare DIP-8P 1998 Direction of Rotation: When the codewheel rotates in the counter- clock
LCD (126)  TVS SOP 01+ 1 A critical component is a component used   in a life-support devi
LCE (21)  INFIEON DIP8 06+ Typical Applications • Vibration Monitoring and Recording •
LCF (8)  1 06+ LT 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
LCG (15)  NTK 04+ Hynix HYMD264726B(L)8J-J series is unbuffered 184-pin double data rate Syn
LCH (51)  TI SOP 02+ Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem
LCI (1)  ST TQFP-144 03
LCJ (7)  LP3985IM5X-2.8 National SOT23-5 Note 1: All devices are 100% production tested at TA = +25C. Specification
LCK (13)  TSSOP14 The device can be used in applications where two buses need to be addre
LCL (21)  NS QFP64 02+ The power supply must be regulated to within the primary range specified
LCM (213)  QFP LATTICE 05+PB +15 VOUT- is a regulated +15 volt output available for ex- ternal uses.
LCN (44)  N/A 0805L HY57V56820A is offering fully synchronous operation referenced to a positi
LCO (4)  SEMTECH SMD-16 00+ Figure 5 shows the output levels overlayed using a storage scope. The at
LCP (47)  ST SIP4 07+ Note: Agilent Technologies encoders are not recommended for use in safet
LCQ (7)  • UL Certified No. E209204 • 600V-30A 3-phase IGBT inverter b
LCR (19)  N/A Available in the Texas Instruments NanoStar™ and NanoFree™ Pa
LCS (98)  90 s Any combination of sectors can be erased s Ready/Busy# output (RY/BY#)
LCT (64)  SANYO DIP-64 07+/08+ Enhanced performance, new generation, high-voltage, high-speed switching
LCU (2)  SOP14 06+
LCV (9)  PHILIPS SSOP24 03+ 5. CPD is defined as the value of the internal equivalent capacitance whi
LCW (6)  microcontroller. Many common microcontrollers have hardware SPI ports a
LCX (119)  MOT TSSOP   Figure 2 illustrates a typical application circuit (output source
LCY (9) 
LCZ (7)  NSC Designed to Work With an Intelligent Host Controller : − Provides
L-D (1)  Beihong 08+ All input and output pins on LinCMOS and Advanced LinCMOS products have a
LD- (38)  95 SOP8 Uses Certified SMC9000 Drivers Which Operate with Every Major Network Op
LD/ (1)  Figure 1 presents a simplified, conceptual overview of the XC5200 archit
LD0 (31)  ROHM 00+ The receive data is determined by the data bus differential signal after
LD1 (553)  ST TO-263-3 The skew between CLKOUT and the CLKA/B outputs is not dynamically adjuste
LD2 (337)  ST 06+
LD3 (77)  ST 06+ The I/O and logic functions of the Configurable Logic Block (CLB) and t
LD4 (64)  PRX SOP NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating leve
LD5 (14)  ST TSO-223 05+ COPYRIGHT © ProTek Devices 2001 SPECIFICATIONS: ProTek reserves the
LD6 (6)   AC97 3D audio controller  Fast PCI ATA/33/66/100 IDE controlle
LD7 (37)  LEADTREND SOT163 06+ The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit buffered voltage o
LD8 (146)  The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffi
LD9 (1)  LEDTECH The standard device offers access times of 70, 90, and 120 ns, allowing h
LDA (153)  MURATA 5650 05+ The 3kΩ load is an EIa-232 requirement, but the data rate and load
LDB (134)  JAT 7m-8R0 05+ 1. Intersil Pb-free products employ special Pb-free material sets;  
LDC (199)  MURATA 1206 05+   Designed for PCN and PCS base station applications with frequencie
LDD (73)  N/A The next 64 bytes of the EPROM Status Memory (addresses 100H to 13FH) con
LDE (107)  N/A 2824   (Unless otherwise indicated, copies of the above specifications, s
LDF (2)  MURATA 05+ If there is one single characteristic that justifies the existence of CMO
LDG (8)  N/A One of the useful functions made possible by the LDG0UQD-3064Bs multiple
LDH (92)  N/A The ST16C2552 is a dual asynchronous receiver and transmitter with 16 b
LDI (1)  N/A N/A 3 channels:   Dual 512-position   Single 128-position 25 k
LDJ (1)  NSC The PSoC device incorporates flexible internal clock genera- tors, inclu
LDK (5)  N/A 0402C product and manage inventory by rapidly pro- gramming test code, then a
LDL (1)  NSC The attached spice model describes the typical electrical characteristics
LDM (3)  OLYMPUS 90+ DIP   Although the Motorola accelerometers contain internal 2kV ESD pro
LDN (2)  Note 14: PSRR is a function of system gain. Specifications apply to the c
LDO (10)  Thirteen CLB inputs and four CLB outputs provide access to the function
LDQ (15)  A common use of the F157A is the moving of data from two groups of regis
LDR (17)  SOP48 06+ ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA,
LDS (73)  TI TSSOP16 00+ These two schemes are shown in the 9310 data sheet The TC output is subj
LDT (29)  NTK 805 The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers
LDU (3)  NSC reads the data to be a receiver. The device that controls the data tran
LDV (3)  LDIC 07+/08+ Differential reference clock input. The reference clock input is used as
L-E (2)  AGERES Information subject to change. The Microchip name and logo, the Microchip
LE- (3)  DIP OO The Fairchild Switch FST16211 provides 24-bits of high- speed CMOS TTL-
LE0 (5)  ZiLOG DIP 96 This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced
LE1 (35)  LOTTE DIP42 Note: 1. Except for the rating Operating Temperature Range, stresses abov
LE2 (142)  SANYO 97/99/00+ The clock enable line (EC) is active High. The EC line is shared by bot
LE3 (37)  AD SOT25 6+   Alternate Function RXD (serial input port) TXD (serial output po
LE4 (24)  ST SOP8 99+
LE5 (83)  ST 07+ The minimum VIN must meet two conditions: VIN 2.3V and VIN (VR + 2.5%)
LE6 (9)  ST SOP-8 The maximum peak input current capability is dependent on the ambient t
LE7 (234)  LEGER 03+ PLCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value sp
LE8 (132)  QFP 0506+ (*) R-L Filter to be used according to EUTELSAT recommendation to impleme
LE9 (33)  LEGERITY PLCC 04+ The jitter tolerance of the 78P7200 exceeds the requirements of TR-NWT-00
LEA (52)  DIP/42 03+ The output of the VCOD is the full speed output frequency seen on the CLK
LEB (23)  LG † Package drawings, standard packing quantities, thermal data, symb
LEC (4)  SAMSUNG The bq2019 advanced battery-monitoring IC accurately measures the charge
LED (90)  AD 06+/07+ Under-Voltage Lockout An under-voltage lockout circuit holds the outputs
LEE (6)  PHILIPS (LX)high-frequency shifters to be cascaded on the same output lines or to a common bus. Th
LEF (1)  Offered in 256Mx8bit or 128Mx16bit, the K9F2GXXX0M is 2G bit with spare 64
LEG (46)  N/A 00+ SOP-8 Rectifiers advanced line of power MOSFET transistors. The efficient geo
LEH (2)  LG INNOTEK The BUF12800 programmable voltage reference allows fast and easy adjust
LEI (2)  DIP42 94 2.7-V to 5.8-V Input Voltage Range 1.6-MHz Fixed Switching Frequency 3 I
LEJ (7)  LEGERITY QFN 04 between X2 and ground. Stuffing of these capacitors on the PCB is optio
LEK (2)  vishay vishay dc97 The HYM72V32M656T8 Series are 32Mx64bits Synchronous DRAM Modules. The mod
LEL (36)  2520(1008) Luminance Output A 75 Ω termination resistor with short traces shou
LEM (263)  TA/YUDEN 2520 Forward-Current Transfer Ratio  IC = 1.0 Adc, VCE = 3.0 Vdc  
LEN (10)  TELSON N/A  The attached datasheets are prepared and approved by SAMSUNG Electr
LEO (6)  NEC PQFP 07+/08+ The LM1881 Video sync separator extracts timing informa- tion including
LEP (11)  NSC  The HYM72V12C756B(L)S4 Series are Dual In-line Memory Modules suita
LER (20)  TAIYO 0805-1R0M 05+ Once set, SDP will remain active unless the disable command sequence is i
LES (185)  N/A
LEV (9)  N/A 06+ NOTES (a) For a device surface mounted on 50mm x 50mm FR4 PCB with high
LEW (8)  LG INNOTEK The internal circuit is composed of 4 stages including buffer output, wh
LEX (12)  AMI PLCC Optical transmitter The optical transmitter in a fiber optic system conve
LEY (1)  LG INNOTEK 256K x 36, 512K x 18 memory configurations Supports high performance syst
L-F (7)  Features • High sensitivity (+4dB compared with ICX086AK) •
LF- (48)  02 Agilents HSMS-286x family of DC biased detector diodes have been desig
LF0 (6)  LTL † Stresses beyond those listed under absolute maximum ratings may c
LF1 (331)  NS CAN CAN Once triggered, the outputs are independent of further transitions of the
LF2 (186)  LOGIC PGA 04+ SENSE (Pin 4): This pin performs two functions. It moni- tors switch curr
LF3 (419)  STM TO220/3 05+ SUPPLY VOLTAGE, +VS to CVS OUTPUT CURRENT, continuous within SOA OUTPU
LF4 (292)  NS 01+/98 The line on the graph shows the actual temperature that might be experie
LF5 (44)  SI SOT-252 01+ ICC and ICC are dependent on output loading and cycle rate. The specifie
LF6 (23)  ST 99 SOP-16 3.9mm The electronic switches on the device operate in a make before break mo
LF7 (5)  GENESIS QFP-208 04 Reading from the device is accomplished by taking Chip En- able (CE) an
LF8 (111)  ST 06+ The LF80CDT-TR is a miniature transmitter module that generates on-off key
LF9 (40)  ST TO-252 The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 5
LFA (72)  ter File, which includes the control and status reg- isters of the on-c
LFB (289)  N/A Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Au
LFC (179)  N/A 3225 KS7333 is a product used in video camera systems, such as camcorders and
LFD (56)  N/A C Internal Memory: Single Voltage FLASH up to 256   Kbytes, RAM up
LFE (135)  BGA 07+ This INFINEON module is an industry standard 144 pin 8-byte Synchronous D
LFF (1)  The ADV7314 has separate 8-/10-/16-/20-bit input ports that accept data
LFH (9)  NATIONAL SOT23-5 03+ A high-side p-channel MOSFET and a low-side n-channel MOSFET tied with
LFI (7)  N/A 9. PRESET MEMORY BUTTONS (1, 2, 3, 4, 5, 6)   These buttons are used
LFJ (13)  MURATA 4532 05+ The HY64UD16162M is a 16Mbit 1T/1C SRAM featured by high-speed operation
LFK (26)  N/A Note 2: This IC contains a zener clamp structure between the chip VCC and
LFL (132)  N/A 0603L DATA AND CONNECTION MEMORY   All data that comes in through the RX i
LFM (3)  N/A The MOC306X-M and MOC316X-M devices consist of a GaAs infrared emitting d
LFN (2)  NSC matching resistors. In CMI mode the transmitter shapes the transmit pulse
LFP (1)  NSC True Dual-Ported memory cells which allow simultaneous reads of the same
LFQ (1)  PHI QFP-32 01 The LFQUALLFQUAL AC input module interfaces directly with AC mains to p
LFR (3)  The Fairchild Switch FST6800 provides 10-bits of high- speed CMOS TTL-c
LFS (94)  N/A The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24
LFT (35)  toko toko dc97 The GS1117 is a low dropout three terminal regulator with 800mA output
LFU (1)  The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 v
LFV (1)  Pin-for-Pin compatible with AMD® Am186ES/188ES devices All features
LFW (2)  Operating Voltage Range of 4.5 V to 5.5 V High-Current Outputs Drive Up T
LFX (114)  LATTICE QFP-144 06 • Supports All Fibre Channel   Topologies; Arbitrated Loop &
LFZ (1)  † All typical values are at VCC = 5 V, TA = 25C. ‡ The outpu
LG- (18)  N/A 0805LED DIGITAL INPUT CURRENT   Input High Current, IIH   Input Low Cu
LG0 (15)  The attached spice model describes the typical electrical characteristics
LG1 (24)  LUCENT N/A For the most current package and ordering information, see the Package Op
LG2 (14)  EPCOS 02+ When 16/68# pin is at logic 1, this input is chip select A (active low)
LG3 (32)  AD SOT25 6+ The LM105 series are positive voltage regulators similar to the LM100,
LG4 (5)  BHG QFP QFP   The ISP2200A is designed to interface directly to the PCI bus and
LG5 (38)  DIP The MAX3873 is implemented in Maxims second-generation SiGe process and c
LG6 (8)  TSSOP30 † For conditions shown as MIN or MAX, use the appropriate value spe
LG7 (3)  SANYO SMD SMD The 32-bit multiplexed bus interface unit of MX98715A provides a direct
LG8 (134)  MIT DIP-64 96+ Transfect cells at high cell density. 90-95% confluence at the time of t
LG9 (3)  LG 06+ 6(8)-bit video data (RGB) is input to the Datapath Block supports up to
LGA (45)  sie sie dc98 © 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks,
LGB (8)  sie sie dc98 Power supply: 3V /5V LCD driving voltage   VLCD V1 V2 VSS, VLCD
LGC (14)  N/A 0805LED High Drive External Buffer Output Enable. These signals provide two outp
LGD (49)  LG 06-07+ Hynix HYMD232M646A(L)8-J/M/K/H/L series is unbuffered 200-pin double data
LGE (8)  LG QFP 08+ The purpose of this 54C/74C Family Characteristics applica- tion note i
LGG (1)  • Plastic package has Underwriters Laboratory   Flammability
LGH (314)  TAYIO 0402L 04+ Voltage follower/buffer/amplifier Charge integrator Photodiode amplifie
LGJ (2)  capacitance NICHICON 08+ The third stage is a topping charge that applies current at a rate low en
LGK (30)  N/A SMK 05+ Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. /UB, /LB(Upper, Lower
LGL (3)  MINIMELF • Thousands of Applications; Program   - Signal Selection/Mult
LGM (36)  WELTREND DIP OO+ This output pin is normally at a low level, but is momentarily driven h
LGN (1)  Note 1: Specifications are production tested at TA = +25C. Limits over tem
LGO (1)  Terminator technology provides an on-chip series termination resistor (R
LGP (21)  SMK Sector Protection   A hardware method to lock a sector to prevent
LGQ (19)  capacitance NICHICON 08+ 40 Plastic DIP 40 Plastic DIP 44 PLCC 44 PLCC 44 TQFP 44 TQFP 40 P
LGR (4)  OSRAMOPTO 0805-G The information herein is given to describe certain components and shall
LGS (20)  SANYO SOP 04+ Even the most conservative heat-sink design will not save the MOSFET. T
LGT (71)  OSRAM 1210 05+ Maximum ratings are those values beyond which device damage can occur. M
LGU (10)  NICHICON 2007+PB The GND terminals of the ISL6537A provide the return path for the VTT LDO
LGV (4)  N/A N/A 2004 Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambi
LGX (3)  PRX 04+ In applications where these voltage ratings could be exceeded, e.g. by t
LGY (4)  capacitance NICHICON 08+ Hynix HYMD512646(L)8-K/H/L series incorporates SPD(serial presence detect)
LGZ (1)  sie sie dc97 NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu
LH- (14)  PF  1) Drive capability: constant-current output 50mA (Max.)  2)
LH0 (472)  CAN CAN Supports Interrupt on change, eliminates management polling Flexible bui
LH1 (466)  VishaySemicond N/A 03+ This document is a general product description and is subject to change wi
LH2 (522)  SHARP TSOP40 04+ All transmitter outputs and receiver inputs are protected to 15kV using I
LH3 (18)  TI SOP 1999  SRAM • Power dissipation   Operating : 40 mA Max &n
LH4 (47)  NS (8) Typical value for minimum intermessage gap time. Under software &nbs
LH5 (1100)  SHARP STK 0636+ Addresses and data needed for the programming and erase operations are
LH6 (78)  99+   Description Level shift-gate driver Internal regulator voltage
LH7 (80)    The first character of the part number suffix determines the devic
LH8 (16)  SHARP DIP-40 07+ The oscillator circuit is designed to be used with ei- ther a parallel r
LH9 (5)  LH 1990 DIP This device requires the 3-STATE control input G to be set low to place
LHA (11)  AD 06+/07+ Unlike devices using MOS bilateral switching elements, these bipolar circ
LHB (1)    The equations are developed to predict the time it takes the RC c
LHC (6)  NANA Functional Description The HSDL-3310 is a small form factor infrared (
LHD (2)  The four manuals listed in Table 1 are required for a complete descript
LHF (19)  SHARP TSOP 07+ NOTES: 1. Minimums are guaranteed but not production tested. 2. This pa
LHG (2)  s GENERAL DESCRIPTION   The NJM2581 is a dual supply voltage wide b
LHI (26)  PERKINELMER This is the connection to the emitter of the onCchip NPN power transistor
LHK (1)  sie sie dc96 Free−Running Borderline/Critical Mode Quasi−Resonant Operatio
LHL (49)  TAIYOYUDEN N/A 02+ Note 3: The maximum power dissipation must be derated at elevated tempera
LHM (77)  TSOP 9840+ SM5212E begin a 4-word transmission cycle upon receipt of a transmission
LHN (2)  OSRAMOPTO 1206-R required to perform active and apparent energy measurements, line-voltag
LHP (3)  A separate 6-bit control register (WCR) independently controls the wipe
LHQ (1)  OSRAMOPTO 0603- • Double data rate architecture: two data transfers   per clo
LHR (11)  The M54/74HC4017 is a high speed CMOS DE- CADE COUNTER/DIVIDER fabricat
LHS (12)  DIP Two times of receiving check Built-in oscillator needs only a 5% resisto
LHT (17)  N/A 1. Typical characteristics are at TA = 25oC. 2. These are absolute values
LHX (1)  NA NA This combination of excellent dc performance with a common-mode input vol
LHY (2)  N/A 08+ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
LI- (7)  MOT 06+ 500 The LI-1455 also supports the revolutionary capabilityofcreatingspeakerin
LI0 (22)  STEWARD 2007+PB This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configurat
LI1 (22)  LT CDIP8 CDIP8 At power-up or reset, all sectors are unlocked. To activate the lockdown
LI2 (3)  N/A 0805BEAD The bq4802Y/bq4802LY real-time clock is a low-power microprocessor peri
LI3 (39)  SHARP 1995 QFP The UVS-312A/313A/315A is 0.3 inch (7.62mm) height single digit display.
LI4 (2)  N/A 1812 H : High level L : Low level X : Immaterial : Low to high transition
LI5 (2)  TSSOP 03 04 A high-frequency phase-locked loop is used for on-chip clock synthesis,
LI7 (1)  The 256 Kbyte Flash memory array is organized into seven blocks called
LI9 (1)  SHARP The CX65105 is comprised of two amplifier stages. The matching circuits f
LIA (83)  Low distortion operation is ensured by the high gain bandwidth product
LIB (3)  The LIB9762/-B are programmed by executing the program command sequence.
LIC (12)  ST TO-251 Note 3: An internal Zener on the GATE pin clamps the charge pump voltage
LIF (9)  N/A QFP   The MAU100 series has limitation of maximum connected capacitance
LIG (2)  BB DIP DIP Average forward output current, at a specified current waveform (normally
LII (1)  RF Integrated Corp. believes the information provided is reliable at pres
LIL (2)  The digital control block takes the comparator inputs and the main clock
LIM (3)  02 WE904/905 are single-chip FM/FSK transceiver ICs operate between 100 to 10
LIN (13)  CD 06+ 15000 It is not necessary to write to all the offset registers at one time. A
LIP (1)  Handle carefully Solder under the following conditions. 5 seconds max.
LIS (38)  Make connection to B side with pink wire for Light ON Make connection
LIT (9)  LITEON LQFP128 2004 For the multi-bit delta-sigma ADC, programmable gain are provided at the
LIU (4)  N/A N/A N/A Programmable up to 60 fps Programmable up to 150 fps 10-bit, on-chip 1.
LIV (3)  PMI SOP7.2 98+
LIZ (3)  SHARP 98 1985 • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum &nb
LJ- (2)  07+/08+
LJ0 (1)  When the deserializer detects edge transitions at the LVDS input, it atte
LJ1 (7)  SAMSUNG BGA 03+ Computer used for compiling and linking target programs Computer that is
LJ2 (3)  TI TSSOP-24 N/A   The following discussion refers to the schematic below. A FET cur
LJ3 (3)  LEDTECH In addition to the savings resulting from reduced parts count and circui
LJ7 (2)  LEDTECH 0304+ HiMARK Technology, Inc. reserves the right to change the product describe
LJ8 (4)  N/A SMD 994965 Reading from the device is accomplished by taking Chip Enable 1 (CE1) LO
LJ9 (1) 
LJA (3)  SONY PQFP-80 99 All data valid at ambient temperature between 3.0V and 3.6V. The followin
LJC (1)  PMC QFP 04+ Min Typ Max Min Typ Max UnitsTest Conditions 320 320VApplied drain-to-
LJD (1)  The input load capacitors are placed on-die to reduce external component
LJE (4)  N/A PQFP-208 00 NOTES: A. CL includes probe and jig capacitance.   B. Waveform 1 i
LJF (2)  MOTOROLA The quickest path to understanding the PSoC silicon is by read- ing this
LJT (10)  PROG (Pin 4): Charge Current Programming, Charge Current Monitor and Manu
LK- (8)  MINI 08+ 16-Channel Single-Ended or 8-Channel Differential Inputs Low Supply Curr
LK0 (2)  N/A DIP 07+ 1.700 (43.18mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC
LK1 (132)  TAIYO 0603-220 05+ * Specifications will vary with foreign standards certificati
LK2 (80)  TAIYO 06+ 31219 An additional toggle bit is available on I/O2 which can be used in conju
LK3 (22)  AD SOT25 6+
LK4 (4)  ST 00+ SOP8   The safe operating area curves indicate ICCVCE limits of the tran
LK5 (8)  AD SOT25 6+ The X76F102 will respond with an acknowledge after recognition of a sta
LK6 (1)  N/A SOP 06+ Integrated 4-band Graphic Equaliser Adjustable output stage filter compen
LK9 (1)  SOP14 06+ † The bus-hold circuit can sink at least the minimum low sustaining
LKM (1)  1. Life support devices or systems are devices or systems    w
LKO (1)  Fifth Generation HEXFETs from International Rectifier utilize advanced p
LKP (6)  Panasonic Relay(DZ) 30128F+ The Advanced Interrupt Controller (AIC) controls the internal sources fro
LKS (5)  NAIS 原装 08+ The MIC5031 detects an overcurrent condition by comparing the voltage d
LKV (1)  MOT PLCC52 06+ The blanking control input on the hexadecimal displays blanks (turns
LL- (27)  LEDTECH The HR700 series parts are high efficiency, low noise, pulse-width modul
LL0 (24)  N/A 612 6. For data calls, Part 68 rules require silence on the   phone line
LL1 (403)  FRANKE LL34 05+ Maximum ratings are those values beyond which device damage can occur. M
LL2 (168)  N/A This document contains detailed information for the MPC852T about power
LL3 (11)  N/A 1206L The 5-volt device is fully accessible and data can be written and read on
LL4 (113)  VISHAY LL34 05+ DQP[A:D]. In addition, the address for the subsequent access (Read/Write
LL5 (28)  TOKO 1678 Three-phase bipolar drive (30 V, 3.5 A) Direct PWM drive Built-in low s
LL6 (13)  TOKO 585 Transmit analog inputs and the outputs for transmit gain adjustment. AIN1
LL8 (2)  N/A SMD 99 The PWM signal is the control input for the driver. The PWM signal can en
LL9 (1)  Fifth Generation HEXFETs from International Rectifier utilize advanced
LLA (22)  N/A 0201X4 The HT82K628A will respond with ACK, clears its output buffer and prepare
LLB (11)  SUMIDA   For proper operation, the current limit resistor (RCL) must be co
LLC (3)  TI SMD 06+ Both a specific 32-bit ID as well as a 128-bit random ID is programmed i
LLD (2)  The GS4882 and GS4982 feature an internal color burst filter for minimiza
LLE (13)  615 † Notice: Stresses above those listed under Maximum Rat- ings may
LLF (19)    length is 24 bits with triangular PDF dither added for dynamic ran
LLG (1)  NTK N/A The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed ba
LLI (1)  JAT 0805-30R 05+
LLK (15)  capacitance NICHICON 08+ The specifications on this data book are only given for information, wi
LLL (9)  N/A Typical active current 400 mA Typical standby current 25 mA Reliable CMO
LLM (17)  TOKO 2008+ 1 mega pixels (1152x864) format, used with 1/2 optical system Support s
LLN (11)  HALF Input/Output: this is an input in NT mode and an output in TE mode id
LLP (18)  N/A 0603L − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance
LLQ (96)  TOK 2007+ Description: DIP and mini-DIP IPMs are intelligent power modules that
LLR (31)  capacitance NICHICON 08+ -1774.50 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -177
LLS (30)  capacitance NICHICON 08+ Temperature range for Y Version: −40C to +125C. See Figure 2 and Fi
LLT (10)  The inverting input is internally connected to the reference voltage of
LLU (5)  capacitance NICHICON 08+ Notes:  2. X =Don't Care. H = Logic HIGH, L = Logic LOW. BWx = 0 si
LLV (36)  N/A 0201L Low power features include a hardwired CD ROM decoder, advanced 0.18um CM
LLX (2)  LINEAR SMD 03+ Stresses above those listed under Absolute Maximum Ratings may cause perm
LLZ (2)  N/A n Fully integrated 1 Mbps HomePNA Physical   Layer (PHY) as defined
LM- (117)  N/A   These devices employ the Schottky Barrier principle in a large are
LM0 (58)  NATIONAL 03+ A LOW signal on MR overrides the Select and CP inputs and resets the fl
LM1 (3816)  NS CAN CAN The 4538 may be triggered by either the positive or the negative edges
LM2 (6416)  NS 07+ The waveform of the maximum DC applied voltage is flat. When a ripple vol
LM3 (4912)  NS CAN N/A The Hynix HYM71V16C735AT8 Series are 16Mx72bits ECC Synchronous DRAM Modul
LM4 (3043)  NS SOT23-5 0450+ micropackage. The HCC/HCF4000B, HCC/HCF4001B, HCC/HCF 4002B and HCC/HCF4
LM5 (698)  NSC CDIP8 Reading lights (car, bus, aircraft) Portable (flashlight, bicycle) Mini
LM6 (800)  NSC 98 The Word Program operation consists of issuing the SDP Word Program comma
LM7 (1483)  UC N/A 100 When the output load exceeds the current-limit threshold or a short is pr
LM8 (511)  A LOW signal on MR overrides the Select and CP inputs and resets the fl
LM9 (315)  NS SMD  The Samsung M390S6450CT1 is a 64M bit x 72 Synchronous Dynamic RAM
LMA (34)    The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-se
LMB (161)  LRC SMD 2008   The PLL is tuned by comparing the local oscillator frequency, afte
LMC (1087)  N/A 0603L Hynix HYMD116G725B(L)8M-M/K/H/L series is low profile registered 184-pin
LMD (49)  CHINA 0403+ 4-bit CMOS I/O ports. These ports can be set for input or output bit for
LME (52)  C&D 06 (1) Lead Forming   When forming leads, the leads should be bent at
LMF (64)  N/A N/A N/A Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple
LMG (29)  Hitachi 810 There are five (5) terminals on the LINE SIDE and five (5) terminals on
LMH (440)  NS 03+ Keep safety first in your circuit designs! 1. Renesas Technology Corpora
LMI (37)  SOP8
LMJ (5)  Panasonic 9990 07+ (4) The products described in this material are intended to be used for s
LMK (132)  Integrated Transmitter, Receiver, and Jitter Attenuator for DS3, E3, an
LML (1)  Die TUHI Serie ist eine Familie von 1.5 W DC/DC Wandler. Sie bieten kost
LMM (10)  NS SOT-23-5 01+ The MSK 5115 series is fully protected against reversed input polarity,
LMN (49)  Protect Register Write (PRWRITE) The PRWRITE instruction is used to writ
LMO (3)  NS SMD Note 1: Absolute Maximum Ratings are those values beyond which the safet
LMP (122)  TI CDIP 06+ * Stresses beyond those listed above may cause permanent damage to the de
LMQ (1)  The LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interfa
LMR (14)  muRata • CPU Features   Fully static core, capable of operating at
LMS (337)  NS TO-263-3 The maximum power that can be safely dissipated by the AD8022 is limited
LMT (45)  MOTOROLA SMD 9448 In more severe ambient conditions, the package/junction temperature of
LMU (38)  LOGIC PLCC-44 05+ The VRE304 is recommended for use as a reference for 14, 16, or 18 bit D/
LMV (1037)  TI SOT323-5 06+ The algebraic convention is used in this data sheet; the most negative val
LMW (1)  NS O7+ The LNA has a 2.4dB typical noise figure and a -10dBm input third-order i
LMX (775)  NS 07+ switch either ac or dc loads. Connection B, with the polarity and pin
LMY (2)  NS 00+ SSOP Data transmission for the DPSK mode requires that data ultimately be tran
LN- (14)  NDK The C6701 includes a large bank of on-chip memory and has a powerful and
LN0 (23)  PANASONIC 00+ N-Channel Synchronous MOSFET Driver Programmable Timeout Reverse Inducto
LN1 (95)  LINET   The PT6670 is a series of high-output Integrated Switching Regulat
LN2 (44)  NSC 218211-001-DTS Rev ADQ# 1011 All technical information is believed to b
LN3 (33)  NS DIP-8 DIP-8 Description Available in either an 8-pin DIP or SO-8 package style respe
LN4 (19)  PAN DESCRIPTION The LE00 regulator series are very Low Drop regulators ava
LN5 (49)  ZILOG SOP 03+ The S1T8825B is a high performance dual frequency synthesizer with two in
LN6 (11)  LDQM and UDQM control the lower and upper bytes of the I/O buffers. In re
LN7 (5)  NS 01+ How to Read: • Controller (host) will send start bit. • Con
LN8 (24)  INTEL 91+ PLCC The current drive capability of the buffered Tx and Ty outputs exceeds
LN9 (1)  MOT DIP 9547+ Each GLB contains 32 macrocells and a fully populated, programmable AND
LNA (20)  WJ 00+ SOP8 These 9 logical devices can be individually enabled or disabled via softwa
LNB (86)  ST SMD N/A The new Smart 3 Advanced Boot Block, manufactured on Intels latest 0.4&mi
LNC (3)  1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
LND (8)  Supertex SOT-89 06+ advanced circuit design to provide ultra-low active current. This is ide
LNE (4)  LINKSYS MQFP 1998 NOTE A: The oscillator generates a sawtooth waveform on RC. During the RC
LNG (18)  ndk ndk dc00 The transmit section of the CY7C9689 HOTLink can be con- figured to acc
LNH (1)  SIEMENS 04+ Beneficial comments (recommendations, additions, deletions) and any pertin
LNI (11)  12 LARA 0009+ Write Protect, active Low/Accelerate (VHH). Wr it e Pr ot ect Funct ion:
LNK (103)  PI SOP 05 The 1 Mbyte Flash memory array is organized into nineteen blocks called
LNL (2)  ndk ndk dc00 Description Power Switch. Connects the drain of the internal high voltage
LNM (1)  Panasonic Configuration Memory The static memory cell used for the configuration m
LNP (1)  *This is a stress rating only and functional operation of the device at t
LNR (1)  The Am79Q02/021/031 Quad Subscriber Line Audio- Processing Circuit (QSL
LNS (7)  LATTRON 03+ Information in this document is subject to change without notice. You may
LNT (1)  LARA BGA 0301+ • Supports bus-powered applications by using renumer-   ation
LNV (5)  PANASONIC 01+ In no event shall ELAN Microelectronics be made responsible for any claim
LNY (5)  The A-to-B enable (CEAB) input must be low in order to enter data from A
L-O (2)  AGERE QFP 06+ EPIC™ (Enhanced-Performance Implanted CMOS) Process Operating Rang
LO. (1)  N/A The internal PFD, a high-speed rising edge triggered type, has an interna
LO/ (1) 
LO0 (1)  • Floating Cannel Designed For Bootstrap Operation To   +600V
LO1 (4)  NSC SSOP8 04+ The external magnetic field component perpendicular to the branded side
LO2 (2)  QFP The NE253 is an 800 µm dual gate GaAs FET designed to provide fle
LO3 (9)  The TPS6210x family of low-power high-efficiency buck converters is desig
LO5 (1)  osram osram dc0438 Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an
LO6 (1)  AMD BGA 00+ RF input pin. This pin requires the use of an external DC blocking capa
LO9 (14)  PHI 95 Notes : 1. In-Band EI 115.2 kb/s and FIR_SEL = 0. 2. In-Band EI 0.
LOA (24)  NSC Note: (1) This parameter is tested initially and after a design or proce
LOB (16)  IR 07+ Utility Meters HVAC Equipment Audio / Video Components Set Top Box / Te
LOC (45)  CLARE DIP8 05+ CMOS Low Power Consumption Oscillation Frequency 4MHz to 125MHz   4
LOD (2)  NATIONAL 03+ A LOW signal on the asynchronous master reset input (MR) overrides the
LOE (9)  OSRAM TOPLED 2006 The CD40109B-Series types are supplied in 16-leadceramicdual-in-linepacka
LOG (55)  N/A N/A N/A   Auto & self refresh capability (8192 Cycles/64ms)   LVTT
LOK (5)  ns 2007 The applied external reference input voltage (VREF) determines the full-
LOL (2)  Hynix HYMD132645B(L)8J-J series incorporates SPD(serial presence detect).
LOM (10)  NSC 2008
LON (1)  SEIICOEPSON 244 TQFP Directly placing semiconductor transient protection devices or MOV's on
LOO (1)  Ready/Busy (RB). Ready/Busy is an open drain output that can be used to
LOP (2)  TO-220 A novel gate-to-drain feedback capacitance network is used to model the g
LOQ (2)  OSRAMOPTO 0603-O In practice, VCC1 and the supply side of the choke on VCC2 will be tied t
LOR (2)  The maximum allowable power dissipation is a function of ambient temperatu
LOS (8)  The OPA727 and OPA728 series op amps use a state-of-the-art 12V analog
LOT (73)  LINEA The Atmel architecture was developed to provide the high- est levels of
LOU (3)  NSC Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supp
LOV (1)  SOP-20 7.2mm 9834 Input Channel A No Internal Connection Internal Reference Supply Bia
LOW (6)  N/A NSC 04+ While in transparent mode if the DS1481 detects that the ENO pin has be
LOX (1)  14 the oscillator circuit. The actual amount that changing the load capacit
LOY (4)  OSRAMOPTO The HC11 and HCT11 logic gates utilize silicon gate CMOS technology to
L-P (1)  SEAGATE QFP 05+ PCI stop clock control input. When this signal is at a logic low level (0
LP- (22)  LANKOM ELEC   The LP-164C is a 4.5 mm (type-1/4) interline transfer CCD (IT-CCD
LP0 (52)  COILCRAFT 07+ The transceiver uses a 2.5-V supply. The I/O section is 3-V compatible. W
LP1 (48)  LG.Philips Address setup time with respect to W Chip select 1 setup time Chip sel
LP2 (2322)  NS 03+ Stresses above those listed under Absolute Maximum Ratings may cause per
LP3 (1941)  NS SMD 113 CyClocksRT is used to generate P, Q, and divider values used in serial pr
LP4 (35)  SOSHIN 07+ The BA178!!T and BA178!!FP series are 3pin fixed positive output voltage
LP5 (200)  Test mode (open or VSS) Test mode (LSB) (open or VSS) Internal digital
LP6 (143)  NA 01+ DESCRIPTION The M27C801 is an 8 Mbit EPROM offered in the two ranges U
LP7 (22)  FILTRONIC SOT-89 06+ The waveform of the maximum DC applied voltage is flat. When a ripple vol
LP8 (114)  NS SOT23-5 08+ NOTES:  1. Dimension are in inches.  2. Metric equivalents are
LP9 (8)  DONG-EUN 04+ Notes: 1. See test circuit and wave forms. 2. This parameter is guarante
LPA (19)  MURATA 2004 These pins are connected to the inputs of the tone control op amps. A c
LPB (3)  BTTC SOP 246 An analog overcurrent detection circuitry is built into the ISP1521, whic
LPC (567)  This pin represents the output of the charge pump. The voltage at this pi
LPD (30)  N/A module 2005+ ♦ PCI Express Compliant ♦ Hot Swaps 12V, 3.3V, and 3.3V Auxi
LPE (17)  SOP14 Note 11: The multiplicity of parallel ground paths reduces the effective
LPF (25)  N/A Port 2, Output. Port 2 serves as the MSB for external addressing. P2.7 is
LPG (3)  < Notice > 1. When power supply of S1T8825B is disconnected, CLK,
LPH (33)  603 The microcontroller features two ports of up to sixteen general purpose I
LPI (8)  N/A Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less
LPJ (7)  Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In
LPK (5)  Hynix HYMD216726A(L)6J-J series incorporates SPD(serial presence detect).
LPL (1)  03+ SMD
LPM (18)  2008 The MC68307 (shown in Figure 1) contains a static EC000 core processor, m
LPN (3)  ABCO 06+ NOTES:   1. Maximum Ratings apply to Case 867 only. Extended exposu
LPO (19)  N/A convenient upgrade from and/or compatibility to previous 4-Mbit and 8-M
LPP (6)  Port 0, Input/Output. Port 0 is the multiplexed address/data bus. During
LPQ (33)  APW 0 4   Typical tSK(0) (Output Skew) < 250ps   ESD > 2000V pe
LPR (24)  N/A The data receiver block is a decoder for decoding the serial input data fr
LPS (122)  IR 06+ SOP16 Note 4: For single supply operation, the following conditions apply: V+ =
LPT (100)  模块 00+ These pins should be open in parallel control mode. These pins should
LPU (2)  N/A Halt function and wake-up feature reduce power consumption Up to 0.5ms
LPV (101)  TI O7+   Device types identified as current may not be a first choice for n
LPW (7)  Differential analog Inputs. With a 1.0V reference voltage the differenti
LPX (10)  Any offset and/or gain calibration procedures should not be implemented
LPY (1)  PHILIPS 91+ MTV s electrically erasable programmable read only memories (EEPROMs) offe
LPZ (5)  N/A Should the input signal fall below a minimum value, the LOWSIG pin goes a
LQ0 (57)    Please be aware that an important notice concerning availability,
LQ1 (74)  Sharp 781 Zener Voltage Range: 6.8V to 200V Hermetically sealed DO-13 metal package
LQ2 (8)  Pb−Free Packages are Available Small Compact Surface Mountable Pac
LQ3 (1)  The LQ323P07 is fabricated on Analog Devices proprietary, high performan
LQ4 (2)  murata SMD 00+ Note Differential gain and differential phase measured for four series LM
LQ5 (3)  The popular 1N5985 thru 1N6031 series of 0.5 watt Zener Voltage Regulators
LQ6 (4)  SHARP 6.1 TFT This family of CMOS analog switches offers low resistance switching per
LQ8 (4)  TQFP64 High-speed consumer electronic ports ESD protection of PC ports, includ
LQ9 (4)  SHARP 8.4 TFT
LQC (19)  taiyo taiyo dc0509 size. Expanded inductance range covering 1.0 nH~680 nH. Realization of
LQD (83)  N/A module 2005+ • Fault Protected 16-Channel 12-Bit A/D   Converter with Sampl
LQF (22)  TOSHIBA QFP100 Performance Motion Devices, Inc. (PMD) warrants performance of its produc
LQG (378)  MURATA . 09+ The output turns low with the magnetic south pole on the branded side o
LQH (1112)  N/A 1206L NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
LQL (65)  Collector-to-Emitter Voltage Continuous Collector Current Continuous
LQM (83)  N/A This device is similar in function to the LCX244 while pro- viding flow-
LQN (272)  MURATA 02+ The THS4513 incorporates a (QFN) exposed thermal pad on the underside of
LQO (1)  - - - Power dissipation at 25ºC: 2.0 watts (also see derating in Figure 1
LQP (336)  MARATA NOTES 1Temperature range from C40C to +85C. 2Operational from V DD = 2.0
LQR (1)  OSRAMOPTO Note 4 A 1 0 MX resistor is connected to the compensation pin (which is t
LQS (183)  MURATA 5650-222M 04+ The minimum bending radius is 45 mm. The mounting surface of the filters
LQV (12)  MURATA 1206-15NJ/23N 02+ The CS8920A implements Plug and Play in ac- cordance with the Intel/Mic
LQW (521)  MURATA . 09+ These octal D-type edge-triggered flip-flops feature 3-state outputs de
LQX (2)  Interface options:   Parallel interface   DSP/microcontroller-
LR- (8)  N/A SOP 07+ The target can run disk less, it only needs an ethernet connection The r
LR0 (33)  CAN8P I/O port with bit-programmable pins; Schmitt5 trigger input or push-pul
LR1 (131)  UTC SOT25 08+ FAST 8-BIT 8032 MCU C 40MHz at 5.0V, 24MHz at 3.3V C Core, 12-clocks
LR2 (53)  LSI PGA 1M Home Phoneline Network physical-layer, single- chip transceiver Suppo
LR3 (180)  SHARP TQFP144 n/a   64-position linear taper   Two nonvolatile wiper storage opt
LR4 (130)  N/A N/A N/A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
LR5 (14)  SHARP • Fully static operation and Tri-state output • TTL compatibl
LR6 (25)  Fuj 继电器 96+ NOTE 1: All voltages are with respect to Logic Gnd pin. All currents are
LR7 (20)  SUPERTEX 05+   The K6F2016V4E families are fabricated by SAMSUNGs advanced full
LR8 (15)  IRF TO-263 02+ MAX 7000A devices provide programmable speed/power optimization. Speed-c
LRA (6)    In this circuit the hot side of the line is switched and the load
LRB (23)  LRC SMD 2008 The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of ser
LRC (141)  SHARP TQFP 03+ Synchronous byte write enables. Each 9-bit b yte has its own active low by
LRD (11)  MINI 08+ The bq2019 provides 64 bytes of general-purpose flash memory, 8 bytes of
LRE (13)  n Variable power management n Packaged in 6-lead SOT-23 (ADC081S101 als
LRF (22)  LOGIC 05+ PLCC Four address spaces, the Program Memory, Register File, Data Memory, and
LRG (4)  PRX For a zero-scale digital output code, the negative input (VIN-) must be 2
LRH (2)  sie sie dc94 Fully Differential Architecture Centered Input Common-mode Range Minimum
LRI (7)  The HIP6017 provides the power control and protection for three output
LRK (1)  3: Regulation is measured at a constant junction temperature using low du
LRL (2)  N/A
LRM (33)  MINI 08+ 2.Controlling dimension: millimeters. 3.Maximum lead thickness includes l
LRO (5)  FUJITSU Texas Instruments LinCMOS process offers superior analog performa
LRP (31)  MINI 08+ This document is a general product description and is subject to change wi
LRS (120)  SHARP BGA 02+ Up to 18-A Output Current 5-V Input Bus Wide-Output Voltage Adjust (0.8
LRT (6)  OSRAMOPTO The second switching regulator operates in the same manner, but with a 17
LRU (10)  EMAC PLCC68 Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation
LRV (1)  200 Wiseview In order to specify each device for true worst case operat- ing conditio
LRX (12)  NATIONAL   TEST CONDITION 4.75V<VIN<5.25V, 5mA[IO[1.3A: TJ=258C 08C[
L-S (4)  PARA 4 Packaged in a small, 40-pin, ceramic TDIP, the functionally complete ADS
LS- (27)  LS 02+ DIP14 The input crystal oscillator of the CY22050 is an important feature becau
LS/ (1) 
LS0 (58)  MOT The LVT574 and LVTH574 consist of eight edge-triggered flip-flops with
LS1 (297)  MOT 96+ DIP Differential and Single-Ended Analog Input/Output Built-In Analog Functi
LS2 (174)  AT&T   Another alternative would be to use a ceramic substrate or an alu
LS3 (129)  AMIS QFP44 The EL4583 extracts timing from video sync in NTSC, PAL, and SECAM syst
LS4 (90)  sgs sgs dc0320 IN2 is connected to Pin 16 (VCCA). A ferrite antenna is connected between
LS5 (93)  DIP Inhibit*: This is an open-collector (open-drain) negative logic input, th
LS6 (57)  DIP/8 02+ 7.5 ATM Encapsulation and spanning-tree RFC 1483/2684 provides a simple
LS7 (104)  TI SOP During steady-state operation for a typical switching cycle, the oscilla
LS8 (27)  Applications • Digital fieldbus isolation:   DeviceNet, SDS,
LS9 (28)  N/A DIP 99+   The IDT5T2110 is a 2.5V PLL differential clock driver intended for
LSA (155)  • Any System Requiring RS-232 Communication Ports   - Battery
LSB (8)  LSS BGA N/A Operating voltage: 2.4V~3.6V Directly drives an external transistor PWM
LSC (1138)  MOTOROLA DIP The leadless chip carrier (LCC) package represents the logical next ste
LSD (88)  CHINA 0403+ Enable EN (enable) is a CMOS compatible input. EN enables or disables a
LSE (12)  01+ SOP The bq2000 is a programmable, monolithic IC for fast-charge manage- ment
LSF (3)  eukulit eukulit dc00 Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a
LSG (27)  osram osram dc01 M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on S
LSH (23)  63 LOGIC 96+ The injection-current effect control allows signals at disabled analog in
LSI (295)  An I2C Bus interface configured as a slave receiver is used for programmi
LSJ (1)  SOP 06+ • On-board single power supply (VCC): VCC = 2.7 V to 3.6 V • Or
LSK (5)  TO220-3 The ISD1000A devices drive a speaker directly through differential output
LSL (14)  SAMSUNG TQFP 2000 In case of the spindle motor to repeat acceleration anddeceleration , the
LSM (85)  Microsemi 07/08+ Notes: 1. Gate Open 2. Measurement using the gate trigger characteristic
LSN (38)  WRITE ENABLE (WEN)   When the WEN input is LOW, data may be loaded i
LSO (2)  Digital Supply Digital Ground Transmit Baud Clock Digital Input of Tr
LSP (50)  MOTOROLA TO-92 04+ In the fixed-voltage configuration, connecting a capacitor b
LSQ (2)  osram osram dc0408   Many conditions affect the thermal performance of the power modul
LSR (50)  95 Note 1) The specified condition Tj=25˚C means that the test should
LSS (12)  GENNUM MICROPAC The LCA user logic functions and interconnections are determined by the
LST (126)  2008 Provides single chip solution for Vcore, GTL+ & clock supply 200mA O
LSU (1)  thailand 04+ 10-bit ADC -1LSB INL; No Missing Codes -Programmable Throughput up to
LSV (3)  LISOTEK 04+ Measured from Pins 1 or 16 with Respect to Pin 2 Maximum Cable Loss Ran
LSW (16)  OSRAM 1210-RW 05+   This method corresponds more accurately to the method of test and
LSX (3)  00+ Analog Undervoltage input. When UV is pulled below the 1.223V threshold,
LSY (14)  osram osram dc01 gain, low frequency, low power applications, es- pecially ideal for batt
LSZ (3)  Superior Temp. Stability for Automotive or Industrial Applications 4.5
LT (1)  • ARM (32-bit) and Thumb (16-bit compressed)   instruction se
L-T (14)  AGERE BGA/10*10 06+ When High, this input holds the address counter reset and puts the DATA
LT- (52)  PLCC-44 06+ The amplifier input is optimally matched to 50 ohms by locating capacitor
LT. (3)  2008 Many of the applications described below apply to both DMS-30 (3½ d
LT/ (1)  R = , see Figure 3 R = 50 Ω (RS-422), see Figure 3 R = 27 Ω
LT0 (115)  LT STK 2006+ The conversion process and data acquisition are controlled using CS and
LT1 (14703)  LT 2008 • Ultra-miniature size with universal terminal footprint • Hi
LT2 (368)  LTNEAR 585 Half of the macrocells on the CY7C374i have I/O pins associ- ated with
LT3 (1315)  LINEAR SMD 03+ Maximum ratings are those values beyond which device damage can occur. Ma
LT4 (407)  LT 99+ The device initialization process is configurable, enabling the CY7C68310
LT5 (293)  LT CAN CAN In a multiple supply, fault tolerant, redundant power distribution syst
LT6 (1059)  LT MSOP 07+ Command Mode: The LT6004HMS8PBF enters command mode on power-up, reset, a
LT7 (70)  LT 08+  tsk(pp)#Pulse skew (device to device)69ns tsk(p) is |tPLH C tPHL|
LT8 (57)  LT SOP 06+ Note 1: All currents into the device are positive; all currents out of the
LT9 (140)  LT 9127 The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768
LTA (227)  LT MSOP8 06+ - 1ch(forward-reverse) control DC motor driver - 4ch BTL(Balanced Transfo
LTB (157)  LT Reference Output Voltage: This output biases to VCC C1.2V. Connect to VT
LTC (14225)  LINEAR MSOP-10 The device provides ultrastable +4.500V output with 0.4500 mV (.01%) init
LTD (224)  LITEON 04+ † Typical values are at VCC = 5 V, TA = 25C. ¶ This parameter
LTE (87)  2008 configuration. Program data may be either bit serial or byte parallel.
LTF (57)  LINEAR SOP 04+ NanoStar and NanoFree Packages Optimized for 1.8-V Operat
LTG (55)  2008 The CY7B993V/994V have a flexible REF and FB input scheme. These inputs
LTH (60)  LITEON 06+ The dropout voltage is defined as the input to output voltage differenti
LTI (35)  LINEAR SMD 03+   The PT4310 modules are a low-power series of isolated DC/DC conve
LTJ (23)  2008 Data is shifted out through the serial port B (SQB0 SQB3) at the rising
LTK (46)  LINEAR SOP 04+ Drain-to-Source Breakdown Voltage 100 Gate Threshold Voltage …2.0
LTL (480)  LINEAR 2008 These octal bus transceivers are designed for asynchronous communicatio
LTM (250)  TOSHIBA This data sheet has been carefully CORPORATION • 5980 NORTH SHANN
LTN (34)  ph ph dc94 DX1 is available on the TP3070 only; DX0 is available on all devices. T
LTO (25)  SHARP SOT23-5 6+ NOTES:   1. Dimension are in inches.   2. Metric equivalents a
LTQ (14)  OSRAM 0603-BG DMOS Outputs Low r DS(on) - 0.25 Ω Maximum Linear Current Control
LTR (71)  LITEON 06+ Notes: 1. The algebraic convention, where the most negative value is a m
LTS (464)  LITEON 0405+ NOTE: EP circuits are designed to meet the DC specifications shown in the
LTT (41)  2008 Internal bias generators that are adjusted by the value of the RFO set th
LTU (20)  AD SOP   It is general knowledge that different individuals have different
LTV (407)  ST DIP-4 9824+ The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable (OE) i
LTW (34)  LT 08+
LTX (31)  2008 SUPPLY VOLTAGE C VDD = 1.7V to 2.0V for program, erase and   read
LTY (24)  LINEAR SMD 04+   For convenience, a 4MHz crystal oscillator has been used rather th
LTZ (30)  N/A N/A N/A Hardware data protection measures include a low VCC detector that automat
LU0 (5)  TI TSOP14 2007+ Note: 1. The transient peak current is the maximum non-recurring peak cu
LU1 (12)  LUCENT 07+ nanoseconds at the processor pins, which translates to an approximately 3
LU2 (1)  Current Output, Sourcing Current Output, Sinking Closed-Loop Output I
LU3 (43)  07+ Note 1) The specified condition Tj = 25C means that the test should be ca
LU4 (3)  LAN-MATE 2 This new IRK series of MAGN-A-paks uses high voltage power diodes in two
LU5 (69)  SHARP SMD SMD Anwendungen • Bauteil mit hoher Strahlstärke zur   Ober
LU6 (4)  SHARP 03+ QFP The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Fl
LU7 (3)  LUCENT QFP 1998+ The HFO is a CMOS output structure. Its output is toggle- controlled by
LU8 (39)  INTEL 07+ The SDP can process a variety of VBI data services, such as closed capti
LUA (1)  For the purpose of understanding a buck converter, Figure 1 illustrates
LUB (3)  sie sie dc98 If an ADJ-bypass capacitor is use, the amplitude of the output ripple w
LUC (262)  LUCENT 07+ Four Input Frequency Range: 2.5 MHz to 45 MHz Output Frequency Range: 10
LUD (3)  The line drivers in the TSB41AB3, operating in a high-impedance current m
LUE (1)  LUCENT SSOP 1998+ The TTL compatible transmitter inputs are the BNC connectors mounted on
LUG (6)  LUCENT 2008
LUK (1)  ITT DIP40P 85+ Note 2: Operating Ratings indicate conditions for which the device is int
LUL (1)  BGA INTEL 06+ The Bold specifications apply to the full operating temperature range. N
LUM (1)  The use of Differential Rambus Signaling Level (DRSL) tech- nology permi
LUN (2)  AMI QFP 00+ The LUN333955 is intended for video applications requiring DC restoration
LUP (11)  Marvel 07+ Texas Instruments and its subsidiaries (TI) reserve the right to make cha
LUR (1)  Thispreliminarydatasheetcontainsthe specifications for the Advanced Boot
LUS (3)  LUCENT Mult Out (Pin 5) (multiplier output and current sense plus): The output
LUT (1)  HAR SOP-28 Conditions Measured from input terminals to output terminals, shortest
LUV (2)  04+  Stresses beyond those listed under Absolute Maxi- mum Ratings may
LUW (1)  Timer counter 7 : 16-bit 1  (square-wave/16-bit PWM output, cycle /
LUX (4)  N/A 01+ SSOP-28 Two Frame Buffer Memory domains utilize cost-effective, high-performance
LUY (3)  The HD74LV2G245A has two buffers with three state output in an 8 pin pack
L-V (2)  AGERE SSOP-14 06+ The numeric devices decode positive BCD logic into characters 0-9, a
LV- (14)  MACH 98+ QFP2828-160 • Input Voltage Range:   36V to 75V • 1500 VDC Isolatio
LV0 (33)  SOP14 06+ • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interf
LV1 (118)  LT TOP220 05 The capacitor connected to this pin sets the Cycle Skip period. Once a cy
LV2 (69)  SANYO SOP-36 05+ Notes a: Stresses greater than those listed under Absolute Maximum Rati
LV3 (43)  SANYO 07+ The DS1258W 3.3V 128k x 16 Nonvolatile SRAM is a 2,097,152-bit, fully stat
LV4 (51)  MIT 01+ QFP fmax = 125 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation De
LV5 (29)  95 The FM1233A permits a pushbutton (or a signal) to initiate a reset exter
LV6 (2)  ST 07+ • CMOS Process Technology • 2M x 16 bit Organization •
LV7 (8)  The C6711/C6711B/C6711C/C6711D has a complete set of development tools wh
LV8 (36)  SANYO TSSOP20 The S1T8825B is a high performance dual frequency synthesizer with two in
LVA (55)  DIP A sense FET monitors the current supplied to the load. The sense FET meas
LVB (2)  PH 08+ The base part, PI6C2308A-1, provides output clocks in sync with a referen
LVC (207)  SOP20 06+ and from X2 to ground. These capacitors are used to adjust the stray ca
LVD (47)  TI TSSOP-16 01+ These devices are ideal for use in broadcast and graphics video systems b
LVE (14)  LATTRON LO IN=-4dBm See note 1. Mixer Preamp ON Mixer Preamp OFF Mixer Pream
LVF (5)  PHI QFP44 01+ With an increasing supply voltage the IC enters the start-up state; the
LVG (2)  Outputs are low-side, open-drain DMOS transistors with output ratings of
LVH (2)  NanoStar and NanoFree Packages Supports 5-V VCC Operation
LVK (1)  Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
LVL (3)  HIT TSOP14 2007+ Preformed Leads (SOD64 Packages) Some types of automatic insertion machi
LVM (1)  Power Supply Voltage When the power supply voltage (Vcc) is less than 2
LVP (7)  INTEL D/S 05+06+07+   This series of Zener diodes is offered in the convenient, surface
LVQ (13)  ST 07+ HARDWARE PROTECTION: Hardware features protect against inadvertent writes
LVR (106)  RAYCHEM . 06+ Single Chip With Easy Interface Between UART and Serial-Port Connector of
LVS (16)  LATTRON One or several SCn/SDn downstream pairs, or channels, are selected by the
LVT (186)  TI TSSOP 01+ ColdFire version 2 variable-length RISC processor Static operation
LVU (2)  SOP14 06+ DP0_RST functions as a hub reset when a 1.5-kΩ resistor is connecte
LVW (1) 
LVX (56)  ST 97+ Please take note of the differences among products before testing and dev
L-W (3)  AGERE Guaranteed monotonic INL error: 4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/C
LW- (1)  CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active
LW0 (126)  Field Maintenance: Batteries must eventually be replaced and this creates
LW1 (11)  Table 1, column 2, IRHM8360. The values in Table 1 will be met for eith
LW2 (6)  75 MICREL 05+ Fully compliant with USB v1.1 specification and USB Device Class Definiti
LW3 (5)  730 MICREL 05+ The device can be used as a three-terminal potentio- meter or as a two-
LW4 (3)  N/A 45321812 The sampling, conversion, and activation of digital output SDO are init
LW6 (2)  NSC SOP 01+ † Vres is the minimum input voltage for a valid RESET. The symbol V
LWA (14)  OSRAS 03/04+ • Up to 60 MIPS at 60MHz core frequency • DSP and MCU funct
LWB (3)  This is a positive edge-triggered phase and frequency detector. When th
LWC (5)  N/A   Preserve correct memory cell data by maintaining power and execut
LWD (18)  NS QFP 01+ Low ON resistance: rDS(ON) = 5ΩΩ Fast transition time: tTRAN
LWE (1)  The process starts at the first low-level bit received from the demodula
LWG (1)  Maximum ratings are those values beyond which device damage can occur. M
LWH (3)  LUXPIA 2004 SMD 1) CPD isdefined as the value of the ICsinternal equivalent capacitance w
LWL (10)  OSRAM SOD-523 04+ The BUF12800 programmable voltage reference allows fast and easy adjust
LWM (4)  2000 PACKAGED THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideal
LWN (1)  The IAM-92516 is ideally suited for frequency up/down conversion for bas
LWO (1)  N/A module 2005+ 1. Permanent device damage may occur if the ratings in Absolute Maximum R
LWQ (22)  LAMBDA Module N/A For K = 1 the transfer function is H(z) = 1, that means no filtering is p
LWR (4)  2008 The SM561 uses a Cypress proprietary phase-locked loop (PLL) and Spread
LWS (1)  MOT 07+ The CS5381 is available in 24-pin TSSOP and SOIC packages for Commercial
LWT (31)  SEC QFP 07+ Single chip transmit and receive interface for E3, DS3 and STS-1 applicat
LWV (1)  A simple, single-input data interface and a buffered clock-out signal at
LWW (2)  (4) The products described in this material are intended to be used for s
LWY (9)  N/A 0805LED Before valid data exchanges between the serializer and deserializer can r
LX- (12)  NANA 00年 Power down protection is provided on all inputs and outputs and 0 to 7V
LX0 (14)  CAN CAN   The NCP1501 is a dual mode regulator that operates either as a PW
LX1 (276)  MSC MLPQ-38 6+ The FS6322 is a ROM-based CMOS clock generator IC designed to minimize co
LX2 (58)  0 06+ Reconfigurable logic can be used to implement system self-diagnostics,
LX3 (19)  MSC QFN-6 06+
LX4 (14)  AD 模块 Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V
LX5 (150)  LINFINITY TSSOP-28 04+ Description: DIP and mini-DIP IPMs are intelligent power modules that
LX6 (28)  MSC SOP-8 06+ Note 2: Typical values are given for VCC = 2.5V and TA = +25˚C. Not
LX7 (25)  LMI SOP-8 04+ The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90
LX8 (305)  JIP JIP  O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
LX9 (9)  lxt PLCC 97+ The LX901PC quad, 12-bit analog-to-digital converter (ADC) features fully
LXA (45)  LSI 2007 When the device is operating as a timing master, the internal digital PLL
LXB (2)  LSI O7+ The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SR
LXC (105)  MOT DIP The Am29LV065D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power sup
LXD (26)  SEC QFP N/A Power conversion gain from 2nd LNA/mixer to 1st IF, PRFin = -50 dBm No
LXE (10)  MSC 05+ SOP-8 With USB connected, but without DC power, charge current is set to 100mA
LXF (73)  00 Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte
LXG (13)  also allows power consumption to be reduced by leaving the separate VEE
LXH (84)  TI SSOP14 04+ The Am27C010 is a 1 Megabit, ultraviolet erasable pro- grammable read-o
LXJ (1)    Please be aware that an important notice concerning availability,
LXK (5)  N/A - 04+   Planar HD3e Process for Fast Switching Performance   Low RDS
LXL (3)  TI TSOP 04/05+ A 6:1 stereo input multiplexer is included for selecting between line l
LXM (95)  (1) Stresses above these ratings may cause permanent damage. Exposure &n
LXN (2)  Inclusion of TI products in such applications is understood to be fully a
LXP (39)  n/a The VRE3041 is recommended for use as a reference for 14, 16, or 18 bit d
LXQ (1)  The product term select multiplexer (PTMUX) allocates the five product te
LXR (1)  Location 00H is an indirect addressing register that is not physically im
LXT (716)  INTEL O7+ 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pino
LXU (1)  TECCOR 2000 TO92 (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5
LXV (72) 
LXY (51)  • Dual Marked with Device   Part Number and DSCC   Stan
LXZ (24)  SOP20 06+ Hynix HYMD116M645A(L)6-K/H/L series incorporates SPD(serial presence detec
LY- (1)  Command Buffer - The command buffer stores up to 40 characters, includin
LY0 (5)  N/A
LY1 (13)  LT 99+ 45 The TPS51020 is a multi-function dual- synchronous step-down controller
LY2 (64)  jae jae dc98   Maximum terminal current is bounded by the maximum applied voltage
LY3 (34)  DIP8 1. H = HIGH voltage level   h = HIGH voltage level one set-up time
LY4 (26)  MOT CAN Transmit Data Input. Serial data for transmission is input on this pin. In
LY5 (31)  Siemens AG n/a Because of the consideration for minimized power consumption, the max.
LY6 (22)  LYONTEK 04+ The algebraic convention is used in this data sheet; the most negative val
LY9 (2)  TI TSSOP-24   The A3213xx and A3214xx integrated circuits are ultra-sensitive, p
LYA (31)  OSRAS 03/04+ Hynix HYMD512646(L)8-K/H/L series is unbuffered 184-pin double data rate
LYB (3)  sie sie dc99 • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) • Optim
LYC (2)  LT SOP † Stresses beyond those listed under absolute maximum ratings may c
LYD (1)  LT 2007 The peak transient current capability rises sharply as the width of the
LYE (27)  OSRAS 03/04+ 500 MH z Gai n Noi se Fi gure Output IP3 Output P1dB Input Return Los
LYG (1)  OSRAM TOPLED 2006 Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connecte
LYH (1)  sie sie dc9942 sFEATURES qInput Full-SwingVIN=VSS to VDD qOutput Full-SwingVOM2.7V min
LYK (9)  sie sie dc96 Output Capacitors: The ESR specification of the output capacitor should
LYL (9)  INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the addr
LYM (20)  TRANSMITTER The transmitter accepts logic level clock (TCLK), positive d
LYN (4)  osram osram dc99 Hitachi AND Flash Write Commands Error Handling and Bad Sector Processi
LYP (1)  N/A The core is a high-performance superscalar design supporting a double-pre
LYQ (1)  Low cost integrated monolithic GaAs amplifier with step attenuator. At
LYR (3)  DESCRIPTION The ACST4 belongs to the AC power switch family built aroun
LYS (8)  osram osram dc01 The HFBR-5710L features an EEPROM for Serial ID. It contains the prod
LYT (111)  osram osram dc0524+ † Stresses beyond those listed under absolute maximum ratings may c
LYW (1)  The above equations assume that VCC equals 9V. The voltage at TON incre
LYY (9)  sie sie dc97
LYZ (1)  lnfineon SOT-23 Up to 0.5ms instruction cycle with 8MHz system clock at VDD=5V Six-leve
LZ- (13)    Many conditions affect the thermal performance of the power modul
LZ0 (2)  loaded into the device. After the last bit of the opcode is shifted in, t
LZ1 (12)  SHARP 9718+ DIP CIS AC; INT VDCREF Config Reg => XXX010XX Gain=1 (Note 1) CCD AC;
LZ2 (96)  taka taka dc96 The 78P2253 is a transceiver IC designed for 139.264Mbit/s (E4) or 155.52
LZ3 (3)  SHARP 04+05 LCC AC LINE TRANSIENT VOLTAGE RUGGEDNESS The ACST4 switch is able to sustain
LZ4 (2)  taka taka dc95 Supply Current at No-Load is 55µA Minimum Over-Current Limit: 150m
LZ5 (3) 
LZ7 (2)  98+ QFP New trench HEXFET® Power MOSFETs from International Rectifier utili
LZ8 (9)  CONEXANT Three 16-bit general-purpose timers are included and can be used to gener
LZ9 (155)  SHARP 02+ DIP-64 Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpo
LZA (12)  N/A 402 This three terminal positive adjustable voltage regulator is designed to
LZB (1)  270 LSI EDO page mode operation permits all 1,024 columns within a selected row
LZD (2)  66.66MHz clock output for AGP support. AGP-PCI should be aligned with a
LZH (1)  The Data Input/Output mask places the DQ buffers in a high impedance sta
LZN (10)  OMRON RELAY 06+ EE cell S1 controls whether the macrocell will be combi- natorial or re
LZO (3)  SHARP Note: 1) The input voltage range 19...36 V meets the requirements for No
LZP (2)  The transceiver can also replace parallel data transmission architectures
LZR (1)  0 0   Vth can be expressed as voltage between gate and source when low o
LZS (1)  N/A 4516   Front-end to baseband in one IC   Inphase and Quadrature (I/Q
LZT (1)  MOT PLCC52 05+   DESCRIPTION   These dual channel diode-transistor optocouple
LZY (3)  MINI 08+ 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 25
About Seekchip- Services - Comments - Contact us - Links - Map

© 2008 China Electronics Market,License 浙ICP备10014259号-9