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  Mfg pack D/C Descrpion
I.B (1)    READ CYCLE tRCRead Cycle Time tAAAddress Access Time tACSChip Se
I.C (1)  MAIN PRODUCT CHARACTERISTICS: Where EMI filtering in ESD sensitive equip
I.R (1)  HARRIS SOP-8 99+ SUPPLY VOLTAGE, +VS to CVS OUTPUT CURRENT, continuous within SOA OUTPU
I.T (2)  If the CPE is a telephone, one way to achieve good CAS speech immunity is
I/3 (1) 
I00 (2)  +5V reference output. This low-drift zener voltage reference is necessary
I01 (3)  TEMIC NOTE: Stresses beyond those listed under Absolute Maximum Ratings may c
I02 (3)    Standby as low as 55 mA (typ) Mailbox function for message passing
I03 (2)  ALCATEL
I04 (5)  ALCATEL/SMS PLCC-28P 00+ Notes: 1. Ratio of output level with 1kHz full scale input, to the output
I07 (1)  706 04+ INTERSIL Typical applications include sensor systems that capture analog signals,
I08 (5)  1066 ZILOG 9900 button supply when a power failure occurs. Func- tions available to the
I09 (2)   Lock Time6  Frequency Pushing (Open Loop)  Frequency Pu
I0I (2)  AMIS TQFP-64P 04+
I0M (1)  The I0MQ040TRS/H and I0MQ040TR5H are PWM control switching regulator IC s
I0X (1)  The DC/DC power module shall be installed in an end-use equipment and con
I1- (100)  HARRIS DIP   LED Display Driver: This six channel current sink driver is ideal
I10 (18)  HARRIS DIP The receiver accepts serial, CMI coded data, at 155.52Mbit/s or 139.264Mb
I11 (16)  pmi pmi dc84+ Initial issue. 1. Note 1 ( Program/Erase Characteristics) is added( page
I12 (2)    I12015 is a high performance current mode PWM controller specific
I13 (1)  SSOP20 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge
I14 (5)  ALCATEL PQFP-208 N/A The I146-4BA/I146-4BA serially interfaced display dri- vers drive up to:
I15 (11)  96 When CS is high, or UB and LB are high, the device enters standby mode: t
I16 (1)  Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic conve
I17 (1)  vikay vikay dc99 Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select.
I18 (2)  The DC/DC converter is a programmable topology synchronized Boost conve
I19 (2)  *Stresses above those listed under "Absolute Maximum Rat- ings"
I1A (1)  TSSOP 04+ The variable product-term distribution on this device removes rigid limit
I-2 (1)  The OPA703 and OPA704 series op amps are optimized for applications requ
I2- (3)  HAR CAN N/A • International standard package   JEDEC TO-247 AD • H
I20 (25)  LATTICE QFP0707-48 00+ Notes: 1. Test conditions assume signal transition times of 5 ns or less
I21 (13)  2300
I22 (11)  HAR 07+ Notes: 1. For Max. or Min. conditions, use appropriate value specified u
I23 (2)  AMD 99 Excellent ac characteristics, such as 20MHz GBW, 30V/µs slew rate
I24 (5)  AMIS PLCC-44P 03+ The device is available with an access time of 70 or 85 ns and is offer
I25 (4)  三洋 袋TO-92 Inside 5B45 & 5B46 Modules C The 5B45/46 internal circuitry compare
I26 (2)  QFN24 The video encoder is used to encode PC graphics data at maximum 1280 10
I27 (1)  The LS395 is a 4-bit shift register with TRI-STATE outputs and can opera
I28 (5)  SOP 97+   The RC32355 incorporates a flexible memory and peripheral device
I29 (3)  DALOG SOP-20 98+ The OPA688 is a wideband, unity gain stable voltage feedback op amp that
I2A (1)  LSI BGA 00+ Loop Back Select. This input is used to select the input data stream sour
I-3 (2)  The 80C186EB has integrated several common sys- tem peripherals with a C
I3- (24)  HAR DIP 07+ NOTES: 1. The falling edge of the Vin(C) signals a charge command, while
I30 (8)  NCR 06+ 500 Transmitter Output Control. TTL/CMOS control input. /TXEN is an active LO
I31 (6)  HYNIX 02+ SOP-3.9-8P This three terminal positive adjustable voltage regulator is designed to
I32 (3)  SANYO 2 Chip Enable input. Used for device selection. A Low level on both CE and
I33 (4)  QFN24 The I331/I3314/I331/I3314 are high voltage, high speed power MOSFET and
I34 (3)  QFN16 When the scaler/interlacer is bypassed, a second VGA monitor can be con
I35 (6)  • Layer 2 priority encoding (802.3p) (up to 16 priority queues) 
I36 (3)  ST TQFP 07+ For NTSC applications without the peaking capacitor the rejection at 27M
I37 (1)  04+ SOP-8 A colour co-processor is required to convert the VV6404 sensors video da
I38 (1)  BP_DIS24IActive-high logic input, disables autoswitch to bus power when s
I39 (3) 
I3D (12)  2-V to 5.5-V VCC Operation Supports Mixed-Mode Voltage Operation on All
I-4 (2)  The I-407AUL powers up the 5VDUAL plane by switching in the ATX 5V output
I40 (2) 
I41 (2)  ST SOP-8 98+ DESCRIPTION The TL7700Aseriesaremonolithicintegratedcircuit supplyvoltag
I42 (2)  INTERSIL SMD For example, S/H1 should not be commanded into the sample mode until al
I47 (1)  • External components   • External host for initialization
I48 (4)  vikay vikay dc99   The Motorola AM26LS31 is a quad differential line driver intended
I49 (4)  HARRIS SOP-8 99+ • Output Voltage Accuracy • Reset Voltage Accuracy • Re
I4D (1)  MOT PLCC44 04+ Can Be Used in Three Combinations: C OR-AND Gate C OR Gate C AND Gate
I4P (6)  HAR PLCC MPC8xx core that incorporates memory management units (MMUs) and instruct
I5- (1)  N/A DIP 07+ Connection to External FET Source Voltage. A sense resistor is connected
I50 (10)  12 HAR/INTERSIL 99/00+ Axial and Surface Mount Power Schottky rectifier suited for Switch Mode
I51 (5)  Create * Absolute maximum ratings are limiting values, to be applied individually
I52 (2)  III. Measurements The circuit was fabricated on a "Quickchip" t
I53 (1)  The IRU1117-33 is a low dropout three-terminal fixed out- put regulator w
I54 (1) 
I55 (2)  ROHM SOP8 The DAC8551 is a small, low-power, voltage output, 16-bit digital-to-ana
I58 (7)  QFN 05+ The power detector is temperature compensated on the chip, enabling a sin
I5H (1)  $W  0+] WKH GHYLFH SURYLGHV D EXUVW DFFHVV RI  QV DW  S) ZLWK D ODWH
I61 (1)  Note: 13. An in-band optical signal is a pulse/sequence where the peak w
I62 (1)  LT 2008   A fully released data sheet contains neither a classification head
I66 (1)  FET control: Optional. Output during every Read and Write access. Is prov
I67 (17)  IMP PLCC 1993 • Execution time : down to 15.6 ns (64 MHz) • FR50 series CPU
I68 (2)    An internal low frequency, low power 5.4 kHz oscillator with a 14-
I6L (1)  INTERSIL Note 12: Skew is defined as the absolute value of the difference between
I6R (1)  IOR DO-4 07+ Description The 18:88 and 88:88 0.56" Four Digit Seven Segment Disp
I6X (1)  2 INTERSIL   In most applications, the transient suppressor device is placed i
I70 (16)  icreate 06+ SSOP/16 Output Capacitors: The ESR specification of the output capacitor should
I71 (3)  2004 LLP/SMD Information furnished by Analog Devices is believed to be accurate and re
I72 (2)  618 INTERSIL 00/01+ The tuning input is typically connected to the output of the PLL loop fil
I74 (38)  When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is in
I75 (31)  DIALOG SOP-24 98+ Note 2: The algebraic convention, where the most negative value is a minim
I76 (5)  HARRIS SOP-8 True remote load sensing it is not possible to provide, because the AMS2
I80 (9)  ASE 00+ technology to Dolby certified customers. A Dolby System License certi- f
I82 (8)  INTEL PLCC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The
I83 (5)  TEMIC 01+ PLCC44   Programmable Output Voltage to 36 V   Voltage Reference Toler
I84 (5)  00+
I85 (4)  DIALOG PDIP28 96+   To define the active polarity of a signal, a suffix will be used.
I86 (2)  N/A PLCC 07+ Motorola reserves the right to make changes without further notice to any
I87 (22)  MOT DIP 02+ On-chip control functions make the ISD1000A Series very easy to use in a
I-9 (1)  These P-Channel MOSFETs from International Rectifier utilize advanced p
I90 (9)  ITEX QFP 2000 Stresses above those listed under Absolute Maximum Ratings may cause perm
I91 (3)  Note 5: The maximum power dissipation must be derated at elevated tempera
I93 (1)  RAYTHEON CDIP-8 03+ An on-chip oscillator eliminates the need for an external crystal oscilla
I94 (2)  Case C Increased Deadtime and Deadband Mode (Voltage on Pin 9 > Pin 1
I96 (4)  intel f=1kHz,THD=1% Volume=0dB VIN=1Vrms, f=1kHz Volume=0dB VIN=1Vrms, f=1kH
I9P (1)  HARRIS 08+ Chapter 6, "Instruction Set," describes the features and convent
IA/ (1) 
IA0 (10)  SOP16   Operating temperature range is C40C to +85C.   Guaranteed by
IA1 (17)  MORNSUN 08+
IA2 (12)  rohm rohm dc99 IRIS-A6131 is a hybrid IC consisting of a power MOSFET and a controller I
IA4 (4)  Integration 2006+ The WCFS0808V1E is a high-performance 3.3V CMOS Static RAM organized as 3
IA5 (4)  04+/03|+ These N-Channel enhancement mode power field effect transistors are produ
IA6 (2)  SYNCOMM The SO-8 has been modified through a customized leadframe for enhanced
IA8 (6)  ASIC Status output from this IC to indicate that the outputs have been disable
IA9 (1)  TI SMD 06+ AUX: Produces a regulated output voltage of 11.6V 5%, which is reference
IAA (8)  CP clare SMD SMD The HYM71V16M755HC(L)T6 Series are Dual In-line Memory Modules suitable fo
IAB (30)  ESLIC PLCC-44 98+   The SY10EP31V is a D flip-flop with set and reset. The device is
IAC (14)  04+ The PSD3XX family architecture (Figure 1) can efficiently interface with,
IAD (17)  AMBIT QFP N/A Figure 3 shows the proper connection of the VRE304 series voltage refer
IAE (1)  VOUT = 3.3 V, IOUT = 300 mA Current−Mode PWM Control Automatic PWM
IAI (1)  96+/99+ HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V 5V TOLERANT INPUTS POWE
IAL (3)  11 INTEYSIL 98 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
IAM (51)  VICOR device ranging from 4 to 12 wide, with an average of 7 logic product te
IAN (6)  N/A N/A N/A Instead of the usual two-diode arrangement for establishing idling curre
IAR (1)  I and Q channel LVDS Data Outputs that are not delayed in the output de
IAS (12)  N/A On power-up, the DS1804 will load the value of EEPROM memory into the wipe
IAT (1)  Fourth Generation HEXFETs from International Rectifier utilize advanced p
IAV (1)  TOKO These transceivers are designed for low-voltage (3.3V) VCC applications,
IAZ (1)  If the voltage across any cell is below the voltage speci- fied by the VS
IB0 (11)  ir ir dc97 The Direct Rambus™ RIMM™ module is a general purpose high-per
IB1 (3)  MORNSUN 08+ High Integration Minimizes System Cost Data Rates from 4 to 128.8 Kbits/S
IB2 (3)  MORNSUN 08+ VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω 1% to VCC - 2V,
IB3 (2)  MX PLCC-M32P 07+ • 10-bit, up to 8 channel Analog-to-Digital   Converter (A/D)
IB4 (3)  2004/ The Fairchild portfolio of Star*Power FETs includes a family of devices
IB5 (6)  HARRIS 06+ Thermal Resistance . . . . . . . . . . . . . . . .jajc    oC/
IB6 (1)  SUPPLY VOLTAGE, +VS to -VS SUPPLY VOLTAGE, +VB SUPPLY VOLTAGE, -VB OUTP
IB7 (3)  Edition 1998-10-08 Published by Siemens AG, Bereich Halbleiter, Marketin
IB8 (2)  READY: This signal can be used to extend the memory read and write pulses
IBA (4)  PLCC 95+ An external voltage divider from the power source sets the shutdown com
IBB (2)  CP clare SMD SMD LCD Bias Adjustment PWM Signal Input C Connect to an RC filter allowing fo
IBC (52)  1. Absolute maximum continuous ratings are those values beyond which dama
IBE (2)  Register-usage rules influence placement of input and results within the
IBF (1)  Note: Stresses greater than those listed under "Absolute Maximum Rat
IBI (15)  ST BGA N/A TELEFILTER GmbH Potsdamer Straße 18 D 14 513 TELTOW / Germany Tel
IBM (621)  N/A SSOP 07+   Unless otherwise specified, VCC=15VDC, +VHV=+VSC=+120VDC, -VSC=-15
IBP (1)  Notes: 2. The Fmin values are based on a set of 16 noise figure measureme
IBR (4)  WE\ is high in read cycle. Device is continuously selected when CE\ = VIL
IBS (2)  ami ami dc04   passive LCD panels.   • Up to 4096 colors on passive LC
IBT (1)  IDT PLCC COMMAND (Digital-to-Analog Converter Output Voltage): This pin is the out
IC- (296)  MIT SOP4 03+ Due to the high current and very high speed capability of the TURBOTRANS
IC( (1)  DMS (Data Management Software) allows systems to easily take advantage o
IC0 (43)  N/A ATMEL 04+ The output voltage of the PT6520 series of integrated switching regulato
IC1 (101)  N/A 45321812 NOTE: EP circuits are designed to meet the DC specifications shown in the
IC2 (51)   The IC200245 Series are Dual In-line Memory Modules suitable for ea
IC3 (16)  SCHLUMBERGER . These devices are organized as four 4-bit low-impedanceswitcheswithsepar
IC4 (168)  ICSI 03+ • Compliant with Intel® CK 408 rev 1.1 Mobile Clock   Synt
IC5 (37)  N/A 865 One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCO
IC6 (302)  ICSI 03+   The conditioning of the pressure signal begins with a capacitance
IC7 (10)  This feature protects against the inadvertent write. The IC702 provides f
IC8 (17)  ICSI 06+ 500 NOTE: Device will meet the specifications after thermal equilibrium has b
IC9 (6)  SMD 03+/04+ n I2C/SPI Control Interface n I2C/SPI programmable National 3D Audio n
ICA (32)  N/A 00+ QFP When output current demands exceed the maximum output current rating by 1
ICB (13)  JAT 805 05+ NOTES: (1) Refer to Logic Input Compatibility section. (2) Adjustable to
ICC (39)  SMD28 99+ The leading edge of the input signal (which consists of a 150 mV overdri
ICD (128)  ICS SMD 99+ The AC258 is a quad 2-input multiplexer with 3-state outputs. Four bits o
ICE (216)  INFINEON 07+ 30000 Loop enable. When LOOPEN is high (active), the internal loop-back path is
ICF (24)  SOP-8 Input voltage. For regulation at full load, the input to this pin must be
ICG (1)  SI QFP120 LCD and Camera data lines in mobile handsets I/O port protection for mo
ICH (10)  QFP 97+ The new Smart 3 Advanced Boot Block, manufactured on Intels latest 0.4&mi
ICI (5)  ICI 06+ 4. Setting possible during non-induction   It is possible to set a
ICK (2)  YAMAHA DIP In the 3-to-8 decoding or demultiplexing mode, the addressed output fol
ICL (2401)  INTERSIL SSOP 06+/07+ 1. Intersil Pb-free products employ special Pb-free material sets;  
ICM (700)  ICMIC SOP-16 N/A CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active
ICN (10)  TELSON SOP Important Information and Disclaimer:The information provided on this pag
ICO (32)  3M ELECTRONIC PRODUCT DIVISION 0240+
ICP (111)  ROHM 1210-1.8A 05+ Hynix HYMD132G725A(L)8-K/H/L series incorporates SPD(serial presence detec
ICQ (40)  TI DIP 96+ A LOW signal on MR overrides the Select and CP inputs and resets the fl
ICR (8)  ELMOS DIP16 07+ These solid state display devices are designed and tested for use in a
ICS (3851)  ICS SOP 99 The Samsung KMM5368003B is a 8Mx36bits Dynamic RAM high density memory mo
ICT (122)  VENES DIP-M30P 6+ The contents of this specification are subject to change without further
ICU (4)  ICU PLCC 95+
ICV (57)  INNOCHIPS 02+ All MAX® II devices provide Joint Test Action Group (JTAG) boundary-
ICW (38)  WIN PLCC-44 The F157A is a high-speed quad 2-Input multiplexer. Four bits of data fro
ICX (542)  SONY N/A   In applications where dv/dt may exceed 50,000 V/µs (such as
ICY (2)  ROHM BGA 0543+ Since the RESET output on the MAX6328/MAX6348 is open drain, these devic
ICZ (8)  MOT 2007 Isolated Frequency Input. Amplifies, Protects, Filters, and Isolates Ana
I-D (1) 
ID- (4)  MHS DIP 04+ Oscillator Synchronization and Mode Selection Input. SYNC = GND (Automa
ID0 (8)  N/A 01+ PLCC-44 Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserv
ID1 (22)  DSI n/a BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controlle
ID2 (31)    The QS3VH16245 HotSwitch is a 16-bit high bandwidth bus switch. Th
ID3 (5)  FDX
ID4 (1)  Differential clock input. The TFP513 supports both single-ended and fully
ID5 (8)  FDK The conditions at the binary-select inputs and the three enable inputs se
ID6 (5)  TOSHIBA N/A 98+ The FAN1086 and FAN1086-2.5, -2.85, -3.3 and -5 are low dropout three-te
ID7 (32)  IDT TQFP 0728vgc+ The CM2009 connects between a video graphics con- troller embedded in a
ID8 (125)  HAR   This device is an advanced direct conversion receiver for operati
ID9 (1)  The automatic mode select/change feature switches the terminator be- twe
IDA (4)  ♦ Dynamically Selectable Output Voltage from  +0.7V to VIN &
IDB (11)  INFINEON 08+ TO-263 Reset: A high on this pin for two machine cycles while the oscillator is
IDC (19)  OPTO 22 模块 08+ For optimal DSP program execution, programmers must follow the DSPs set
IDD (18)  INFINEON 08+ TO-263 Note 8: The converter is in external SCK mode of operation such that the
IDE (9)  PLCC 01+ The UC3825A and UC3825B have dual alternating outputs and the same pin co
IDF (2)  IDF SOP24 SUMMARY DESCRIPTION The M29W400B is a 4 Mbit (512Kb x8 or 256Kb x16) no
IDG (3)  INVENSEN qfn 07+ Note 3: the LTC1982E is guaranteed to meet performance specifications fr
IDH (28)  INFINEON PG-TO220-2-21 07+ Fully operational to +1200V Tolerant to negative transient voltage dV/dt
IDI (33)  DIPTR Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shi
IDJ (4)  99+ The graphs and tables provided following this note are a statistical summa
IDL (6)  INFEL SOP8 This small, power-efficient PA has a full 1700 to 2200 MHz bandwidth cove
IDM (28)  NS DIP 90 The BS62LV1024 is a high performance, very low power CMOS Static Random A
IDN (2)  QUALCOMM PLCC-68 Writing to the SRAM is accomplished when the chip select (CS) and write
IDP (25)  INFINEON 08+ TO-220 IF+, IF C (Pins 2, 3): Differential IF Signal Inputs. A differ- ential si
IDQ (1)  The receiver is designed for maxi- mum sensitivity to IrDA signals and
IDR (1)  INTERSIL SOP8 07+ Total Endurance, ICSP, In-Circuit Serial Programming, Filter- Lab, MXDEV,
IDS (29)  ZIOLG DIP Four address spaces, the Program Memory, Register File, Data Memory, and
IDT (13786)  IDT 8 SOIC 08+  CRFree-running conversion rateCS at 0 V668770 conv/s † All t
IDV (2)  The DG534A/DG538A are built on a D/CMOS process that combines n-channel
IDW (2)  INFINEON 08+ TO-247 Maximum ratings are those values beyond which device damage can occur. Ma
IDX (3)  98 CLKA/CLKB (Pins 5, 16): Card Socket. The CLKA/CLKB pins should be connect
IDY (1)  The following Functional Description describes the base architecture of
IE- (3)  WAITRONY 2007+ The device provides ultrastable +4.096V output with 0.4096 mV (.01%) init
IE0 (1)  NOTES: (1) VS = +5V. (2) VOUT = 0.25V to 2.75V. (3) NTSC signal generato
IE1 (3)  One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and   seven 64 Kbyte secto
IE2 (4)  SHARP . *Very low external component required. *High current output and high op
IE4 (1)  00+ The PIC12CE67X devices have 128 bytes of RAM, 16 bytes of EEPROM data m
IE7 (1)  The Erase Suspend/Erase Resume feature enables the user to put erase on
IEA (2)  In the interest of memory transfer operation applications, the IS93C56-3
IEB (3)  AMIS The above data is derived from fixtured measurements which include 3 paral
IEC (12)  Note 9: Shutdown current is measured in a normal room environment. Exposu
IED (4)  INFINEON SOP-18 04 The TLV350x family of push-pull output comparators feature a fast 4.5ns
IEE (16)  LEDTECH DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This i
IEF (3)  N/A As mentioned previously, the odd/even field output of the device is gener
IEG (13)  IR TO-3 ♦ Plastic package has Underwriters Laboratory Flammability  C
IEH (1)  Secured Silicon Sector: Extra 256 Byte sector   Factory locked and
IEL (12)  9508+ PDIP8 ternational Airport Industrial Park • Mailing Address: PO Box 11400,
IER (1)  En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 2: P1
IES (11)  N/A Notice: This document contains information on products in the sampling an
IEX (2)  05-07+ The input stage design of the LM6682/83 enables an input signal range t
IF- (5)  The ZA2030 is a fully integrated 30W bridged Class-D Audio Amplifier. Thi
IF0 (5)  FDK SMD 2000 The LM26 is a precision, single digital-output, low-power thermostat co
IF1 (12)  TEMIC Level Conversion Circuit The IF1-80C31-16BK has a built-in level convers
IF2 (1)  Virtually all external pins can be used as general purpose I/O port All
IF3 (3)  Basic waveforms and dc operating voltages for the test set are derived f
IF6 (2)  04+ PRODUCT IDENTIFICATION: The product identification mode identifies the d
IF7 (1)  VGS=12V, VDS=0V ID= −1mA, VGS=0V VDS= −20V, VGS=0V VDS= &#
IF9 (3)  har har dc98 Serial Data Input; receives serial data from the control device; serial
IFB (6)  NTK SOP24 04+ This manual describes the characteristics of typical optocouplers. Also i
IFC (13)  97 SSOP The OPB680 consists of an NPN phototransistor and an infrared emitting d
IFD (16)  SAMSUNG 00+ Fifth Generation HEXFETs from International Rectifier utilize advanced p
IFF (2)  S-CERA Voltage, current, and temperature measurements are made every 2C2.5 secon
IFG (1)  Two Line Output Control Because EPROMs are usually used in larger memor
IFH (2)  • Internal oscillator requires no external components • I2C-bu
IFI (3)  04+ HY57V28820B(L)T is offering fully synchronous operation referenced to a po
IFL (3)  The device operation is controlled by instructions from the host processo
IFM (3)  Figure 6 shows an SDA signal interfaced via P82B96 and the PCA82C250 to
IFN (1) 
IFR (74)  HARRIS TO-252 99+ • Power dissipation at 25ºC: 0.5 watts (also see derating &n
IFS (1)  TAMURA Notes;   Repetitive Rating: Pulse Width Limited by Maximum Junction
IFT (22)  QUALOOMM QFP 500 MHz, 500 mV −3 dB bandwidth, AV=2 400 MHz, 2VPP −3 dB b
IFU (1)    This octal buffer/driver is built using advanced dual metal CMOS
IFV (1) 
IFX (3)  INFINEON 06+ * Equipped with all stages of a mono receiver from antenna to   aud
I-G (1)  N/A TQFP-80 99 Fixed regulator output (Regulator #2) C It is recommended to bypass to GND
IG- (12)  YAMAHA DIP-42 © Cypress Semiconductor Corporation, 2002. The information contained
IG0 (10)  The TC650/TC651 acquire and convert their junction temperature (TJ) inf
IG1 (5)  ROHM 92 The LPC2131/2132/2134/2136/2138 microcontrollers are based on a 32/16 bit
IG2 (5)  96+ SOP
IG8 (1)  HAR CPGA68 9408+ Each output has independent blink timing with two blink phases. All LEDs
IGA (7)  INFINEON TO-220 08+ Pulse triggering occurs at a particular voltage level and is not directly
IGB (21)  INFINEON 07+ These parameters guaranteed but not tested. HSB is an I/O that has a we
IGC (2)  N/A N/A N/A Two different interfaces are supported on the network side. The first is
IGD (7)  Concetp驱动器 ±15A,一单元驱动器 07+原装特价原装 The EM78M612 series has sereval types of packaging. Each type is divided
IGE (2)  MURATA C.CAP 2006 These three terminal positive regulators are supplied in a hermetic metal
IGG (1)  IR 06+ TO-3P   3.3 Electrical performance characteristics and post irradiation pa
IGI (1)  ALCATEL 00+ 100 Chip Enable, Output Enable and Write Enable sig- nals control the bus o
IGO (3)  TDK 2008   This is not an extensive capacitor list. Capacitors from other ve
IGP (12)  INFINEON P-TO22 05+ s Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge
IGR (1) 
IGS (4)  98+99 PLCC International Rectifiers RAD-HardTM HEXFET® MOSFET technology provi
IGT (32)  PHILIPS 06+ SOT-23  4.4.2 Group B inspection. Group B inspection shall be conducted in
IGW (9)  INFINEON 08+ TO-247   There are two limitations on the power handling ability of a tran
I-H (1)  Because BiFET operational amplifiers are designed for use with dual power
IH- (9)  HAR L0001 DIP16 The 60HQ Schottky rectifier series has been optimized for low reverse lea
IH0 (6)  TI 8235 4. For best results, a crystal oscillator design should drive the clock i
IH1 (16)  HARRIS 99+ SOP-5.2-24P NOTE: EP circuits are designed to meet the DC specifications shown in the
IH2 (7)  HAR CAN N/A The MAX3873A is implemented in Maxim's second-generation SiGe process and
IH3 (5)  TI 8227 0s to 1s. Programming is accomplished via the internal device command r
IH4 (8)  INTERSIL DIP 2. Another solution not uncommon in synchronous applica-   tions is
IH5 (300)  INTERSIL DIP   1.1 Scope. This specification covers the performance requirements
IH6 (28)  扁平 陶封 A six byte command (bypass unlock) sequence to remove th e req uirement
IH7 (1)  QFP 2003 The programmable features of the ICS8430I-61 support two input modes an
IH8 (4)  TI 8235 • Single power supply. • Crystal/Ring oscillator option. 
IH9 (1)  HAR PDIP18 9006 In case of using R1 with different condition from the above, formula is as
IHA (13)  DL 06+/07+ The HC393 and HCT393 are 4-stage ripple-carry binary counters. All coun
IHB (5)  FEATURES High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over
IHC (8)  TI 扁平 陶封16Pin 8333 Reader Response: To improve the quality of our publications, we welcome y
IHD (23)  DL 06+/07+ Asasecond-generationHOTLinkdevice,the CYP(V)15G0401DXB extends the HOTLin
IHF (1)  The software clock is a poor timekeeper. Any change in the interrupt-reque
IHI (3)  INTERSIL DIP16 00+ On-board components include an AD780 which is a pin programmable +2.5 V
IHK (1)  Six of the 32 registers can be used as three 16-bit indirect address regi
IHL (132)  VISHAY Spartan series FPGAs are implemented with a regular, flex- ible, program
IHM (8)  n/a 03+ Notes 1. Absolute Maximum Ratings are those values beyond which the safe
IHP (2)  INFINEON TO-220 08+ During a reprogram cycle, the address locations and 64 bytes of data are
IHS (24)  vishay vishay dc99 VPN Gateways Some of the biggest challenges facing hardware designers
IHT (1)   The Hynix HYM71V16M655B(L)T6 Series are Dual In-line Memory Modules
IHV (1)  N/A N/A 2004 The AIC1722A is a 3-pin low dropout linear regulator. The superior charac
IHW (21)  INFINEON TO-247 07+ Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
II- (3)  INTERSIL DIP 04+ The blocks in the memory are asymmetrically ar- ranged, see Tables 3 an
II0 (1)  INTERPHASE 00+ N/A Operating voltage : 2.4V~5.2V Built-in 256kHz RC oscillator External 32.
II1 (2)  Pin driving the discharge-controlling FET (P-ch) Normally "L";
II2 (1)  CHIP 07+ When the voltage of the battery cell exceeds the overcharge protection vo
II3 (2)   JEDEC standard 3.3V power supply  LVTTL compatible with multip
IIC (5)  The HSDL-1100 contains a high speed, high efficiency, TS AlGaAs 870 n
IID (2)  NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected w
IIM (1)  IMP 04+ As seen in the block diagram, these modules contain a single Light Em
IIR (1)  IOR 2007 Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maxi
IIS (1)  Infineon 5520   or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function
IIT (21)  IIT 2008 The DE-SERIES SPICE Model is illustrated in Figure 1. The model is an expa
IJ0 (2)  SOP20 06+ 8-Pin SOIC switching controller with HICCUP current limiting reduces diod
IJC (1)  NOTES:  1. W is high for read cycle.  2. All timings are refer
IJR (1)  Transformerless 2W to 4W conversion Controls battery feed to line Progra
IK0 (2)  Output data enable C Used to indicate time of active video display versus
IK2 (9)  IKANOS 03/04+ Notes: 1. For Max. or Min. conditions, use appropriate value specified u
IK3 (7)  IKANOS 01+ Maximum ratings are those values beyond which device damage can occur. Ma
IK4 (1)  The 56800E core is based on a Harvard-style architecture consisting of th
IK5 (9)  N/A BGA VCCA/VCCB (Pins 4, 1): Card Socket. The VCCA/VCCB pins should be connecte
IK6 (3)  BGA N/A The varistors consist of a disc of low-â ceramic material with two
IK9 (1)  Use with 10 to 14-bit A/D converters 5 Megapixels/second minimum throughp
IKA (5)  INFINEON TO-220 08+ The DS1543 is available in two packages (28-pin DIP and 34-pin PowerCap m
IKB (8)  INFINEON TO-263 08+ The IKB01N120H2 PWM controller contains all of the features necessary t
IKC (1)  ST PLCC-44 99 In addition to the standard output configuration, the outputs of the is
IKD (3)  07+ Figure 1 shows an LM136 with a 10k potentiometer for ad- justing the re
IKE (2)  3.3V core power supply 3.3V power supply for CK48 clock outputs 3.3V pow
IKF (2)  IKANOS 2006 Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
IKK (2)  100 天龙伟业 靳先生 Fully Integrated xVCC and xVPP Switching xVPP Programmed Independent of x
IKL (1)  apem apem dc05 Notes ; Repetitive Rating : Pulse Width Limited by Maximum Junction Temp
IKM (1)  ICS SSOP 06+ Notes: (1) If (C)Remote Sense is not used, pin 12 must be connected to pi
IKN (4)  SAMSUNG 05+ SMD An additional feature of the ispLSI 3448 is the Boundary Scan capability
IKP (7)  INFINEON TO-220 08+ The S1 and S0 select pins are tri-level, meaning that they have three s
IKS (1)   The Hynix HYM71V32735AT8 Series are Dual In-line Memory Modules sui
IKW (16)  INFINEON TO-3P 08+ IT887x design for card using INTA# (Sharing IRQx), driver auto detect IRQx
IL- (203)  Vishay 05+   These circuits monitor the power supply voltage of µP based
IL/ (1)  SIEMENS DIP6 The LatticeECP/EC FPGA fabric, which was designed from the outset with lo
IL0 (19)  DRIVE This product has been designed to meet the extreme test conditions and env
IL1 (45)  VISHAY 04+ 05+ SOP8 1 Allowable ambient temperature against   % coil voltage (max. insi
IL2 (206)  VishaySemicond N/A 03+ The filters have a 4th-order Butterworth characteristic with an op
IL3 (187)  VishaySemicond N/A 03+ Note 1: Absolute Maximum Ratings are those values beyond which the life
IL4 (219)  VishaySemicond N/A 03+ pins 4 & 6 connected See application schematic See application schem
IL5 (43)  INFINEON Case: DO-214AA (SMB) Epoxy meets UL 94V-0 Flammability rating Terminals
IL6 (89)  VishaySemicond N/A 03+ The K3P7V(U)1000B-YC is a fully static mask programmable ROM fabricated u
IL7 (102)  IK 06+ Four private product terms can be ORed together with up to four shared
IL8 (5)  In the IDT Standard mode, the FF function is selected. FF indicates whet
IL9 (11)  ILYS 3000/Reel 05+ • 1.5 Mbps data rate • On-chip 3.3V regulator • Endpoi
ILA (10)  INFINEON 08+ TO-220 The 80C186XL provides a local bus controller to generate the local bus c
ILB (39)  N/A 1206 Note 1: The Absolute Maximum Ratings are those values beyond which the sa
ILC (302)  FAIRCHIL MSOP 03+ Drain-to-Source Breakdown Voltage Gate Threshold Voltage# ➃ Gate-
ILD (379)  VishaySemicond N/A 03+ An extra 64 bytes of MRAM are available to the user for Device ID. By rai
ILE (4)  NULL 06+ 500 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
ILF (5)  Differential analog Inputs. With a 1.0V reference voltage the differenti
ILG (1)  The MATCH ROM command, 55h, is used by the host to select a specific SDQ
ILH (10)  DIP6 Row Address Clock; an open drain output. The RAC pin goes LOW   1
ILI (5)  ALCATEL The DS1809 will also support a command-initiated wiper storage operation
ILK (1) 
ILL (7)  MAXIM 06+ With only 1 square inches and less than 1 Watt per channel (in ADSL mod
ILM (2)  MAXIM DIP 07+ Note 3: This IC includes overtemperature protection that is intended to
ILN (2)  TOSHIBA 06+ 1280 Regulates voltage over a broad operating current and temperature range W
ILP (2)  INFINEON 0703+0725+ TO-220 Very high speed: 55 and 70 ns Wide voltage range: 2.2V to 3.6V Pin compa
ILQ (182)  SIEMENS • N channel FET switches with no parasitic diode to VCC   C I
ILR (2)  murata 99+00 The Programmable Interconnect Array (PIA) solves inter- connect limitatio
ILS (28)  VISHAY 0805-R22K 05+ NOTES: (1) LSB means least significant bit. With VREF equal to +2.5V, on
ILT (3)  91 Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port
ILW (1)  (Continued)   • Sub-clock (32.768 KHz) operation available &
ILX (137)  SONY CCDIP FEATURES s 300 mA Output Current per Channel s Independent Over-Current
ILY (2)  † Applies only to the -1 version and only if VCC is between 4.75 V
ILZ (1)  for each channel of each device listed in this data sheet, absolute ma
IM- (14)  DL 06+/07+ The AT91X40 Series Microcontrollers integrate an ARM7TDMI with its embedd
IM0 (75)  DLE The IM02EB102K offers outstanding features with its CPU core, a 16/32-bit
IM1 (15)  IM 模块 02+ may be accessed by hardware or software operation. The hardware operatio
IM2 (26)  IMS 2007 The SA2400A is a fully integrated single IC RF transceiver designed for
IM3 (17)  MAXIM QFP 01+ Any data, prices, descriptions or specifications presented herein are sub
IM4 (332)  LATTICE 06 manage the transfer of data between the DQA/DQB pins and the sense amps
IM5 (30)  INTERSIL CDIP Designing for Microprocessor Applications As it was mentioned before, the
IM6 (69)  INTEL CDIP24 00+ Stresses above those listed under Absolute Maximum Ratings may cause per
IM7 (5)  HARRIS 99+ PLCC-M44P * This is a stress rating only and functional operation of the device at
IM8 (8)  DIP N/A   Calibration can minimize these errors.   The gain calibratio
IM9 (13)  The four address select inputs (ADD0 to ADD3) allow up to 16 MAX1169 devi
IMA (12)  ROHM 12000 07+ © 1997 MX•COM Inc.www.mxcom.com Tele: 800 638-5577 910 744-5050
IMB (132)  ITT SOT-23
IMC (199)  Vishay 2008+ SENSE (Pin 1): Maximum Overcurrent Sense Input. A sense resistor (RSENSE)
IMD (68)  ROHM SOT-163 05+ The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of ser
IME (6)  N/A N/A N/A Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Au
IMF (12)  ROHM 12000 07+ 4-wire touch screen interface LCD noise reduction feature (STOPACQ pin)
IMG (4)  SEIKO QFP 2001 Skyworks CX65105 Power Amplifier (PA) is a fully matched, 8-pin Leadless
IMH (91)  ROHM The communications interface allows the host to observe and control the c
IMI (399)  CY SMD
IMK (2)  imm imm dc05 - PMOS open drain output for control   of the charge control MOSFET
IML (7)  The devices feature single 3.0 V power supply operation for both read and
IMM (2)  IMM 98+ Note 1) The specified condition Tj=25˚C means that the test should
IMN (13)  ROHM T108 SOT153-N1 P A buffered output-enable (OE) input can be used to place the eight output
IMP (740)  IMP 14-pin, PDIP 08+   These miniature surface mount MOSFETs utilize Motorolas High Cell
IMQ (2)    The 8-bit program status word (PSW) controls ALU operations and in
IMR (8)  TEMIC QFP 02+ The output stages consist of an low RDS ON Power-MOS H-bridge. In H-bridge
IMS (375)  INMOS DIP/20 NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable
IMT (70)  ROHM 2008   The serial interface centers on a fourteen bit shift register. The
IMU (4)  ROHM 05++ SOT-163   Parameter Carrier Frequency Operating Voltage (VDD_MEM) Operati
IMV (4)  QFP This IC functions in a variety of CPU systems and other logic systems, to
IMW (2)  ROHM 2008 The MAX 3000A architecture includes four dedicated inputs that can be us
IMX (57)  ROHM SOT-163 AVCC Propagation Delay and Rise Time With 1µF Load, 3.3V Switch AVC
IMZ (25)  ROHM SOT 06+   Small Size   Industry Standard Footprint   Compatible w
IN- (19)  NND SOP28 03+/04+ NOTES: 1Stresses above those listed under Absolute Maximum Ratings may c
IN0 (7)  ON 02+ SOP-8 !Features 1) Suitable for damping resistors. 2) Convex electrodes  
IN1 (12)  In addition, the low-power properties of Siemens ACMOS technology allow ap
IN2 (13)  INNO SMD N/A RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Vol
IN3 (5)  This advanced technology has been especially tailored to mini- mize on-st
IN4 (144)  Extended data out (EDO) allows data output rates up to 40 MHz for 60-ns d
IN5 (89)  Limits in standard typeface are for TJ = 25˚C and limits in boldfac
IN6 (12)  N/A N/A N/A   The state of the OUT pin is driven by a voltage comparator whose o
IN7 (95)  HYNIX 02+ SOP-7.2-20P It features a preamplifier module with adjustable gain and a unique power
IN8 (51)  RichTek 08+ The 64Mb SDRAM has the ability to synchronously burst data at a high da
IN9 (13)  RichTek 08+ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
INA (1030)  TI 07+ PARAMETER Soft-Start Section Charge Current Power Good Section Fb1 Low
INB (5)  Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current
INC (16) 
IND (31)  IND 06+
INE (7)  NEC 04+ • 1024 refresh cycles, 16 ms refresh interval   - RAS-only or
INF (3)  Infineon The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an
ING (3)  /DACK /DMA Acknowledge (Input, active Low). /DACK, in conjunction with /I
INI (12)  NS 08+ The UART transmits data, sent to it over the peripheral 8-bit bus, on the
INK (2)  00+ SOP This device contains circuitry to protect the inputs against damage due
INL (4)  INNOCOR 11/DIP 07+/08+ Specifications Outline Dimensions Pin Connections and Short Description
INM (2)  INMOS(ST) LCC20 Limited range ADC : VDD > Vref > Vgnd, Vgnd=VDD/2. For power savin
INN (2)  EL DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGM
INP (1)  N/A N/A N/A Master Clock. Master clock provides the clock for DSP. In MPI mode, it
INQ (3)  BI 04+ SOP-16 NOTES: 1. H = HIGH Voltage Level   L = LOW Voltage Level   X
INR (16)  N/A 0805BEAD   The first character of the part number suffix determines the devic
INS (124)  nsc nsc dc86 The Application Engineering Group is available to assist you with the app
INT (87)  BB 2007 SWITCHING PARAMETERS Qg(4.5V) Total Gate Charge QgsGate Source Charge Q
INV (41)  STM SOP-8 04+ The B-port drivers are Low-capacitance open collectors with controlled
INX (1)  • Single element, current limiting fuses provide superior short-cir
INY (4)  PI DIP 06+   The PT4580 series is a single-output isolated DC/DC converter, ho
IO- (2)  The bq2014 determines battery capacity by monitoring the amount of charge
IO1 (1)  TEMIC Hynix HYMD232646A(L)8J-J series incorporates SPD(serial presence detect).
IO2 (1)  TOS 99 Stresses beyond those listed under absolute maximum ratings may cause per
IO4 (2)  SMD   Simplifies Circuit Design   Reduces Board Space   Reduc
IOA (4)  † All characteristics are measured with a 0.33-µF capacitor a
IOB (2)  MOT The LM4924 is a Output Capacitor-Less (OCL) stereo head- phone amplifier
IOC (8)  AMIS 0302+ SSOP New high voltage technology designed for ZVS-switching in lamp ballasts
IOD (2)  120 MICROCHIP 99+ 1. Storage Under normal circumstances, storage of beam lead diodes in
IOF (1)  SANKEN 03+ Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Inpu
IOI (3)  AMIS 06+ 500 A configuration interface between the controller and the Altera FPGA(s)
IOM (2)  MITEL QFP2828-208 00+/01+ Applying a LOW to the INIT input causes an immediate load of the program
IOP (2)  SHARP QFP 2000 Notes: (1) See SOA curves or consult factory for appropriate derating. &
IOR (235)  N/A N/A N/A The FM20 can be easily mounted by gluing or cementing it to a surface. I
IOS (2)  microprocessor. When the voltage on VSENSE rises above the COMMAND volt
IOT (2)  The digital serial interface can be configured for 3-wire operation and
IOU (1)  MITSUMI SOT23 06+ NOTES 1Stresses above those listed under Absolute Maximum Ratings may ca
IOW (1)  1. Use of the READY pin is optional. 2. Introducing an RC delay to the
IOX (1)    Variations on this circuit could easily be made Simply by revers
IP- (374)  N/A   2.4 V to 18 V Steady State Power Rating of 200 mW Small Body Ou
IP0 (21)  SOP8 IOR 98+ A modulation current control loop (MCCL) maintaining a constant modula-
IP1 (109)  IOR BGA 04+ Revised orderable part numbers on page 2. Revised Table 2, Table 14, Ta
IP2 (77)  2008 The readout procedure is shown in figure 1. This procedure is valid for a
IP3 (83)  HYNIX DIP-8P 6+ The comparator compares the wiper voltage VW with the external input vo
IP4 (109)  PHILIPS 2004 Input Voltage Noise Non-Inverting Input Current Noise Inverting Input
IP5 (26)  NXP 07+ 07+ DESCRIPTION: The CENTRAL SEMICONDUCTOR CMPZDA2V4 Series silicon dual zen
IP6 (4)  N/A SOP 07+ Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both = "1&quo
IP7 (13)  IOR SOP-8P 03+ These unconditionally stable amplifiers provides 21dB of gain and +12dBm
IP8 (66)  TEMIC DIP Single 1.2-V to 3.6-V Supply Operation High Throughput C 200/240/280KSPS
IP9 (28)  INTERPION SOP-28P 05+ ICs form an on-board 28-bit serial-in/parallel-out shift register with c
IPA (18)  Power DissipationInternally limited Input Voltage15V Operating Junctio
IPB (133)  INFINEON TO-263 08+ • Device with high radiant intensity suitable for   surface m
IPC (35)  HYNIX HSOP-3.9-7P 6+ This document is a general product description and is subject to change wi
IPD (115)  INFINEON 06+ These dual beam leads are intended for use in balanced mixers and in eve
IPE (60)  CMD SSOP-20 96+ The MAX6950 and MAX6951 are five-digit and eight-digit common-cathode LED
IPF (21)  Infineon TO-251   Operating temperature range is: C40C to +85C.   Guaranteed b
IPG (8)  IR 06+ TO-247 Notes:  1. Stresses greater than those listed under absolute maximu
IPI (50)  INFINEON TO-262 08+ Notes: (i) Io 1(min) current of 0.1A can be divided between both outputs
IPL (6)  TI 2001 • High speed   tAA = 12 ns • Low active power  
IPM (26)  SAMWON 04+ Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control Wit
IPN (7)  IC+ The no-correction window size is 324 ns for DPLL #1 and 32 µs for D
IPO (2)  The PKA 2000 I Series DC/DC power modules are designed in accordance with
IPP (112)  INFINEON TO-220 08+ • In-house programming of samples and prototype   quantities
IPQ (2)  IP stock The Constant, B, related to the failure mechanism is derived from either
IPR (33)  IR DIP 07+ Sport Mode or GPIO5 Sport Mode or GPIO6 GND 12MHz Clock/Crystal Input
IPS (213)  IR 04+ Each DS1258W device is shipped from Dallas Semiconductor with its lithium
IPT (7)  LATTICE QFP All of the bytes in the chip must be verified to check whether they have
IPU (40)  INFINEON TO-251 08+ Maximum ratings are those values beyond which device damage can occur. Ma
IPV (3)  2008 Signal Processor (DSP) TMS320C6701 C 8.3-, 6.7-, 6-ns Instruction Cycle T
IPW (9)  INFINEON TO-247 07+ 433-MHz, 868-MHz, and 915-MHz Industrial, Scientific, and Medical (ISM) B
IPX (2)  JAT SMB 05+ microcontroller. Many common microcontrollers have hardware SPI ports a
IQ1 (3)  IQ 08+ NOTES: (1) For detailed drawing and dimension table, please see end of da
IQ3 (6)  12 BGA 96+ Several pins on this device serve as dual function in- put/output pins. D
IQ4 (1)  I-CUBE MQFP1420 9810 Single Package Fully-integrated 4-bit Flash Microcontroller with RF Transm
IQ6 (3)  AVIQ TQFP 03+ instant visual indication if there are any issues with the wiring plant
IQ7 (1)  INTERSIL DIP-40 01+ † The D package is available taped and reeled. Add the suffix R to
IQ8 (3)  TI QFP44   The switching safe operating area (SOA) of Figure 9 is the bounda
IQ9 (3)  The LT ®1937 is a step-up DC/DC converter specifically designed to dr
IQA (1) 
IQB (2)  MINI 08+ † Stresses beyond those listed under absolute maximum ratings may c
IQD (10)  DPL 4519G Programming Interface User Registers Overview Description o
IQK (1)  Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2
IQM (1)    devicescatalogs, data books, etc. Contact SHARP 8 (Internet) &ie
IQS (3)  INF 04+ SOP8   4.3 Screening. Screening shall be in accordance with table IV of M
IQT (2)  ST QFP1420-100 The ADS5553 is a high-performance, dual channel, 14 bit, 65 MSPS analog-t
IQU (2)  AGILENT N/A The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an
IQX (74)  jauch jauch dc01 Changes throughout document including the following chapters and/or secti
IR- (12)  AKR SMD 03/+04+ The loop is stabilized by a PID compensation amplifier with high stabili
IR/ (1) 
IR0 (92)  ir ir dc99 The 3D7205 5-Tap Delay Line product family consists of fixed-delay CMOS i
IR1 (307)  ir ir dc04 Notes: 1Tester measures code transitions by dithering the voltage of the
IR2 (1018)  IOR SOP-8 04+ • The basic gate function is lined up as Renesas uni logic series.
IR3 (737)  ir ir dc0414 F High-performance CMOS non-   volatile static RAM 2048 x 8 bitsF 25
IR4 (147)  ir ir dc00 When operating properly with 5V in (for example), VOUT will also be abou
IR5 (122)  IR SIP SERIAL BUS TIMING   Clock Frequency, fSCLK   Glitch Immunity,
IR6 (79)  ir ir dc86   The LVC244A device is organized as two 4-bit line drivers with sep
IR7 (205)  IR SOP-8? UART channel A Receive Data or infrared receive data. Normal receive data
IR8 (69)  IRF 97 SOP-8 The IA186ES/188ES microcontrollers are an upgrade for the 80C186/188 micr
IR9 (174)  NAGAREC SOP 05+ During power-on, RESET is asserted when the supply voltage VDD becomes hi
IRA (50)  SANYO 05+ 314 (Note) (1) "NEC Electronics" as used in this statement means N
IRB (10)  HP PLCC 06+ The pulse width is controlled by means of an external po- tentiometer (4
IRC (107)  IR 07+ Note 4 For a power supply of 5V g10% the worst case output voltages (VOH a
IRD (70)  IR 07+ The SIE allows the IRDCIP1203-A series to communicate with the USB host t
IRE (10)  06+ SMD The Virtex-E FPGA family delivers high-performance, high-capacity progr
IRF (8083)  IOR 06+ 20000 The ICM7211AM accepts a four-bit true binary (i.e., positive level = logi
IRG (914)  IR TO-263 04+ Stresses beyond those listed under "absolute maximum ratings" m
IRH (312)  IR TO-254AA 00+ Note 4: Dynamic supply current is higher due to the gate charge being de
IRI (29)  IR TO-220F Note 1: Specifications to -40C are guaranteed by design and not production
IRJ (2)  I Occupies only 2.25 mm2 of PCB area.   Less than 50% of the area o
IRK (1697)  IR A proper value of feed forward capacitor parallel with  R1 can impr
IRL (1484)  IR 975 Care should be taken before applying power and signals to the evaluation
IRM (121)  EVERLIGHT Dip-3 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t
IRN (1)  N/A SOP5.2mm
IRO (3)  IR 01+ ZIP-7 During the rise and fall time interval when switching a resistive load,
IRP (71)  IR 07+ In simple mode all feedback paths of the output pins are routed via the a
IRR (13)  220 04+ Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
IRS (290)  IR 06+ This is accomplished by converting the input voltage to a current which i
IRT (17)  ITT (*) CPD is defined as the value of the ICs internal equivalent capacitanc
IRU (533)  IR TO-220 infrared heat lamp for 5C10 minutes on clean filter paper. Freon degreas
IRV (15)  IR SOP-8 03+ • Low-power CMOS technology:   - Maximum write current 3 mA a
IRW (2)  The CY29946 is capable of generating 1 and 1/2 signals from a 1 source. T
IRX (10)  LUCENT Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active
IRY (1)  SIS The MAX1698 features digital soft-start and adjustable lossless LED curre
IS- (43)  TEMIC PLCC44 2007+ The UC3825A,B has dual alternating outputs and the same pin configurati
IS0 (34)  SHARP CAN8 06+ • T.M. 4.1 Service Classes   C CBR   C VBR (single, dual
IS1 (37)  ISOCOM 06+ Each IS101 contains a unique 64Cbit code (see Figure 5) stored in ROM. Th
IS2 (270)  96 TI warrants pe rformance of its se miconductor products to the spe cifica
IS3 (12)  ISSI 05 Ergonomics   Convenient front access to USB, audio,   and Sma
IS4 (412)  ISSI TSOP 03+   This data sheet provides an overview of the R4700s CPU features a
IS5 (19)  142 TEMIC 99+ The MX841 features a 1.0MHz switching frequency to accommodate the use of
IS6 (1834)  ISSI SOJ An overrun character is placed in the HT82K628A buffer and replaces the l
IS7 (14)  DENSO 07+ SOP The IS93C46A/56A/66A are controlled by a set of instructions which are
IS8 (158)  PLCC 04+ Asasecond-generationHOTLinkdevice,the CYP(V)15G0401DXB extends the HOTLin
IS9 (71)  ICS SSOP56W 03+ The switching PWM controller drives two N-Channel MOSFETs in a synchronou
ISA (3)  NPC MODULE N/A system is fail-safe; that is, the slaves will be continue operating sho
ISB (32)  ST 798 The Intersil HS-80C86RH high performance radiation hardened 16-bit CMOS
ISC (82)  06+ 1210-4.7UH   The RC4700 incorporates a complete floating-point co-processor on
ISD (481)  ISD The CLBs are used to implement most of the logic in an FPGA. The princi
ISE (1)  itron QFP128 B ild / Fig. 7 W1C - E inpha sen -We ch selweg schaltung / S ingle- phase
ISF (2)   1. Package is non-polarized. Parts may be on reel in orientation il
ISG (4)  PLUSS TSSOP 00+  The Hynix HYM71V8635AT6 Series are Dual In-line Memory Modules suit
ISH (2)  ST 02+   The IDT70V7399 is a high-speed 128Kx18 (2Mbit) synchronous Bank-S
ISI (6)  ISSI DESCRIPTION The M74HC4020 is an high speed CMOS 14 STAGE BINARY COUNTE
ISJ (2)  The above default CD/Mute function can be overwritten as follows: if the
ISL (3928)  INTERSIL LQFP-208P 2003 Note 1: Dropout is caused by either minimum control voltage (VCTRL) or mi
ISM (53)  GPS 2008 Input Voltage as low as 1.4V 250mV dropout @ 1A Adjustable output fro
ISN (5)  TAIYO DIP18 04/05+ Through its 1-Wire interface, the DS2751 gives the host system read/write
ISO (219)  BB DIP DIP Min. Typ Max. Min. Typ. Max. UnitsTest Conditions 80 80VApplied drain-t
ISP (2358)  LATTICE 2007 Voltage-feed-forward ramp modulation, current mode control, and internal
ISQ (9)  ISOCOM 04+ 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the
ISR (26)  RECTRON TO-220F 05+ • AN765, Using Microchips Micropower LDOs,   DS00765, Microchi
ISS (153)  ISSI 3.9mm 2000 The following characteristics are applicable to the operating temperature
IST (15)  IDT SMD —— The Hynix HYM71V16635HCT8P Series are 16Mx64bits Synchronous DRAM Modules.
ISU (3)  MOT PLCC52 06+ This device can be used as four 8-bit transceivers, two 16-bit transceive
ISV (40)  FT深圳一极代理 07/08+ The HYM72V64656T8 H-series are gold plated socket type Dual In-line Memory
ISW (1)  ISSI 0516+ The data receiver block is a decoder for decoding the serial input data fr
ISX (1)  This is a single positive-edge-triggered D-type flip-flop. When data at t
ISZ (1)  4 The MAX1156/MAX1158/MAX1174 are ideal for high- performance, battery-powe
I-T (1)  ST ISO422 can be used in half duplex, or full duplex data communication bus
IT- (11)  IL SWITCH 2005 THERMAL EFFECTS Internal heating can have a significant effect on curren
IT0 (4)  IT 04+ DESCRIPTION: The CENTRAL SEMICONDUCTOR BZV55C2V4 Series Surface Mount Si
IT1 (14)  N/A N/A N/A • Flexible dual-bank architecture   C Support for true concurr
IT2 (16)  NEC 05+ BGA These converters are manufactured in a facility certified to MIL-PRF-38
IT3 (25)  INFRANT BGA 05+   The RC4700 floating-point execution units support single and doubl
IT4 (7)  ITT SOT-23-5 06+   The NCP1000 through NCP1002 series of integrated switching regula
IT5 (9)  N/A N/A N/A With pin 4 connected according to Figure 3 on page 8, the set duty cycle
IT6 (7)  SOT23 standard for high-speed system bus running at half the CPU clock High-b
IT7 (5)  ITE SOP16 05+ Serial Data (SDA) SDA is a bidirectional pin used to transfer data into
IT8 (200)  ITE 05+ CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output
IT9 (9)  Jack(Available) The Programmable Interconnect Matrix (PIM) connects the two logic blocks
ITA (37)  HP n/a 96   The ITA-06328/1226/1227 performs voltage conversions but does not
ITB (1)  International Airport Industrial Park • Mailing Address: PO Box 1140
ITC (20)  CLARE SOIC-16 03 The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramati
ITD (36)  INTEL 00+ •This catalog has only typical specifications. Therefore,thereareno
ITE (5)  INTERSLL 8219 Lead Temperature (soldering, 10s)+300C (1) Stresses above these ratings
ITF (19)  N/A 01+ TO-3 The ispLSI 1032EA is a High Density Programmable Logic Device containin
ITI (8)  SOP-16 98+ Note: 1. These modes limit to 15 bits (SO14-0) instead of 16   (SO
ITJ (2)  ZILOG DIP 93+ Wavelengths of light less than 4000 Angstroms begin to erase the ITJ3V0 i
ITL (2)  Micrels ITL117 is a high efficiency boost PWM control IC. With its wide
ITM (14)  SIMcom 07+
ITN (1)  Output Capacitors The minimum required output capacitance is 330µF
ITP (8)  MOT PLCC52 06+
ITQ (1)  BI SSOP16 02+ • Point of Load (POL) applications such as drivers for   FPGAs
ITR (25)  EVERLIGHT  Lead Temperature 1.6mm (1/16 inch) from Case for 10s260C (1) Stres
ITS (168)  ST 04+ † Stresses beyond those listed under absolute maximum ratings may c
ITT (95)  ITT TO-92 98+ The ITT022L4 is a low cost high speed JFET input operational amplifier w
ITV (21)  STM SOP-20 04+ Description The HYS 64V64220GU and HYS 72V64220GU are industry standard
ITW (5)  ITW 06+ 555   Features 1) The built-in bias resistors consist of thin-film resis
ITY (1)  Clear Channel Assessment (CCA) is an output used to signal that the chann
ITZ (2)  HP 94 This parameter is measured with the recommended copper heat sink pattern
IU- (2)  Notes: 1. For Max. or Min. conditions, use appropriate value specified un
IU0 (2)  SONY CCD N/A
IU1 (4)  IR 06+ SOP-8 96 Outputs Plasma Display Driver 95V Absolute Maximum Rating Reduced E
IU8 (5)  LGS 02+ DIP-M30P This output presents the output of the demodulator when chip in power up
IUA (1)  MAX 02+ 7858 System designers have the option of embedding PowerPacket-specific control
IUB (1)  AMIS O7+ During the switch between active and standby conditions, transient curren
IUG (1)  the full-scale output current. The differential linearity errors of the
IUL (2)  * High performance CMOS technology. * Rhythm wind or Normal wind for SLEE
IUM (3)  N/A N/A N/A Note: 1. Commercial Product : TA=0 to 70C, unless otherwise specified &n
IUP (1)   This IC's package is POWER-SSOP, so improVing the board on which th
IUS (1)  If the X76F102 is in a nonvolatile write cycle a no ACK (SDA=High) resp
I-V (1)  TI 07+ Location 00H is an indirect addressing register that is not physically im
IV0 (1)  N/A SOP-8 The power handling ability of a power transistor is charac- terized by i
IV1 (1)  QFP 01+   The NCP1086 voltage regulator series provides adjustable and 3.3
IV3 (2)  CYPRESS O7+ Programmable undervoltage and overvoltage detectors disconnect the load w
IV4 (1)    Three-State PWM Input for Power Stage Shutdown   Internal Bo
IVA (27)  HP 06+ 500 The SN74LVT16646 is available in TIs shrink small-outline (DL) and thin s
IVC (7)  PHILIPS SMD20 ©2002 by ZiLOG, Inc. All rights reserved. Information in this publica
IVD (1)  ST The SNI consists of five main logical blocks a) the oscillator generates
IVG (1)  • Provides a C2/C1.5 output clock signal with the frequency  
IVL (1)  IVL PLCC44 01+ Absolute maximum ratings indicate sustained limits beyond which damage to
IVM (2)  Automatic test equipment High speed instrumentation Scope and logic anal
IVN (7)  N/A 01+ TO-3 The APA4863 is a stereo bridge-tied audio power am- plifier in various po
IVP (1)  TEX QFP 04/05+ • High-speed, low-power, unidirectional, First-In   First-Out
IVR (6)  IVNET 2008 The DLYBLK input can be used to halt address generation at the end of a
IVS (4)  invox invox dc99 Write Protect, active Low/Accelerate (VHH). W r it e Pr ot ect Funct ion
IVT (3)  RAKON 99+ The CY7B951 provides the necessary clock and data recovery function to
IW- (1)  • 13 I/O pins with individual direction control • High curre
IW0 (3)  JRC 00+ SSOP The architecture of the Direct RDRAMs allows the highest sustained band
IW1 (5)  29 XINGER 04+ When the X-rays emitted from the X-ray generator pass through the materi
IW2 (6)  IWATT Notes: 7. Typical performance plots are based on test   board shown
IW3 (2)  Techwell The R1RW0408D is a 4-Mbit high speed static RAM organized 512-kword 8-bi
IW4 (25)  HYNIX 02+ DIP-S14P since an approaching finger could be compensated for partially or entire
IW5 (4)  Leads are Readily Solderable Lead and Mounting Surface Temperature for S
IW7 (1)  MX The CZ80CPU is designed to run at frequencies up to 80 MHz on a typical 0.
IW8 (8)  CAN3 Excellent power supply ripple rejection for VIN-VOUT down to 110mV Exce
IW9 (1)  SGS CAN3 04+ The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outpu
IWD (13)  N/A Note The data output functions may be enabled or disabled by various sign
IWH (2)  . . 04+ BENEFITS • Long life • Maintenance free • Current-lim
IWI (2)  The LPC2210/2220 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU
IWR (1)  JAT 3W 05+ • True dual-ported memory cells that allow simultaneous   acc
IWS (34)  IPD DC/DC模块 0043+ Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type.
IWT (1)  N/A Stability The IRU431L has many different domains of stability as a funct
IWV (2)  ITSWELL For cellular phone and PDA applications, voltage-mode control provides
IWW (2)  KIT Pin Description Chip Select. Activates the device. When high, all output
IX0 (566)  499 SHARP eight CAT24FC02 may be individually addressed by the system. The last b
IX1 (299)  SHARP The Broadcom reference design is based on the industry-proven ARM9 RISC
IX2 (329)  N/A SOP 07+ SG1 applied to V22, V27 and V31, SG10 applied to V46, SG2 applied to V60
IX3 (60)  SHARP PARAMETER VCC Turn On Voltage VCC Turn Off Voltage VCC Hysteresis VCC
IX4 (2)  IXYS DIP14 07+ Information furnished is believed to be accurate and reliable. However, S
IX5 (5)  Xinger SMD 02+ The MAX202ECMAX213E, MAX232E/MAX241E line drivers/receivers are designed
IX6 (5)  IXYS DIP14 07+ The "double sampling" aspect of CDS refers to the operation of
IX7 (3)  SHARP The LCX240 is an inverting octal buffer and line driver designed to be
IX8 (3)  SHARP 86 Copyright © 1995, VIA Technologies Incorporated. Printed in Taiwan. A
IX9 (3)  Eight of the macrocells (I/OF0CI/OF7) have two inde- pendent feedback
IXA (51)  SHARP Low power RS-485 systems Network hubs, bridges, and routers Point of
IXB (61)  IXYS TO-3P 05+ SYNC (Pin 5): The SYNC pin can be used to synchronize the oscillator to a
IXC (30)  TOSH SOP48 03+ Stresses above these ratings may cause permanent damage. Exposure to abso
IXD (165)  1850 This IC contains a zener clamp structure between the chip VCC and COM wh
IXE (57)  INTEL 2007 Current Output, Sourcing Current Output, Sinking Closed-Loop Output I
IXF (915)  IXYS O6+ TO-247 Form, Fit and Function Compatible with the DEC™ 21140AF Available
IXG (551)  IXYS TO-247 05+ Thermal Ground FBAR resonators have a negative temperature coefficient o
IXH (9)  IXYS TO-3P The Clock and Data Recovery stage was designed to automatically recover t
IXI (8)  SHARP DIP-42 01+ IXI147CENI is a clock generator IC that can generate multiple frequencies
IXJ (1)  IXYS SOP8 07+ Philips provides a sophisticated API running on the internal 80C51, all
IXK (28)  IXYS TO-220 08+ The AFV461 EMI filter will reduce the input line re- flected ripple cur
IXL (43)  SHARP SMD INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11   Input
IXM (8)  IXYS DIP 06+ Unlike other nonvolatile memory technologies, there is no write delay wit
IXN (1)  QFP 9439+
IXO (16)  The bus protocol is controlled by transition states in the SDA and SCL
IXP (39)  LEVELONE 2007   It is important that the logic used to turn ON and OFF the various
IXQ (2)  The HS-26C32RH has an input sensitivity typically of 200mV over the comm
IXR (11)  BB 04+
IXS (159)  IXYS 2007 The IXSN50N60UI is a high performance , very low power CMOS Static Random
IXT (1047)  IXYS TO-263 08+   Low power loss, high efficiency   Low profile surface mount p
IXU (9)  IXYS SOP Hynix HYMD18M725A(L)6-K/H/L series incorporates SPD(serial presence detect
IXW (10)  AV+,BV+,CV+ - Are the power connections from the hybrid to the bus. The p
IXX (2)  UT 06-07+ Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
IXY (24)  IXYS The HLMP-0X0X series of rectangular lamps are direct replace- ments for A
IXZ (3)    Pb−Free Package is Available   Designed for 1.65 V to 5
IY0 (1)  The C-suffix devices are characterized for operation from 0C to 70C. The
IY1 (2)  ST 99 POWER SUPPLY BYPASS Since the LM2471 is a wide bandwidth amplifier, prop
IYA (2) 
IZ1 (1)  TAMRA FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit
IZA (24)  250 SHARP 98+ The error amplifiers exhibit a common-mode voltage range from C0.3 V to V
IZN (1)  shar qfp 07+ The APW7093 is a reversible energy flow, constant- off-time, pulse-width
IZT (1)  Clocking is accomplished through a 2-input NOR gate per- mitting one in
IZY (4)  diotec diotec dc00
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