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D/2 (1) 
D/4 (1) 
D/A (3) 
D/F (1) 
D/Q (1) 
D/Z (7) 
D-0 (2)  CONTACT SOP 411 SPI Serial Memory The memory portion of the device is a CMOS Serial EEP
D00 (34)  SMD 05+ This three terminal positive adjustable voltage regulator is designed to
D01 (54)  BGA 01+   The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
D02 (17)  FAIRCHILD QFN 05+ The TLV349x family of push-pull output comparators fea- tures a fast 6&
D03 (46)  MARKI 0021+ Controller (host) will send start bit. Controller (host) sends the read
D04 (17)  FALCO原盘 SMD This document describes how to implement a switching volt- age regulator
D05 (33)  coilc coilc dc99 RSL (Pin 4): The slew control resistor sets the maximum current and volta
D06 (28)  CEN 28000 A write operation requires an 8-bit data word address following the devic
D07 (24)  Dialog TSOP-20P 6+ The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable L
D08 (40)  99 Circuit Board Material: .014 Getek, 4 - layer, 1 oz copper, Microstrip li
D09 (54)  DiaIog O7+   ARM7TDMI™ ARM® Thumb® Processor Core   Two 16-b
D0A (2)  As shown in the functional block diagram on Page 1, the ADSP- 21262 uses
D0C (20)  its I input changes. When LEn is LOW, the latches store information tha
D0E (1)  QFN 06+ The D0E01 is a fully integrated transceiver for dual band IS136/AMPS hand
D0N (1)  Youre probably having trouble keeping the constant voltage across RA and
D-1 (13)  RYC 07+ 38000 As the battery accepts charge and approaches the pro- grammed voltage, th
D1- (46)  HARRIS DIP   Parameter Read cycle time Address access time Chip select1 ac
D10 (337)  N/A SSOP 98+ IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and pub
D11 (392)  DIALOG BGA0808 03+ • 10,000 erase/write cycles Enhanced FLASH   Program memory t
D12 (731)  ROHM TO-220F 06+
D13 (87)  HITACHI Notes:  1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Dont
D14 (75)  01+ 1. Torque rating applies with use of compression washer (B52200-F006 or e
D15 (247)  The TPS5435x devices are available in a thermally enhanced 16-pin TSSOP
D16 (278)  AML Figure 2 shows the waveforms of the circuit of Figure 1. This circuit h
D17 (502)  NEC DIP N/A Under-Voltage Lockout An Under-Voltage Lock-Out (UVLO) inhibits the ope
D18 (110)  TOS TO-3P The Read operation of the EM39LV040 is controlled by CE# and OE#. Both hav
D19 (43)  SANYO TO-220F 03+ Shunt protection devices clamp voltage peaks at the Output-Pin and VDD-
D1A (10)  KUAN DIP-8 95+ Time t6, represents a transition between light and heavy load. A single
D1B (2)  KUAN DIP 94+ An address access read is initiated by a change in address inputs while
D1C (6)  COSMO Relay(new original) North America Literature Fulfillment: Literature Distribution Center for
D1D (9)  N/A N/A N/A Notes:  2. X =Don't Care. H = Logic HIGH, L = Logic LOW. BWx = 0 si
D1E (2)  SHINDENGEN SMD 2008 4. Dropout voltage is defined as the input-to-output differential at which
D1F (81)  TOSHIBA SOD-106 Device logic is automatically configured to the users speci- ʂ
D1G (3)  2008 The D1G-11TF provides two high-speed serial communication ports (UARTs),
D1H (3)  ST TO-252 Each circuit of the HEF40106B functions as an inverter with Schmitt-trig
D1J (1)  DIP-6 07+/08+ The D1JA memory array consists of fourteen 8-byte sectors. Read or writ
D1L (3)  Load Mux. RRE = "1" and MSE = "1": LDM is an output te
D1M (1)  The SMLW010 Single-Output, Low-Profile, PCB Mount Power Modules are low-p
D1N (44)  新电元 The JFET-input operational amplifiers in the TL07x series are similar to
D1P (4)  92 DIP The PWM signal is the control input for the driver. The PWM signal can en
D1R (1)  MURATA 05+ The XC2173 series are high frequency, low power consumption CMOS ICs wit
D1S (1)  2005 VSENSE (Output Voltage Sensing Input): This pin is connected to the syst
D1U (7)  SHINDENGEN BENEFITS  2 lines low-pass-filter + 2 lines ESD protection  H
D1V (3)  Stresses above those listed under Absolute Maximum Ratings may cause pe
D-2 (8)  N/A 1458 99+ The core of the picture processor (see block diagram) is formed of the Im
D2- (4)  D2 QFP 06+ Low Quiescent Current of 40 mA Typical Low Dropout Voltage of 100 mV at
D20 (159)  SML HIGHFREQUENCY N/A (*) CPD is defined as the value of the ICs internal equivalent capacitanc
D21 (227)  INTEL CDIP18 9539 SMDI will provide the detailed layout (AutoCad format) to users wishing t
D22 (62)  NEC 2008 ActiveArray™ Bottomless™ CoolFET™ CROSSVOLT™ D
D23 (145)  NEC Test data output. One of four terminals required by IEEE Standard 1149.1-
D24 (80)  SONY QFP 98+ Leakage Current: Capacitors shall be stabilized at the rated temperature
D25 (721)  FCI 08+   Integral Nonlinearity (INL)2   Offset Error (Unipolar, Bipol
D26 (12)  EUPEC 4820A,8500V,9000V 07+特价模块 Regulates voltage over a broad operating current and temperature range E
D27 (495)  INTEL Note 1: All voltages with respect to Gnd (Pin 1). Note 2: All currents
D28 (168)  INTEL DIP N/A VBIAS (VCC, VBS, VDD) = 15V, unless otherwise specified. The VIN, VTH and
D29 (59)  MOT SOP8 N/A Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
D2A (17)  HASCO DIP 4+4 08+ The 221 and LS221 devices are dual multivibrators with performance char
D2B (1)  N/A SMD 98+ † All typical values are at VCC = 3.3 V, TA = 25C. ‡ This is
D2C (8)  INTEL DIP N/A   Typical specifications represent average readings at 25C and VDD =
D2D (8)  N/A OMRON 05+ In addition, the AT8xC5112 has a Hardware Watchdog Timer, a versatile ser
D2E (1)    Featuring continuous load current ratings to 500 mA for each of t
D2F (69)  OMRON 原装 08+ These Schottky diodes are specifically designed for both analog and digi
D2H (5)  OMRON 原装 08+ To verify that the input offset voltage falls within the limits specified
D2J (9)  OMRON 原装 08+ This input terminal is used to manage the cross-conduction between the int
D2L (17)  GULF DO-15 2007   Maxim evaluates pressure pot stress from every assembly process du
D2M (16)  OMRON 原装 08+ The MAX1978 operates from a single supply and provides bipolar 3A output
D2N (28)  NI The DAC0808 series is an 8-bit monolithic digital-to-analog converter (D
D2P (5)  N/A N/A N/A This device utilizes advanced silicon-gate CMOS technolo- gy to implemen
D2R (8)  OMRON 原装 08+ The 3-wire serial interface operates at clock rates up to 50 MHz and is
D2S (51)    The NCP1050 through NCP1055 are monolithic high voltage regulator
D2T (1)  MOT CAN6 02+ 25 mV (or less) For normal line resistances data may be recovered from l
D2V (8)  N/A OMRON 05+ Compliance with PCI Local Bus Specification revision 2.2 Supports full-d
D2W (30)  N/A n OSD Window Fade In/Fade Out n OSD Half Tone Transparency n OSD overrid
D2X (2)  In Discontinuous mode, when the inductor current drops to zero, the vol
D-3 (4)  AMP PCB-3 99+ The TPS6113x devices provide a complete power supply solution for product
D3- (15)  HARRIS O7+ We Listen to Your Comments Any information within this document that you
D3. (1)  NEC MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The
D30 (117)  202 HITACHI 96+/97+/98 Hynix HYMD264646(L)8-K/H/L series incorporates SPD(serial presence detect)
D31 (54)  N/A N/A N/A Notes: 1. Absolute maximum ratings are limits beyond which operation may
D32 (64)  TI SOP Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Seria
D33 (43)  NEC DIP 06+ Precision Optical Performance AlInGaP II (aluminum indium gallium phosph
D34 (53)  The standard device offers access times of 45, 55, 70, 90, and 120 ns,
D35 (77)  HOSONIC 0609+
D36 (97)  55 TEXAS O2 NOTES: (1) Stresses above these ratings may cause permanent damage. Expo
D37 (116)  NEC SOP 98   Octal bidirectional bus interface   Non-inverting 3-state out
D38 (145)  YAGE BGA 1999 xeala CHARACTERISTICS (Ta=25C, V =9V, RL=47kΩ, Vin=100mVrms/1kHz &
D39 (22)  PLCC-84 96 Care should also be taken in the resistor selection to ensure that the c
D3C (8)  N/A SMD 1998
D3D (10)  OMRON 原装 08+ Miniature,cost-effective switching solution. Molded construction for comp
D3E (2)  N/A 3X3可调电阻 The device offers fast page access times of 25, 30, and 45 ns, with corr
D3F (11)  MOT SOP8 N/A Up to 3-A Output Current at 85C 3.3-V / 5-V Input Voltage Wide-Output Vo
D3G (1)  Up to 2 Gsps Sampling Rate Power Consumption: 4.6 W 500 mVpp Differentia
D3H (1)  N/A N/A N/A Microchip received ISO/TS-16949:2002 quality system certification for it
D3J (1)  00+ TO-23 OBDL (pin 12) and OBDK (pin 13)  These are the active high output s
D3L (5)  SHINDENG TO-220 AO is driven by a source follower that requires an external pulldown resi
D3M (6)  OMRON 原装 08+ The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local
D3N (13)  95   The NCV8501 is a family of precision micropower voltage regulator
D3P (2)  The POWER MOS 7® IGBT is a new generation of high voltage power IGBTs
D3S (25)  新电源 The D3S82 and D3S82 are designed for a number of general purpose video, c
D3U (1)  When a push-button is used to manually reset a µP, ringing from the
D3V (1)  The main PLL within the D3V-6G-1C24-K is constructed from an input pream
D3W (1)  This monolithic device contains a sawtooth oscillator, error amplifier, a
D-4 (5)  0731+ Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR
D4- (3)  HAR   3.8 Notification of change for device class M. For device class M,
D40 (228)  NEC SOP16S 2007+ 32-bit non-multiplexed address and data bus High-speed interruptible DMA
D41 (192)  N/A 00+ DIP-16 ACEx™FACT™ ActiveArray™FACT Quiet Series™ Bottomless
D42 (311)  NEC 93+ Note 9: If the product is in shutdown mode and VDD exceeds 3.6V (to a max
D43 (424)  3637 † Stresses beyond those listed under absolute maximum ratings may c
D44 (173)  NEC DIP24 Note 1: Absolute Maximum Ratings are those values beyond which the safet
D45 (180)  ON-SEMI SCG 07+ W - Wiper of the Potentiometer. This pin is the wiper of the potentiomete
D46 (32)  SMD-30 05+ BURST SUSPEND: The Burst Suspend feature allows the system to temporarily
D47 (81)  93 The SRC input of the bq2060 measures battery charge and discharge current
D48 (89)  NEC TSOP 99+ drivers to drive either 3.3V or 2.5V output levels while the device logi
D49 (29)  DIP CHMC 04+ Figure 1-2 shows how the key values in EEPROM are used in the encoder.
D4A (7)  NEC DIP24 2007+   The D4A6C contains a silicone dielectric gel which covers the sili
D4B (4)  Synchronous rectification provides excellent efficiency at high power lev
D4C (3)  MOC SMD-8 04 05 High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF
D4D (4)  4200 In the multi-picture mode the operating mode transmitted on the I2C Bus i
D4E (2)  The buffers wide input dynamic range enables them to receive dif- ferent
D4F (1)  SHINDEGEN SMD 04+NOPB1000 The on-chip status register allows the progress of various operations to
D4G (1)  Direct Interface to ISA and PCMCIA with No Wait States High Impedance Sp
D4L (5)  PI TO-220F SILENT SWITCHER â UHC™ SMART START™UltraFET â SPM
D4M (6)  This is both the power and analog ground for the IC. Note that both pin t
D4N (14)  MOTO SOP8 00+ N-CHANNEL (Q2, Q3)   Total Gate Charge1   Gate-Source Charge 1
D4P (1)  MOT SMD-8 The ADC122S101 operates with a single supply that can range from +2.7V
D4R (4)  N/A 00+ N/A 4. Design your application so that the product is used within the ranges
D4S (14)  SHINDENGEN 2008+ 1.3.3 Bit-Level Control Bit-level control over many of the microcontroll
D4V (3) 
D-5 (2)  3000 Notes: (1) The Inhibit (pin 3) has an internal pull-up, which if left ope
D5- (1)  The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partit
D50 (45)  INT DIP NOTE: Intersil Pb-free products employ special Pb-free material sets; mol
D51 (48)  PHILIPS QFN-S 6+ The ATF1502ASVs logic structure is designed to efficiently support all ty
D52 (53)  N/A N/A N/A • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew)
D53 (41)  IT 05/06+ The Maximum allowable values of Cx and Rx are a function of leakage of ca
D54 (40)  SMD SMD The D540001 is part of a complete GSM/EDGE receive and transmit chipset.
D55 (75)  NEC 05+ During normal operation, power consumption may be minimized by disabling
D56 (33)  MOT 5.2mm 98 The Red source color device are made with Gallium Arsendide Phosphide Red
D57 (13)  TOSHIBA 05+/06+ Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V
D58 (13)  FAI TO220-3 99+ Hynix HYMD264646B(L)8-M/K/H/L series incorporates SPD(serial presence dete
D59 (10)  CHMC QFP44 2003 There are four (4) high-impedance physical tamper detect input pins, 2
D5A (12)  INTEL DIP   Designed for N- CDMA base station applications with frequencies fr
D5B (1)   CRFree-running conversion rateCS at 0 V668770 conv/s † All t
D5C (53)  INTEL DIP System Considerations The power switching characteristics of Advanced C
D5D (2)  1230   The EFJ2803 is a high reliability EMI filter for use with the DAC
D5F (1)  SHINDE TO- This high speed latch decoder driver utilizes advanced sili- con-gate CM
D5I (1)  99 The negative terminal of the battery pack (negative terminal available to
D5K (2)  TO220 Protect Register Write (PRWRITE) The PRWRITE instruction is used to writ
D5L (7)  SHINDENG TO The Si9986 is available in both standard and lead (Pb)-free, 8-pin SOIC
D5N (6)  MOT SOP8 Do not store the product in the area where temperature exceeds the maximu
D5S (19)  NEW TO-220 02+   The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS F
D5V (2) 
D5W (1)  The NMH series of industrial temperature range DC-DC converters are the
D5X (1)  Solderability: 90% coverage after 5 second dip in 235C solder following
D-6 (3)  N/A N/A 2006+ Overvoltage Sense. When VOUT is greater than 38V (typ), the internal n-ch
D6- (1)  In personal computer (PC) architecture, there are industry-accepted bus s
D60 (37)  DESTINY QFP100 There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877)
D61 (231)  NEC 00+ The ADV7330 has separate 8-bit or 16-bit input ports that accept data in
D62 (66)  NEC QFP 07+ The write enable (WEN) instruction must be executed before any device p
D63 (127)  88 NEC O5 Note 4 For a power supply of 5V g10% the worst case output voltages (VOH a
D64 (260)  N/A N/A N/A The AD581 can be easily connected with power pnp or power Darlington pnp
D65 (380)  When the SVHS mode is selected, the DC restore on the Aux_Cout pin will
D66 (93)  N/A N/A N/A The K9K1G08X0B is a 128M(134,217,728)x8bit NAND Flash Memory with a spare
D67 (34)  CHIPS PLCC 07+ AAL2 mode (ITU-T I.363.2): - Support for up to 16 AAL2   ATM VCCs
D68 (14)  STR SIP 97 Each of the off-chip memory spaces of the ADSP-21991 has a separate cont
D69 (28)  NEC DIP (2) When the receiver will be used as the wire-less remote controller, ple
D6A (1)  2000 LINEARITY   Linearity refers to how well a transducers output follo
D6B (1)  OMRON 04+ SOT-6P Winbonds I1800 ChipCorder® provides high-quality, single chip, single-
D6C (19)  IT 05/06+ 3. Measured by the voltage drop between A and B pins at the indicated cur
D6F (14)  1600 The HY62K(U,V)T08081E is a high-speed, low power and 32,786 X 8-bits CMOS
D6H (1)  AMD 95+ PLCC20 Thaler Corporation has developed a nonlinear compensation network of ther
D6K (1)  The LTC®4055 is a USB power manager and Li-Ion battery charger design
D6L (5)  PI TO-220F   The SMB series is designed to protect voltage sensitive component
D6N (8)  MOT SMD-8 PCI_STP# is an input to the clock generator and is made synchronous to
D6P (3)  N/A N/A N/A Functionally, the ÉlanSC300 microcontroller is a 100% DOS/Windows
D6R (11)  IT 05/06+ NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia
D6S (5)  GULF GBU 2007 This device can be used as two 8-bit transceivers or one 16-bit transceiv
D-7 (4)  ZILOG SOP 03+ Note 6: Junction-to-ambient thermal resistance (JA) is taken from a therm
D7. (1)  NEC 1W-7.5V 04+ • EP2, 4, 6, 8CEight 512-byte buffers, bulk, interrupt, or iso- &n
D70 (410)  NEC In order to increase the adjustment range of VCO3 with fixed external tan
D71 (152)  PLCC 05+ The LP2950 and LP2951 are micropower voltage regulators with very low q
D72 (224)  NEC 00+   The PT6440 Excalibur™ power modules are a series of high per
D73 (57)  NEC DIP40 2000 An integrated soft-start feature brings all outputs into regulation in a
D74 (138)  NEC SOP 05/06+
D75 (588)  NEC QFP 95+ • 22 I/O pins with individual direction control • High curre
D76 (48)  QFP 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD
D77 (143)  NEC 99+ SOP-24 The FDC05 and FDC05-W series offer 5 watts of output power from a 2 x 1 x
D78 (648)  NEC QFP 0051 1) Worst case package. 2) Max number of outputs defined as (n). Data in
D79 (16)  NEC SOP 04+ Set VDD above the start threshold before setting at 9V. Does not includ
D7A (3)  The Philips SA56004X is an SMBus compatible, 11-bit remote/local digital
D7C (2)  NOTES: (1) For detailed drawing and dimension table, please see end of da
D7E (6)  IBM 01+ Mono-channel multi-level D/A converter High performance analog characteri
D7H (6)  MOT 2003 BGA TOP BOOT SECTOR LOCK: When the TBL pin is held low, program and erase ope
D7K (1)  HIT 03+ QFP NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale
D7M (1)  SIEMENS 08+   solution to be used worldwide • Superior alternative to ca
D7N (11)  MOT 06+ 647 Table 4 shows ACEX 1K device performance for some common designs. All pe
D7O (1)  63 NEC O4 NOTES: (1) Long-Term Input Offset Voltage Stability refers to the average
D7P (1)  Freescale BGA 2007 DMS (Data Management Software) allows systems to easily take advantage o
D7S (1)  88 The 56800E core is based on a Harvard-style architecture consisting of th
D-8 (5)  hot sell DIP40P 79 CAUTION: Stresses above those listed in Absolute Maximum Ratings may caus
D80 (306)  INTEL DIP 06+ The Hynix Low Power SDRAM is suited for non-PC application which use the
D81 (68)  ON SOP-16 04+ The CKE input determines whether the CLK input is enabled. The next ris
D82 (414)  INT/NEC CDIP CDIP   The 556C/W for the SOTC23 package assumes the use of the recommen
D83 (29)  TO-3PF Operating Voltage Range Sleep Mode Supply Current Supply Current (Ave
D84 (40)  BGA Figure 1 shows a block diagram of the 80C186EB 80C188EB The Execution Un
D85 (62)  PAN TO-3P DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -
D86 (7)  The D86316F2-011 is a member of Atmels family of 4-bit single-chip microc
D87 (123)  INTEL DIP 0105+ The noise of Q1A and Q1B would normally be quite signifi- cant about 6 n
D88 (46)  NEC TRI-STATE is a registered trademark of National Semiconductor Corporation
D89 (15)  93 A picture signal with reduced noise and cross-color appears on the output
D8B (1)  OMRON   Figure 4 illustrates the differential or gauge configuration in t
D8C (1)  The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microco
D8L (11)  04+ During the clamping operation, the input video signal is passed through t
D8M (1)  1) CPD is defined as the value of the ICs internal equivalent capacitance
D8O (4)  INTEL DIP 03+ ANALOG I/O   8-Channel, 400kSPS High Accuracy, 12-Bit ADC   O
D8P (1)  INTERSIL TO252 2002 1 Undervoltage sensors causes each channel to switch off and reset. 2 Ove
D8R (2)  06+ SOP-5   This device contains protection circuitry to guard against damag
D8T (1)  2. The ADS-929 achieves its specified accuracies without the   need
D9- (3)  The IC requires only a common inexpensive capacitor in order to function.
D90 (34)  DESTINY Above +125C case temperature, derate output power linearly to 0 at 135C c
D91 (19)  NEC PLCC 07+   the part number LM26CIM5-TPA has TOS = 85˚C, and programmed a
D92 (18)  FUJI TO-3P 05+ In addition, the device has on-chip error detection and correction circ
D93 (36)  INTEL DIP First of all, use the largest supply voltage available (15V or +30V is c
D94 (8)  NEC QFP160 The ThinPakTM Package is a perforated, metalized ceramic substrate attac
D95 (11)  NEC QFP160 • 64-bit Password Security • One Array (112 Bytes) Two Passwo
D96 (27)  NEC 00+ TQFP-M144P Members of the Texas Instruments SCOPE™ Family of Testability Produ
D97 (32)  Electrically-insulating, thermally-conductive "pads" may be in
D98 (67)  QFP48 Guaranteed 1% output voltage tolerance (LM317A) Guaranteed max. 0.01%/V
D99 (21)  NEC PLCC 00+ Features • Improved Accuracy at High Temperature • Available
D9A (2)  NEC 12PIN-TO5 08+ 6. Maximum package power dissipation limits must be observed. 7. Tested
D9B (1)  The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core cloc
D9C (3)  MT RESET (RS)   Reset is accomplished whenever the Reset (RS) input is
D9D (1)  MICRON BGA 05+ only, and functional operation of the device at these or any other conditi
D9F (3)  170 MT 05+ Specifications of any and all SANYO products described or contained herei
D9G (2)  MT BGA 06+ The 163CMQ isolated center tap Schottky rectifier module series has been
D9H (1)  Function Charge Pump Ground. The ground return path of the charge pump.
D9P (3)  INTERSIL When the output enable (OE) input is high, both the A and B ports are pla
D-A (3)  SMC The D-A93C is used in conjunction with level-shifting devices such as t
DA- (41)  AD The Texas Instruments MSP430 family of ultralow-power microcontrollers co
DA0 (34)  N/A DIP-8L 00+ The 5-volt device is fully accessible and data can be written and read on
DA1 (225)  ROHM SOT-523 05+ HT1625 make it suitable for multiple LCD applications including LCD modul
DA2 (127)  INTEL TSOP 98+/03+
DA3 (26)  D&A 05+ Note 1: Performance from application circuit shown in Figures 3 - 5 guara
DA4 (27)  PAN QFP-48 4 channel 10-bit resolution A/D conversion time : 15.2 µs (MB899
DA5 (34)  ittcann ittcann dc80+ The bq2019 works with the host controller in the portable system to imple
DA6 (6)  DSI n/a The voltage drop (VSR) across the sense re- sistor RS is monitored and i
DA7 (29)  TDA SOP-8   2.1 General. The documents listed in this section are specified in
DA8 (38)  PHILPS SOP 03/+04+ At any time, the FIFO can be reset to an empty state by putting the ADS
DA9 (19)  N/A SSOP Collector-to-Emitter Voltage Continuous Collector Current Continuous
DAA (12)  SOP16 03+ Disclaimer: Atmel Corporation makes no warranty for the use of its product
DAB (5)  MSOP 02+ The CY22050 is programmed at the package level, i.e., in a programmer soc
DAC (2902)  NS DIP Hynix HYMD212G726A(L)S4-M/K/H/L series incorporates SPD(serial presence de
DAD (6)  TI QFP-80 00+ also allows power consumption to be reduced by leaving the separate VEE
DAE (7)  01+ The bq4802Y/bq4802LY provides direct connections for a 32.768-kHz quart
DAF (13)  MICROCHIP 08+PBF 2µs Settling to 0.0015% for 10V Step 1LSB Max DNL and INL Over Indu
DAG (7)  SANYO 05+ * If the inductive load is driven near steady state conditions,   a
DAH (3)  SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This fea
DAI (16)  PHIL SMD 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continu
DAJ (4)  On the subsequent clock rise the data lines are automatically three-state
DAK (13)  Power 08+ The internal VCO is based on the TLC2932 and TLC2933s ring oscillator. It
DAL (82)  N/A PLCC N/A AMD MirrorBit flash technology combines years of Flash memory manufactu
DAM (72)  cinch cinch dc80+ Unless otherwise specified, the following specifications apply for AGND =
DAN (113)  ROHM 07/08+ New B6HF bipolar techology, 25 GHz fT Reduced external components Freq
DAO (2)  D CDIP CDIP Enhanced Word Spotting capability (10 SI or 4 SD words) in parallel Nois
DAP (155)  ST Input Voltage Noise Non-Inverting Input Current Noise Inverting Input
DAQ (3)  Information relating to products and services furnished herein by Zarlink
DAR (4)  N/A SOT89 08+ Collector Emitter Breakdown Voltage Collector Emitter Breakdown Voltage
DAS (61)  ST Each ADC includes a front-end analog multiplexer followed by a Sample and
DAT (51)  DATEL SOP16 03+ Note: 1. Stresses greater than those listed under "Absolute Maximum
DAU (3)   Noise bypass Capacitance Cp Noise bypass capacitance Cp reduces noi
DAV (14)  ST 08+ 90% Efficiency at 20W Frequency to 600kHz 30W output at 22Vin 2.4V to 2
DAW (3)  INTERSIL SOP-8P 07+ 5.2.4 Control of Transceiver Chip The ST20196 runs the firmware controll
DB- (43)  SUNM SOT23-8 97+
DB0 (7)  (*) Our SO-8 package used for Voltage Regulators is modified internally t
DB1 (133)  SEMIKRON SOP In addition, the XC7300 architecture employs the Univer- sal Interconnec
DB2 (85)  T The Hyundai HYM72V16M636AT6 Series are 16Mx64bits Synchronous DRAM Modules
DB3 (24)  N/A TSSOP-10 2004 The DB3BBDCDB3BBD device has Power-on Reset, selectable Watchdog Timer, s
DB4 (8)  ST 05+ The Simtek STK12C68 is a fast static RAM with a nonvolatile, electrical
DB5 (17)  FCI 08+ Maximum ratings are DC values beyond which the device may be damaged or h
DB6 (3)  The two PWM controllers that regulate the system main 5V and 3.3V voltag
DB7 (4)  SMD USA 05+   Two Channel Coupler   SOIC-8A Surface Mountable Package &nbs
DB8 (16)  DIP 2007+ DESCRIPTION Power input pins for VCC operate mode. 2.8 to 5.5 volts opera
DB9 (14)  n/a N/A RFT6120 Device Features • CDMA2000 1X Mobile Station Modem chipset
DBA (20)  MODULE MODULE 08+ NOTES:   Stresses above those listed under Absolute Maximum Ratings
DBB (39)  EUPEC Due to their tiny size and low power consumption, these microcontrollers
DBC (20)  23 Note 1: TA=25C unless otherwise specified. Note 2: ESD applied to input
DBD (2)  Eupec f/sDIO   The LX1910 PWM buck regulator achieves very high efficiencies ove
DBE (4)  PLCC IMP 03+ In a slow mode, the conversion is completed before the serial I/O CLOCK d
DBF (25)  ittcann ittcann dc72+ ESD damage can range from subtle performance degradation to complete dev
DBG (2)  Absolute Maximum Ratings are stress ratings only. Permanent damage to the
DBI (4)  MODULE MODULE 08+ Specifications are production tested at TA =25C. Specifications over the -
DBJ (6)  N/A   To remove this residual error, Thaler Corporation has developed a
DBK (3)    The RST pin is normally driven high and will be clocked low when
DBL (150)  DAEWOO 2008 NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu
DBM (60)  HITACHI 06+ 6.2 ST20196 FEATURES DMT modulation Max. number of bit per tone: 15 b
DBN (2)  N/A N/A N/A odcOutput Duty Cycle4753 All parameters measured at fMAX unless noted o
DBP (11)  FCI 08+ The MAX104's T/H amplifier input circuit design reduces the input signal
DBR (2)  IAC: (current proportional to input voltage) This input to the analog mul
DBS (45)  − Conforms to USB specification Rev. 1.1 − Supports 1 devic
DBT (19)  MINI 08+ Atmel Colorado Springs, USA Atmel Nantes, France Atmel Colorado Springs,
DBU (9)  IT 05/06+ Note: Stresses greater than those listed under MAXIMUM RATINGS may caus
DBV (1)  Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
DBW (3)  ITT SOP   All inputs and outputs are ESD and short circuit protected making
DBX (6)  C&D Technologies (NCL) Limited reserve the right to alter or improve
DBZ (1)  0 TSSOP During the pre-equalizing, vertical sync and post equalizing periods, com
DC- (78)  99 7KLV GRFXPHQW VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV UHJDUGLQJ WKH 6
DC/ (2)  TI 07+ The appropriate converters must be ordered to take advantage of this fe
DC0 (47)  2000 • Input Voltage Range:   36V to 75V • 1500 VDC Isolatio
DC1 (149)  digital BGA RoHS revision 13.2.2003. Glass and High Temperature Solder Exemptions App
DC2 (47)  07+  Lead Temperature 1.6mm (1/16 inch) from Case for 10s260C (1) Stres
DC3 (53)  FOX NOTE: EP circuits are designed to meet the DC specifications shown in the
DC4 (28)  Figure 3 describes the noise model for the non-inverting amplifier conf
DC5 (17)  DIAMOND SOP16W 2007+   Dimensions   InchesMillimeters  MinMaxMinMax .178.195
DC6 (16)  NULL N/A Notes: 1. These ratings are limiting values above which the serviceabilit
DC7 (14)  NEC DIP N/A output selectable). On-chip RAM performs buffering for EFM demodulation
DC8 (15)  ST QFP 07+ These synchronous, presettable counters feature an internal carry look-
DC9 (12)  CTIS SSOP24 07+   The LSTTL / MSI SN54 / 74LS257B and the SN54 / 74LS258B are Quad
DCA (54)  SANYO SOT-23 The TPS758xx family of 3-A low dropout (LDO) regulators contains four f
DCB (23)  SANYO SOT-23 FEATURES Faults detected on 7 independent supplies • 1 High Volta
DCC (10)  SANYO SOT-23 A typical interface circuit using the SPT1018 in a color raster applicat
DCD (20)  SANYO S0T-23 05+ The CM8560 is a low cost linear regulator designed to provide a desired o
DCE (14)  SAMPO TQFP 00+ The AVR core combines a rich instruction set with 32 general purpose work
DCF (25)  SANYO SOT-323 05+ This product paves the way for a smaller, lighter, easier to produce,
DCG (15)  SANYO SOT-323 05+ Analog Ground. All input signals and the VDD supply voltage must be refe
DCH (50)  BB/TI SIP The 16-bit digital output is multiplexed into an 8-bit output word that
DCI (2)  ST 01+ SOP8 Voice signals can be fed into the chip through two independent paths: a di
DCJ (11)  SANYO 05+ The LM34 series are precision integrated-circuit tempera- ture sensors w
DCK (1)  ELNA STANDARD DEFINITION MODE   Hue Accuracy   Color Saturation Acc
DCL (2)  A flow-through pinout has been adopted to allow simple PCB routing and
DCM (63)  ittcann ittcann dc68+ The availability of the bias current terminal, IABC , allows the device
DCN (2)  96 Each channel has a request bit associated with it in the 4-bit Request re
DCO (4)  N/A SOP 07+ Over a Dynamic Range 1000 to 1 Over a Dynamic Range 1000 to 1 Over a Dyn
DCP (178)  BB/TI SOP 1.2MHz Switching Frequency Low VCESAT Switches: 330mV at 1.3A High Outpu
DCQ (3)  48 AMIS The MAX 3000A architecture supports 100% transistor-to-transistor logic
DCR (124)  BB SMD 00+ The basic unit of logic on these devices is the Generic Logic Block (GL
DCS (60)  TAISEI • Bidirectional data strobe(DQS) • Differential clock inputs(
DCT (32)  bey bey dc00 This pin connects directly to the rectified AC line voltage source. At sta
DCU (43)  Jack(Available) Hynix HYMD216M726(L)6-K/H/L series incorporates SPD(serial presence detect
DCV (44)  BB DIP-7 07+ In case of a brownout or power failure, it may be necessary to preserve t
DCW (20)  4200 No Option and Option 300 contain 50 units (HCPL-7710), 100 units (HCPL-071
DCX (18)  IDE SOT-363 05+   Two independent DMA channels   Programmable interrupt contr
DCZ (4)  TDK DIP-16 07+/08+ Sustaining a more acceptable gain with an output in direct relation to
DD- (16)  DDC The DD-00429FP-200 is a stereo audio power amplifier in a 24-pin TSSOP th
DD( (6)  Operation at 500kHz allows the use of small magnetics and output capacito
DD/ (12)  The IL400 is an optically coupled SCR with a gallium arsenide infrared
DD0 (67)  QFN 05+   : the number for special module.: the number of CR (Control Regist
DD1 (261)  N/A FEATURES Single-Supply Operation: 7 V to 16 V Dual-Supply Operation: 3.
DD2 (168)  MODULE MODULE 08+ Maximum ratings are those values beyond which device damage can occur. M
DD3 (52)  100 天龙伟业 靳先生 (1) Lead Forming   When forming leads, the leads should be bent at
DD4 (52)  N/A It also provides the non-volatility of Flash without any requirement fo
DD5 (67)  . TO-220-3 The host system can detect whether a program or erase operation is compl
DD6 (55)  This example program is a function written in generic C. So it should wor
DD7 (29)  PARAMETER Reference Voltage Section Fb Voltage Fb Voltage Line Regulati
DD8 (57)  If a location is being written to by one port and the opposite port attem
DD9 (42)  MODULE MODULE 08+ DYNAMIC PERFORMANCE  Signal to Noise + Distortion (SINAD)2  Si
DDA (9)  DIODES SOT-363 04+ 1) CPD is defined as the value of the ICs internal equivalent capacitance
DDB (118)  04+ Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial
DDC (57)  ST SOP-16   Please be aware that an important notice concerning availability,
DDD (4)  05+ SOP-20 • Low On-Resistance (33Ω typ) Minimizes Distortion and  
DDE (2) 
DDF (3)  05+ For self biased off-line applications, -2 and -4 versions (UVLO on and
DDG (3)  Hitachi The SiP41109/41110 enters shutdown mode when the signal driving PWM ent
DDH (1)  Drain-to-Source Breakdown Voltage-200 Gate Threshold Voltage-2.0 Gate-
DDK (1)  efficiency minimizes the requirement for heat-sinking and the low output
DDL (1)  2 QFP   At startup, C2 is charged through the startup resistor RS. When
DDM (21)  ittcann ittcann dc67+   Referring to the Functional Block Diagram, the RF input stage is a
DDN (1)  N/A NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
DDO (1)  Absolute maximum ratings indicate sustained limits beyond which damage to
DDP (37)  GINGER DIP-28P Note 2: Absolute Maximum Ratings indicate limits beyond which damage to th
DDR (22)  02+ FEATURES Operates over entire Li+ Battery range Interoperable with EIA
DDS (3)  NS SMD-16 00+ Ÿ Fast page mode operation Ÿ Read-modify-write Capability &#
DDT (133)  DIODES 05+PB2500
DDU (27)  模块8 9003+ +REG IN - is the input pin for applying power to the internal +15V regul
DDV (1)  Integrates 10BASE-T Transceiver Functions: -Driver and Receiver -Link I
DDX (40)  ST SSOP36 04+ The CAT661 can replace the MAX660 and the LTC660 in applications where
DDY (3)  N/A N/A N/A 1.) When operated within the SAFE OPERATING AREA as defined by the above
DDZ (59)  DIODES 06+ 25 mV (or less) For normal line resistances data may be recovered from l
DE- (24)  DELTA BGA Regular supply bypassing techniques are recommended. A 10µF capaci
DE0 (144)  96 *Stresses above those listed under Absolute Maximum Ratings may cause per
DE1 (160)  MURATA Blackfin processors do not define a separate I/O space. All resources ar
DE2 (82)  SEEQ DIP AC97 3D audio controller Supports Serial ATA controller Fast PCI ATA/33/
DE3 (14)  TI TSSOP 07+ • Cambie las pilas del control remoto cuando el   televisor co
DE4 (8)  DEC n/a 99 • Flame retardant encapsulant (UL 94V-0). • Completely encaps
DE5 (83)  DSP 0626 MISCELLANEOUS PERFORMANCE  input capacitance  input resistance
DE6 (7)  CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick
DE7 (24)  ADI 4 SOT23-5 The MAXQ3120 microcontroller is a high-performance, 16-bit microcontrolle
DE8 (6)  Diagonal 4.5mm (Type 1/4) 510 (H) 492 (V) approx. 250K pixels 537 (H
DE9 (31)  LMD is the last measured discharge capacity of the battery. On initializa
DEA (67)  N/A WRITE PROTECT: When the WP pin is low, program and erase operations to al
DEB (55)  MURATA The LCX240 is an inverting octal buffer and line driver designed to be
DEC (138)  MOT 86+ DIP16陶瓷 The XTO is a one-pin oscillator that operates at the series resonance of
DEE (5)  • Scanner/Printer Stepper Motor Control   − Four outputs
DEF (2)  DESCRIPTION The SLIC KIT (L3000N/L3092) is a set of solid state devices
DEG (1) 
DEH (32)  MURATA The transmitter accepts CMOS logic level clock (TCLK), positive data (TPO
DEI (21)  N/A 00+ PLCC-44   When using the internal oscillator, the stability may be enhanced
DEJ (5)  SAMSUNG MQFP-144P 2000 Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Bu
DEK (10)  VIN = 2V VIN = 2V VFBx = 1.4V, VLFB > VBRT C 0.1V VFBx = 1.4V, VLF
DEL (53)  99 enable ( WE ), and output enable ( OE )control normal read and write ope
DEM (195)  Freescale/Motorola 07+ The ISD1000A ChipCorder Series devices are designed to Record and Play ba
DEN (10)  06+ Reduced Threshold Voltages for LVTTL on Control Pine ♦ Eliminates
DEO (2)  NOTES:   1. Dimensions are in inches.   2. Metric equivalents
DEP (13)  NOTES:  1. Dimension are in inches.  2. Metric equivalents are
DES (15)  INTEL BGA The DES1101AA represents a marked improvement over the previous generatio
DET (10)  N/A NSC 04+ As the battery accepts charge and approaches the pro- grammed voltage, th
DEU (4)  The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK UHF transmitter designe
DEV (11)  SOP14 06+ The TC650/TC651 are integrated temperature sensors and brushless DC fan
DEW (3)  Data flow in each direction is controlled by output-enable (OEAB and OEBA
DEX (2)  Sii QFP- 07+/08+ 1. Package devices (8-pin SOP) have designation SM5009S. 2. The recommend
DEY (1)  SEEQ 1678 Note 1: The Absolute Maximum Ratings are those values beyond which the sa
D-F (3)  phoenlx 436 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
DF- (9)  N/A need very low flicker noise. The HSMS-285x is a family of zero bias de
DF0 (119)  GS 05/06+ Snubbers are employed to protect the output MOSFETs from inductive transi
DF1 (517)  SANREX OFFSET VOLTAGE, initial OFFSET VOLTAGE, vs. temperature OFFSET VOLTAGE
DF2 (307)  SANREX 04+ 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources)
DF3 (330)  N/A N/A N/A
DF4 (31)  B. Failure Rate Prediction The failure rate will depend on the junction
DF5 (38)  TOSHIBA 07+/08+ The advanced and highly flexible digital output interface enables perfor
DF6 (51)  1735 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
DF7 (68)  The value of Ki may also be slightly different at the extremes of the
DF8 (7)  ITT DIP   This is a diagram of a typical application of the MSK 4220. The d
DF9 (49)  HRS 07+ Note The Absolute Maximum Ratings are those values beyond which the safet
DFA (70)  SanRex SOP The SP304 is an enhanced-performance version of the Sipex SP302 RS-232 an
DFB (6)  Delta 07+ 50000 The load specifications for each model of the DFBM-CS224 series gives bo
DFC (227)  MURATA SOT 05+nopb   To remove this residual error, Thaler Corporation has developed a
DFD (19)  TOSHIBA Video input data and controls may be directly connected to the SPT1018.
DFE (7)  deutsch deutsch dc84+   The 370C/W assumes the use of the recommended foot- print on a gl
DFF (4)  DI TO-220F 07+ The two banks have their own dedicated frequency select pins and can be
DFG (1)  Hitachi Members of the Texas Instruments Widebus ™ Family Inputs Are TTL-Vo
DFH (15)  TOSHIBA The A64 device also has an external clock prescaler (ECP) module that, wh
DFI (4)  rca rca dc85+ • Single 3.0 V read, program, and erase   Minimizes system lev
DFK (19)  EMKO 01+ The DFK08R1765A1855G03 is powered by a single 3.3-V supply. The core volt
DFL (34)  DIODES 06+ The SoftStart charge eases batteries into the fast charge stage by gradual
DFM (39)  DYNEX SOP 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (
DFN (13)  fordahl fordahl dc00 The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36 and 524,288 x 18 SRA
DFP (18)  DI SEMICONDUCTOR 2005 The TL750L, TL751L series are low-dropout regulators. This means that cap
DFR (3)  SAMSUNG 01+   Output skew with respect to the REF input is adjustable to compens
DFS (6)  99 (*) CPD is defined as the value of the ICs internal equivalent capacitanc
DFT (10)  si si dc85+ TxDAC AC CHARACTERISTICS   Fundamental   Signal-to-Noise and D
DFU (2)  DI TO-251 07+ The 153CMQ isolated, center tap Schottky rectifier module series has be
DFV (9) 
DFW (1)  • 100,000 erase/write cycle Enhanced Flash   program memory t
DFX (20)  SAMSUNG 2001 NOTES: 1. Timings referenced as in AC Test Conditions. 2. Industrial tem
DFY (68)  N/A N/A N/A tPHZPropagation delay time, high-level-to-high-impedance output tPLZProp
DFZ (2)  PARTRON SOT 04+ The AD7734 analog front end features four single-ended input channels wi
DG- (4) 
DG0 (18)  SHINDENGEN SOT-123 05+PB Steering Input/Guard time (Output) Bidirectional. A voltage greater than
DG1 (214)  INTERSIL 04+ RF output and bias pin. Bias should be supplied to this pin through an
DG2 (410)  advantage series SOP original stock Write accesses are initiated when the following conditions are satisfied
DG3 (300)  INTERSIL CAN10 Table 1. Bluetooth Mini module interface definitions   Pin#NameTypeN
DG4 (595)  SILICONIX DIP-16 05+ STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions
DG5 (320)  SILICONIX DIP All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.6
DG6 (74)  VISHAY SOIC-16 07+ Handsets and Telecommunications Applications Two Differential Microphone
DG7 (12)  MAXIM N/A N/A An active bias circuit can be implemented if the user does not wish to sa
DG8 (13)  DIP   The Samsung M390S2858DT1 is a 128M bit x 72 Synchro- nous Dynamic
DG9 (62)  Ns SMD-8 96+ Baseline JPEG Compression/Decompression Image Resize Engine 16-bit YC Di
DGA (58)  DAEWOO 2008 Thermal Ground FBAR resonators have a negative temperature coefficient o
DGB (1)  The LTC®6900 is a precision, low power oscillator that is easy to us
DGC (5)  ST QFP 99 1.Computer terminals. 2.Registers,copiers,automatic vending machines.
DGD (2)  SONY 05+ Melexis Inc. reserves the right to make changes without further notice to
DGE (1)  The DDX-2100 surface mount package includes an exposed thermal pad on the
DGG (2)  DAEWOO 06+ PLCC-68 2. JC is measured in free air with the component mounted on a high effect
DGH (2)  DSP QFP 04+ SRAM. The DM9601 has interfaces to the UTP3, 4, 5 in 10Base-T and UTP5 in
DGL (2)  DDC The only write enable when device is configured to have programmable flags
DGM (9)  AD 模块 模块 Current-controlled Output Current Source with 5 Input Channels 2 Selectab
DGN (1)  MOT SOP8 N/A † All characteristics are measured under open-loop conditions with
DGO (2)  SHINDENGEN SOD-123 04+ Under normal start-up conditions, devices will not begin to regulate until
DGP (19)  N/A POWER ONE 04+ Typicals and limits appearing in plain type apply for TA = TJ = +25˚
DGS (17)  IXYS TO-263AB (D2 PAK) 08+ • Second Generation SuperWIDE HIGH DENSITY   IN-SYSTEM PROGRAM
DGT (13)  ALCATEL PQFP-100 99
DGV (1)  SI SMD N/A • CLK: with each cycle of this signal a one-bit transfer on the comm
DGY (1)  SI 06+ The negative terminal of the battery pack (negative terminal available to
DH- (6)  SUNMULON 1. Test conditions: T = 25º C, Supply Voltage = +5 V, Device Voltage
DH0 (48)  PHILIPS SOP Hook Switch. The OFFHK input is used to control the on-hook and off-hook
DH1 (43)  NEC 2003 6SDQVLRQŒ )ODVK PHPRU\ SURGXFWV FRPELQH \HDUV RI )ODVK PHPRU\ PDQXID
DH2 (17)  DSP 05+ QFN • Synchronous Operation. • On-Chip Address Counter. •
DH3 (42)  DSP QFP 0714+ The Hynix HYM71V16C735AT8 Series are 16Mx72bits ECC Synchronous DRAM Modul
DH4 (13)  SON QFP N/A Notes: 3. Derate linearly as shown in Figure 4. 4. Drive currents betw
DH5 (9)  TEMEX 805 06+ The HA-5020 features low differential gain and phase and will drive two d
DH6 (5)  IXYS TO-247AD 08+ Notes:  1. PD indicates an internal pull-down and PU indicates an i
DH7 (11)  DH DIP 07+ The ADSP-21365/6 contains three megabits of internal SRAM and four megab
DH8 (5)  N/A The logic control inputs can be driven up to +3.6V regardless of the supp
DH9 (2)  FEATURES Faults detected on 7 independent supplies • 1 High Volta
DHA (4)  The receive (RX) section of the CYP(V)15G0401DXB Quad HOTLink II consists
DHB (4)  1. One output at a time for a maximum duration of one second. VOUT = 0.5V
DHC (6)  SIL 04+ Note 1: Absolute maximum ratings are the extreme limits that the device wi
DHD (5)  COSEL Designed to meet the the derating requirements of MIL- STD-975 and manu
DHE (5)  DHE PLCC 07+ BOOT BLOCK LOCKOUT DETECTION: A software method is available to determin
DHI (2)  N/A QFP 07+ Video input data and controls may be directly connected to the SPT1018.
DHJ (1)  The Hitachi HM5112805F, HM5113805F are 128M-bit dynamic RAMs organized as
DHM (2)  HITACHI CDMA balanced input pin. This pin is internally DC-biased and should be
DHP (8)  DANAM 模块 N/A The circuit accommodates any type of LBO output (active high or active low
DHR (10)  N/A SOP 07+ The CM3004 is supplied in a space-saving, 8-lead power SOIC package whi
DHS (19)  Infineon The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive re
DHT (4)  N/A DIP 07+ The analog input range is equal to a 2V spread. The voltage on VT-VB wi
DHX (1)  Reading from the device is accomplished by taking Chip En- able 1 (CE1)
DHY (1)  The maximum power that can be safely dissipated by the AD8021 is limited
DHZ (1)  • DLL aligns DQ and DQS transitions with CK   transitions 
DI- (20)  100 SOP 00+   SymbolParameter Input Characteristics   IIHInput HIGH Curren
DI/ (1)  AMIS The HY51V(S)17400HG/HGL is the new generation dynamic RAM organized 4,194,
DI0 (7)  SOT-23 94+ nection to a separate SNAPHAT housing contain- ing the battery. The uni
DI1 (22)  PANJIT 07+ Maximum ratings are those values beyond which device damage can occur. Ma
DI2 (3)  ? SIP3 —— Note 1: Calculated by measuring the combined oscillator and prescaler supp
DI3 (3)  2008 • Rated isolation voltage (RMS includes DC)   VIOWM = 1000 VR
DI4 (4)  DI SOP28 03+ Note A: Characteristic data has been developed from actual products teste
DI5 (2)  7. The CH1817 DAA as is meets or exceeds the   hazardousvoltage,surg
DI6 (12)  HARRIS DIP DESCRIPTION The M74HC123 is an high speed CMOS MONOSTABLE MULTIVIBRATO
DI8 (7)  4. EMI/RFI Suppression.   The capacitor/ inductor network should be
DI9 (14)  DIODES Power Diode Module FDF60BA is designed for single phase full wave rectifi
DIA (10)  DALLAS  Maximum ratings are those values beyond which device damage can occ
DIB (21)  DIBCOM 08+ Maximum output deviation is 10% inclusive of trim. If remote sense is not
DIC (30)  DIC DIP-32 07+/08+ 4. ALC   The ALC block controls the exposure electronically by inpu
DID (4)  MOT SOP 07+ Notes: 1. Minimum Noise Figure and Associated Gain at Fmin computed from
DIE (3)  A/N SOP-8 02 − Provide software confirmation of completion   of program or
DIG (26)  N/A DIP-8 03+ DIG-1208-010 supports either the interleaved burst sequence used by the I
DII (4)  91 TEMPERATURE COMPENSATION   Figure 2 shows the typical output charac
DIL (28)  meder meder dc90 Several features have been designed in for added value. A thermal overlo
DIM (107)  DYNEX SOP Up to 16 serial input and output streams Maximum 2,048 x 2,048 channel no
DIN (30)  AD 06+/07+ The ADR39x family of micropower, low dropout voltage references provides
DIO (5)  commtech commtech dc02 Timer counter 3 : 8-bit 1 (square-wave output, event count, generation o
DIP (118)    SymbolParameterRatingUnitRemark VIN, VOUTInput/Output Voltage-0.3
DIR (12)    MAX6323_UT__-T -40C to +125C 6 SOT23-6 Push-Pull   MAX6324_UT
DIS (15)  TI This is an input pin to the device and is generated by the master that i
DIT (17)  N/A 275   Output Drive Capability: 10 LSTTL Loads   Outputs Directly In
DIU (1)  SEP/PEC/HY/HA 桥堆 07/环保 Temperature-30+70C Supply Voltage2.73.03.6V Transmit Current506880mA Re
DIV (3)  BB N/A N/A   Operation of the circuit is straight-forward. The motor advances
DIX (5)  TI 07+ The Intersil HS-26C32RH is a differential line receiver designed for di
DJ- (6)  ???? When operated in its default mode, the sensor gener- ates a VGA image at
DJ0 (4)  RXD_0[1:0] RXD_1[1:0] RXD_2[1:0] RXD_3[1:0] RXD_4[1:0] RXD_5[1:0] RX
DJ1 (7)  N/A N/A "Advance" product information describes products that are in de
DJ2 (4)  SOP 03/+04+   FIFO status flags monitor the extent to which each FIFO buffer h
DJ3 (13)  A simple LC noise reduction filter (L5 and C7) is connected between pin
DJ4 (1)  DESCRIPTION The LE00 regulator series are very Low Drop regulators ava
DJ5 (1)  The chroma input is driven by a low impedance source of 0.7VP-P or the o
DJ6 (1)  DESCRIPTION The VN920PEP is a monolithic device designed in STMicroelec
DJ8 (7)  ASTEC MODULE N/A   Controller (host) sends a start bit.   Controller (host) send
DJA (6)  DN 07+ SymbolItem   IDRMRepetitive Peak Off-State Current, max.   IR
DJB (1)  DJBx ON SOT23-6 over 2000 volts can accumulate on the human body or asso- ciated test eq
DJC (4)  ON 02+ Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence o
DJD (1)  The Multi-Input Wake-Up (MIWU) feature is used to return (wake-up) the
DJE (1)  AMPHENOL 06+ The DJE30-D88-13100 is an npn silicon planar epitaxial transistor, inte
DJH (2)  djh djh dc98   Read the contents of the Data Register pointed to   by R1CR0
DJK (1)  The LT1013C, LT1013AC, and LT1013D are characterized for operation from 0
DJL (42)  INTEL QFP 1. In Figure 1, test circuit electrolytic capacitors C1 and C2 are 100&mi
DJM (1)  Notes: 1. Absolute maximum ratings are limits beyond which operation may
DJN (1)  AD 06+/07+ Pb−Free Packages are Available Small Compact Surface Mountable Pac
DJS (3)  The transmit path interpolation filter provides an upsampling factor of
DJT (3)  DAEJIN 04+ *: The capacity of the built-in capacitor is 208 pF by standard.  
DJV (1)  The ISL6522 provides simple, single feedback loop, voltage- mode control
DK- (19)  SANYO 2008 The low (3.5pF) input capacitance makes this part useable for applicatio
DK0 (7)  Negative chip select, when at a low level allows normal read or write ope
DK1 (43)  FINE 05+
DK2 (20)  AMIS The stress on Q1 under load is related to the output current and the volt
DK3 (7)  N/A DIP 07+  Antenna driver current is dimensioned, so as to guarantee that for
DK4 (4)  ST 08+ ISSI reserves the right to make changes to its products at any time witho
DK5 (4)  TO-92 The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O toleran
DK6 (9)  . 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources)
DK7 (3)  TI SOP16 04+ These BCD-to-decimal decoders drivers consist of eight in- verters and t
DK8 (1)  The CLC425's combination of ultra-low noise, wide gain-band- width, high
DK9 (5)  Note 1: Supply current, output power, and efficiency are greatly dependent
DKA (7)  MOT The Rambus RIMM modules are offered in a 184-pad 1 mm edge connector pad
DKB (4)  FAIRCHILD 06+ ance state. The output control does not affect the in- ternal operation
DKD (2)    The g-cell beams form two back-to-back capacitors (Figure 2). As
DKE (5)  † Stresses beyond those listed under absolute maximum ratings may c
DKF (10)  NEC DIP-16 08+ The DS1265 devices execute a write cycle whenever WE and CE signals are ac
DKH (4)  DSP QFP 03+ The OPA860 is a versatile monolithic component designed for wide-bandwi
DKL (5)  National Semiconductor DIP-16 07+/08+  IGSSGate-to-Source Leakage Forward  I GSSGate-to-Source Leakag
DKM (1)  These Intersil RS-485/RS-422 devices are ESD protected, fractional unit l
DKN (2)  ALT This can be a problem if RXDATA is driving a circuit that must sleep when
DKO (3)  TOSHIBA Q1 through Q4 and also additional external output transistors can be prote
DKR (15)  100 天龙伟业 靳先生 During the turn−on and turn−off delay times, gate current is
DKS (5)  The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve hig
DKT (3)  FREESCALE O7+ SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operat
DKV (3)  N/A MOT 04+   The SY100EP57V is a high-speed, low-skew, fully differential PEC
DKW (1) 
DL- (36)  289 SANYO 01+   Resolution10 Bits   Conversion Rate40 MSPS   ENOB9.4 Bi
DL0 (34)  83 Highly Integrated Solution to Reduce Components Integrated 50-V Power Sw
DL1 (161)  98+99+ QFP-128P
DL2 (42)  97 Host HCI Transport (3-Wire UART) To reduce the number of signals and to
DL3 (39)  RCL DIP 07+ † Typical values are at VCC = 5 V, TA = 25C. ¶ This parameter
DL4 (95)  N/A DL-34 The E/A will start to operate and the output voltage starts to increase.
DL5 (46)  TOKO DIP The AV9155 is a low cost frequency generator designed spe- cifically for
DL6 (164)  90 Output is asserted if line alarm indication signal (LAIS), path alarm ind
DL7 (14)  TOKO DIP-14 07+/08+ The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily
DL8 (10)  IC+ QFP 02+ It is possible to connect the Data In and Data Out pins together. Howev
DL9 (3)  DATEX QFP 07+ IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark o
DLA (31)  SOD-6 The DLA11C/LA offers precise gains from 1 to 5 with a true 0.1% linearit
DLB (3)  PHI SOP 05+ Also See: • HEDS-9000/HEDS-9100   Encoder Module Data Sheet
DLC (18)  PLCC   The MPX10 series device is a silicon piezoresistive pressure senso
DLD (3)   Gallium arsenide (GaAs) is a substance used in the products describ
DLE (2)  Comparator/Interrupt Mode As indicated in the O.S. Output Temperature Re-
DLF (9)  In the event that any or all SANYO products(including technical data,serv
DLG (10)  sie sie dc96 The INH inhibit input can be used to cut off the complete module. This re
DLH (42)  timonta timonta dc95 Fast Carry: As described earlier, each CLB includes high- speed carry lo
DLK (2)  TI 07+ N-channel enhancement mode field-effect power transistor in a plast
DLL (4)  DEC 01+ Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient
DLM (7)  N/A  This data sheet has been carefullyAPEX MICROTECHNOLOGY checked and i
DLN (4)  ALLEGRO DIP The accuracy of the DAC/reference combination is 1%. The overvoltage and
DLO (6)  The Hyundai HYM72V64C736AT4 Series are 64Mx72bits ECC Synchronous DRAM Mod
DLP (43)  1. Tolerance 10% for L > 10 µH, 20% for L 10µH 2. Induc
DLR (9)  SIEMENS DIP 9818+ The BCT8244A scan test devices with octal buffers are members of the Te
DLS (8)  MICREL CDIP CDIP Note 1. Exceeding the absolute maximum rating may damage the device. Note
DLT (14)  AT 07+   Controller (host) sends a start bit.   Controller (host) send
DLV (3) 
DLW (52)  N/A The information contained herein is presented only as a guide for the app
DLX (1)  A max clock frequency of 0.5MHz is assumed. For applications where a le
DLY (1)  SAMSUNG SMD SMD The application circuit shows a flyback converter for video recorders wit
DLZ (3)  INTERPOINT CDIP16 0002+ Suffix denotes Vz tolerance: non suffix for 20%, A suffix for 10%. Measu
DM- (30)  SCM QFP 06+ rating only, and functional operation of the device at these or any other
DM. (3)  NS SOP14S 2007+ This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configurat
DM/ (7)  NS SOP16S 2007+ Couples AC and DC signals 0.01 % Servo Linearity Wide Bandwidth, >
DM0 (32)  FSC DIP-8 05+ If the scene is too dark and the integration period has almost reached
DM1 (189)  NS CDIP16 84 7. The CH1817 DAA as is meets or exceeds the   hazardousvoltage,surg
DM2 (121)  NS DIP 2006 er clock, the master must have an open drain out- put, and a pull-up re
DM3 (52)  MICROCHIP 08+PBF In the 5 pins configuration (PENTAWATT and PPAK) a Shutdown Logic Contr
DM4 (41)  98+ 模块 The semiflash architecture reduces power consumption and die size compa
DM5 (786)  NS 00+   The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchr
DM6 (21)  DAVICOM QFP100 Note 1: Absolute Maximum Ratings are those values beyond which the life
DM7 (2566)  NS 11 Drain-to-Source Breakdown Voltage 500 Gate Threshold Voltage …2.0
DM8 (232)  NS . The conditions at the binary-select inputs and the three enable inputs se
DM9 (203)  VICOM QFP 9940+ Output clock. This pin is selectable under processor control to be either
DMA (33)  N/A PLCC 07+ Programmable Power Limiting and Current Limiting for Complete SOA Protec
DMB (17)  CTC (LX)high-frequency 1. Timer Data Structure   The DMB10-25 using BCD code which consist
DMC (221)  DAEWOO 2008 The active polarity of SHP/SHD (active high or active low) can be chosen
DMD (25)  SANREX 04+ The terminator's internal power is dissipated primarily by conduction th
DME (17)  SMSC QFP 06+ Error Flag (FAN2501 only) To indicate conditions such as input voltage d
DMF (20)  PARTRON 05+ The SL1024A series offers high levels of current handling on fast rising
DMI (3)  ITT VID0-VID4 (DAC Digital Input Code Control) Pins 15-11 - These are the DA
DMJ (9)  ALPHA 08+ SCLK Frequency SCLK Cycle Time SCLK Low Time SCLK High Time SYNC to SC
DML (7)  ST SOP 04+ Wire-bond and flip-chip packages are available. Table 4 and Table 5 show
DMM (16)  DIODES This device provides the necessary clocks for a differential host bus sys
DMN (34)  DIODES SOT-23 07+PB   Composite type with an N-Channel Sillicon MOSFET unit : mm  
DMO (2)  DIODES SOD-523 06+PB RXD[4:1] are dual purpose pins. When RESET is active, these pins are samp
DMP (69)  ST DIP-18 04+ Fifth Generation HEXFETs from International Rectifier utilize advanced
DMQ (2)  FSC CDIP 8530   The first character of the part number suffix determines the devic
DMR (62)  apm apm dc00 Each DAC has a high-impedance differential current output, suitable for s
DMS (14)  high-frequency tube TOS 04+ • Fast access time:   C 4 ns-125 MHz; 5 ns-100 MHz;   6
DMT (12)    Case: Molded Epoxy   Epoxy Meets UL94, VO at 1/8   Weig
DMU (4)  ST TO-220 Bottom of DAC reference ladder. Normally bypassed with a 0.1µF capac
DMV (30)  DMV QFP 3.1 The END USER shall have the right to transfer the AMBE-2000™ Vo
DMX (15)  N/A DIP 03+ The DC/DC converter is a programmable topology synchronized Buck conver
DMZ (2)  N/A Notes: (1) Clip mounting (on case), where lead does not overlap heatsink
D-N (1)  Factory locked and identifiable: 16 bytes available for   secure, ra
DN- (6)  DATANET QFP-60P 6+ SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sy
DN0 (6)  N/A SSOP-24P 07+   High-speed access time: 8, 10, 12, and 15 ns   CMOS low powe
DN1 (45)  Notes: 3. These specifications are guaranteed only for the test conditio
DN2 (29)  SUPERTEX 08+
DN3 (22)  SILICONIX 00+ CAN/6 The Electrical and Switching Characteristics of the HCPL-2300/HCPL-0300
DN4 (10)  PLCC 03+ DESCRIPTION Axial Power Schottky rectifier suited for Switch Mode Power
DN5 (14)  AUK 06+ SOT89 PROGRAM MEMORY Program memory consists of 768 x 8 ROM These bytes of RO
DN6 (24)  Panasonic QFP- 07+/08+   Information present at any register is transferred to the respect
DN7 (87)  FAIRCHILD SOP16 99 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATING
DN8 (58)  PANASONIC
DNA (28)  HIT The VCXO provides a tunable, low-jitter frequency refer- ence for the r
DNB (3)  DAEWOO 2007 Fault (Open-Drain Output/Input): This active-low output signal activated
DNC (3)  DAEWOO 2008  This evaluation board is designed to have the maximum value of VG a
DND (1)  Speaker output signal can be attenuated either by internal register or ex
DNE (7)  JAPEN 06+ DIP-64 The Fairchild Switch FSTU6800 provides 10-bits of high- speed CMOS TTL-
DNF (39)  AERODEV N/A   The Rambus ® RIMMTM module is a general purpose high-performa
DNG (1)  The LPV321 is available in space saving SC70-5, which is approximately
DNI (12)  ADVANTECH 0446+ push-pull outputs which are sequentially pulsed in groupings of bursts; a
DNM (2)  DIP NS 98+   Motorolas MPXAZ4115A series sensor integrates onCchip, bipolar op
DNN (2)  ROHM SOT353 01+ Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups T
DNO (2)  N/A N/A N/A Available in the Texas Instruments NanoStar and NanoFree
DNP (4)  N/A All outputs are capable of driving 2Vpp, AC or DC coupled, into either a
DNS (2)  SOP28 05+ The MATCH ROM command, 55h, is used by the host to select a specific SDQ
DNV (1)  2008 The sensor consists of a precision linear Hall IC, which is optimized to
DNX (1)    DESCRIPTION   The NJW1503A is a PLL frequency synthesizer es
DO- (2)  The FLEX 8000 family is supported by Alteras MAX+PLUS II development sys
DO0 (5)  CRYDOM Relay(new original) 1. Use this component within operating temperature range. It might not be
DO1 (84)  N/A The HD74LV2G245A has two buffers with three state output in an 8 pin pack
DO2 (6)  MICREL QPN 04+ (VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RL = 16Ω
DO3 (115)  N/A The ICL7106 and ICL7107 are high performance, low power, 3½ digit A
DO4 (2)  SMD En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 2: P1
DO5 (56)  N/A It is recommended that CE be decoded and used as the primary device-selec
DO6 (2)  DIALOG DIP-28 01+ The hardware RESET# pin terminates any opera- tion in progress and resets
DO7 (6)  DIALOG SOP 03+/04 Areas where care in design must be observed are thermal ground, RF groun
DO8 (1)  ON 01+ SOP-8 • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V p
DO9 (3)  UOL QFP O1 This Digital Audio HEXFET® is specifically designed for Class-D audio
DOA (3)  N/A The HYM71V75S1601 H-Series are Dual In-line Memory Modules suitable for ea
DOC (15)  Transtek Magnetics 02+
DOE (4)  A/N QFN 00 Power Diode Module DD100GB series are designed for various rectifier circ
DOG (1)  Low power dc-to-dc regulator designers must consider both the on-resista
DOH (1)  8 ST 03+ One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCO
DOL (2)  TI 07+ The above default CD/Mute function can be overwritten as follows: if the
DOM (2)  MICROCHIP SMD18 I. Introduction In portable communication equipment, such as cellular pho
DOO (1)    For driving the N-Channel gates, it is important to keep in mind t
DOR (2)  ADDRESS INPUTS A0 through A25 are address bus lines which enable direct
DOS (1)  AMIS 06+ 500 Lead finish is solder dipped rather than gold plated. This option is avai
DOT (2)  99 High Speed: tPD = 1.0 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC
DOV (1)  MIC SOT143-4 05+ Use Opti-MEM® I Reduced Serum Medium (Catalog no. 31985-062) to dilut
DOY (1)  EX 805 05+ A bias arrangement that can be accomplished at lower cost than those al
D-P (1)  The intended application of this device and signaling technique is for po
DP- (7)  FAIRCHILD SOT153 06+ Members of the Texas Instruments Widebus™ Family Flow-Through Arch
DP0 (34)  PHAEDRUS 03+ Stresses beyond those listed under Absolute Maximum Ratings may cause p
DP1 (61)  apem apem dc05 These chips, when properly assembled, display characteristics similar to
DP2 (31)  08+ Output frequency range: 2050 MHz to 2450 MHz Divide-by-2 output 3.0 V t
DP3 (19)  DANFOSS SOP The Hyundai HYM71V73C1601 H-Series are 16Mx72bits ECC Synchronous DRAM Mod
DP4 (13)  N/A Two clock sources are used to drive the microcontroller, a main clock dri
DP5 (26)  N/A N/A N/A The 80C186EB can receive interrupts from a num- ber of sources both inte
DP6 (11)  95/96 CAPACITIVE LOADS Like most micropower circuits, the LM45 has a limited a
DP7 (30)  CPL-E SOP-8 04+ the device has a Sector Protect function which hardware write protects
DP8 (793)  NS DIP 07+ to the load side, the effective resistance between the regulator and the
DP9 (17)  FAI N/A TO-220 P5 This input is programmable. It functions as a read-write input (R/W) and
DPA (79)  POWER TO-263 07+ The output pull-up structure can be globally configured to be either a
DPB (6)  eupec This Infineon module family are industry standard 144-pin 8-byte Synchron
DPC (29)  NS N/A 01+ pre-filter, followed by an eighth order switched-capacitor bandpass fil
DPD (10)  DC-DC DIP DIP † All typical values are at VCC = 2.5 V, TA = 25C. ‡ The bus
DPE (1)  The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM i
DPF (7)  COSEL SOP Two video control output signals (VIDCTL[1:0]) provide digital control
DPG (4)  IXYS TO-247 08+   C Fifteen 32K Word (64K Bytes) Sectors with Individual Write Locko
DPH (2)  TQFP1414-100 Efficiency at 3-A Continuous Output Current Uses External Lowside MOSFET
DPI (8)  NOTES 1. Operating temperature range is as follows: B Version: C40C to +
DPJ (1)  • 0.13µ CMOS design allows industrys lowest power • Ad
DPK (3)  NOTES:  1. Dimensions are in inches.  2. Metric equivalents ar
DPL (36)  ALTERA SOP 02+ OSCILLATOR The UC3823A,B/3825A,B oscillator is a saw tooth. The rising
DPM (9)  162 The device supports low-power standby operation. When RESET is low, the d
DPN (2)  Hynix HYMD212G726A(L)S4M-M/K/H/L series is designed for high speed of up
DPO (3)  QFP 03+/04
DPP (3)  micronas micronas dc00
DPR (4)  TECOM SOP-16 97+   The following discussion refers to the schematic below. A FET cur
DPS (117)  NS SOP24 01+ Over Vin range Measured at center of case, auto-reset Surface tempratur
DPT (41)  DPT 07/08+ The DDU4C tolerances are guaranteed for input pulse widths and periods gr
DPU (42)  1230 Several pins on this device serve as dual function in- put/output pins. D
DPV (5)  LUCENT O7+ NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the
DPW (2)  (5) The products and product specifications described in this material ar
DPX (32)  TDK 1206 Braking. The braking function is implemented by driv- ing the device in
DPZ (1)  High and low band filters are included to shape the amplitude and phase r
DQ0 (1)  PHILIPS QFP80 03/04+ The ADS8381 is an 18-bit, 580 kHz A/D converter. The device includes a
DQ1 (16)  sgs sgs dc80+ CURRENT MONITOR- is a pin providing a current viewing sig- nal for exter
DQ2 (78)  SEEQ DIP Figure 2 shows the waveforms of the circuit of Figure 1. This circuit h
DQ3 (2)  SEEQ DIP 07+ Boost converter with a 2A, 0.18Ω switch Boost output voltage adju
DQ4 (3)  SEEQ DIP Voice within each group are combinations of different fixed memory secti
DQ5 (26)  SEEQ DIP The Harris CD74HC259 and CD74HCT299 are 8-bit shift/storage registers w
DQ6 (8)  AC Electrical Characteristics (Continued) (See Notes 1 and 4 and Figure 1
DQ7 (4)  Coev 2006+  tr, tf0.11.0ns0.55 to 2.4V AC characteristics apply for parallel o
DQ8 (9)  SEEQ DIP 04+ NOTE: Intersil Pb-free plus anneal products employ special Pb-free materi
DQ9 (4)  SI SOP/8 00+   This user system interface cable should only be used by those who
DQA (1)  SEEQ 04+ • The basic gate function is lined up as Renesas uni logic series.
DQC (1)  Note 1) The specified condition Tj=25˚C means that the test should
DQD (1)  NOTE: EP circuits are designed to meet the DC specifications shown in the
DQM (2)  If the boot loader revision in the device is previous to V1.63 then in up
DQN (1)  Storage temperature range, TSTG−65 to +150C (1) Stresses above th
DQX (1) 
DR- (50)  SANKEN 06+ DIP EN - Is the enabling input for the bridge. This digital input, when pull
DR0 (8)  BEN 05/06+ Thermal Resistance, Junction-to-Case - IGBT Thermal Resistance, Junctio
DR1 (29)  QFP48 The ground return for the digital supply for the ADC12DL065s output driv
DR2 (16)  N/A module 2005+ The DS1267 Dual Digital Potentiometer Chip consists of two digitally contr
DR3 (58)  DSP 04+ QFP Medium-range Cable, satellite, and IP set-top boxes Digital video recorde
DR4 (4)  netwave netwave dc00+ The DR4001043 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 6
DR5 (2)  AIWA 97+ QFP-100P ENCV Variable clock enable (TTL compatible input) - This input directly c
DR6 (12)  MACOM SOP16 04+ Length is measured from the mounting surface to the free end of the sha
DR7 (17)  Coiltronics 2008+   Each device includes a voltage regulator for operation with supply
DR8 (4)    MAX6323_UT__-T -40C to +125C 6 SOT23-6 Push-Pull   MAX6324_UT
DR9 (4)  ROHM SMD SMD The treble network consists of R7, R8, R9, R10, C7, C8, C9, and C10. Res
DRA (77)  00+ 8 BGA MAS9162 is a low dropout voltage regulator with an enable/disable pin,
DRB (6)  MURATA 2000 This model provides a more precise description of the thermal charac- ter
DRC (25)  ddc ddc dc87 Note 6: The fOP frequency specification specifies a minimum clock period
DRD (73)  murata murata dc00 • SuperWIDE HIGH DENSITY IN-SYSTEM   PROGRAMMABLE LOGIC  
DRE (20)  TI 07+ SUMMARY DESCRIPTION The M68AF511AL is a 4 Mbit (4,194,304 bit) CMOS SRA
DRF (13)  AUK SOT-223 05+ 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-R
DRG (3)  POWER Threshold Current (BOL) Wavelength Wavelength Tuning Coefficient Exte
DRH (23)  Power-Up Sequence. (see Fig. 8):  1.1 Upon application of input powe
DRI (37)  TI 07+ Case: SOT-23, Molded Plastic Case material - UL Flammability Rating Clas
DRK (1)  The bq2060 SBS-Compliant Gas Gauge IC for battery pack or in-system inst
DRL (7)  1500 The CA3227 consists of five general purpose silicon NPN transistor
DRM (18)  SMD AUK 05+ Maximum gain setpoint for all phase setpoints VBBI = VBBQ = 0 V differen
DRN (4)  *Very low power consumption *Wide common-mode (up to Vcc+ ) and different
DRO (3)  The THS4061 and THS4062 are general- purpose, single/dual, high-speed v
DRP (22)  430 The bq2000 is a programmable, monolithic IC for fast-charge manage- ment
DRQ (81)  Coiltronics 2008+ The device can easily control keys over graphical LCD panels or LEDs when
DRR (40)  N/A The HSDL-3600 comes in three package options; the front view option (
DRS (58)  Fujitsu DIP-5 07+/08+ These chips, when properly assembled, display characteristics similar to
DRT (18)  2000 Stresses beyond those listed under "absolute maximum ratings" ma
DRU (6)  BB 06+ 500 2not subject to production test, specified by design 3V   Loaddump
DRV (144)  BB TR7 04+ ANALOG I/O   8-Channel, 400kSPS High Accuracy, 12-Bit ADC   O
DRW (16)  OEG Relay(new original) These devices have a 300% minimum CTR at an input current of only 0.5
DRX (22)  micronas micronas dc03 • Single 3.3V0.3V power supply • All device pins are LVTTL co
DRY (3)  N/A N/A N/A   The EP111 is specifically designed, modeled and produced with low
DRZ (1)  Note 12: The maximum absolute allowable voltage which may be applied to t
D-S (6)  N/A N/A The device has a low 12µA quiescent supply current, which reduces t
DS- (89)  SHINKO 04+ SMD These octal transparent D-type latches feature 3-state outputs designed
DS/ (11)  NS SOP16S 2007+ This device contains circuitry to protect the inputs against damage due t
DS0 (238)  The IALUs have hardware support for circular buffers, bit reverse, and z
DS1 (5685)  DALLS SOP8 95+99+ After a minimum wait of 250 ns (5V operation) from the falling edge of
DS2 (1456)  NS CDIP16 —— 1 A critical component is a component used   in a life-support devi
DS3 (696)  N/A Voltage Output Models Three settling times are specified to 0.01% of ful
DS4 (481)  AMD   Flash Performance   70 ns Initial Access Speed   25 n
DS5 (337)  NS The ADS1206 and ADS1207 are a low-cost, high-performance, synchronous v
DS6 (31)  MOTOROLA Processor Socket Chipset System memory (GB) DIMM slots Flash EPROM Sy
DS7 (427)  NS DIP
DS8 (539)  DALLAS DIP 05+ • 2nd generation HOTLink® technology • Fibre Channel and
DS9 (1140)  N.S The 82091AA Advanced Integrated Peripheral (AIP) is an integrated I O sol
DSA (96)  AD 1.2MHz Switching Frequency Low VCESAT Switches: 330mV at 1.3A High Outpu
DSB (53)  SANYO SOT-23 The LM89 is an 11-bit digital temperature sensor with a 2-wire System M
DSC (105)  Notes:  2. Multiple Supplies: The voltage on any input or I/O pin ca
DSD (101)  IXYS O6+ TO-247 The HEDS-5500, 5540, 5600, 5640, and the HEDM-5500, 5600 provide moti
DSE (277)  N/A N/A N/A CONNECTION MODE   In Connection Mode, the addresses of input source
DSF (12)  SANYO 05+ The integrated power-on reset (POR) circuitry sets the internal logic to
DSG (5)  SANYO SOT-23 05+ other than the GSM Tx path, thus achiev- ing low loss. For the GSM Tx pa
DSH (44)  DSP QFP   The TC55NEM216AFTN is a 4,194,304-bit static random access memory
DSI (50)  IXYS O6+ TO-220AC Valid Combinations list configurations planned to be supported in volum
DSK (63)  99   The DSK10B-AB1, DSK10B-AB1 series are optically coupled isolators
DSL (9)  N/A PQFP-100 01 The SPT1018 is a monolithic 8-bit digital-to-analog converter capable of
DSM (56)  SANYO SMA The MCF5249 was designed as a system controller/decoder for MP3 music pla
DSN (19)  SANYO SOT-89 12. Measured by the voltage drop between A and B pins at the indicated cu
DSO (49)  INFINEON SOP12 04+ A capacitor is a component which is capable of storing electrical energy.
DSP (1093)  LUCENT 01+ Blocking voltage : VDRM / VRRM = +/-700V Avalanche controlled : VCL typ
DSQ (2)  299 DALLAS 07+ The MT8931C Subscriber Network Interface Circuit (SNIC) implements the ET
DSR (63)  DSR Output voltage can be programmed using the on-chip DAC or an external pre
DSS (266)  MURATA Aluminum electrolytic or tantalum capacitor types can be used. (Because
DST (43)  KDS   Please be aware that an important notice concerning availability,
DSU (57)  Modulus control output for controlling an external dual-modulus prescaler
DSV (7)  NS SMD Bidirectional Data I/O lines. As inputs, they feed into an on-chip data re
DSW (5)  95 The Discharge Count Register (DCR) is used to update the Last Measured Di
DSX (51)  KDS 96+ SMD High-speed consumer electronic ports ESD protection of PC ports, includ
DSY (8)  DALLAS BGA 08+ Supported by FPGA Foundation™ and Alliance Development Systems -
DSZ (4)  DALLAS 06+ It contains 8 bidirectional and digitally controlled analog switches. A
DT- (22)  NA 05+ DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer
DT0 (19)  FDK 00+ 1. Specified value of the pick-up, drop-out, set and reset voltage
DT1 (132)  ROHM 3000 07+ Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video
DT2 (102)  N/A N/A N/A The TLC3704C is characterized for operation over the commercial tempera
DT3 (75)  DELTA 0043+ • 1.8V/2.5V +0.1V/-0.1V Power Supply. • I/O Supply Voltage 1.
DT4 (20)  LUCENT 2008 Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current
DT5 (28)  EUPEC MODULE Begin analysis at the VOL (quiescent) point. This is the intersection of
DT6 (39)  DELTA 0135+ The 3819 group is a 8-bit microcomputer based on the 740 family core tec
DT7 (119)  N/A SSOP 07+ Note 5: Dynamic supply current is higher due to the gate charge being de
DT8 (7)  1735 The 74LVC(H)16244A is a high-performance, low power, low voltage, Si-ga
DT9 (20)  EUPEC 模块 07+特价模块 The differential input serial data (RIN) is not only used by the PLL to
DTA (703)  ROHM Fast access times: 8 ns, 8.5 ns, 10 ns, and 12 ns Internal self-timed w
DTB (80)  ROHM SOT23 The ADS821 is a low-power, monolithic 10-bit, 40MHz Ana- log-to-Digital
DTC (945)  ROHM SOT-23 Timer counter 4 : 8-bit 1  (prescaler, serial clock generator, time
DTD (89)  三角牌 SOT-23 The ADC108S102 is a low-power, eight-channel CMOS 10- bit analog-to-digi
DTE (9)  DELTA 05+ Voltage follower/buffer/amplifier Charge integrator Photodiode amplifie
DTF (4)  SSOP 98+ An output voltage droop can be programmed to improve the transient window
DTG (5)  G 金属帽 8724 In the interest of memory transfer operation applications, the IS93C46A/
DTH (1)  The thermally efficient package mea- sures only 2mm x 2mm x 0.75mm. Its
DTI (17)  ITT QFP-48 03+ 3.3 Volt Operation (5V tolerant) Programmable Wakeup Event Interface (IO_
DTK (2)  100 天龙伟业 靳先生 Single Byte/Single Cycle Code Execution The efficiency is due to the fac
DTL (3)    The SY10EP89V is a differential fanout gate specifically designed
DTM (15)  N/A TQFP-100   Two products are offered in the series with different output volt
DTN (10)  N/A 0805T The bq2000 uses a peak-voltage detection (PVD) scheme to terminate fast c
DTP (5)  Unless otherwise stated, all power supplies = 3.3V, no load on any output,
DTR (46)  TRANSCL 0303+ The DTR-03-S aligns the recovered data clock frequency to the reference c
DTS (52)  N/A The AT17A Series Configurator allows the user to program the polarity of
DTT (8)  N/A The use of Differential Rambus Signaling Level (DRSL) tech- nology permi
DTU (3)  ROHM 05+ A 6:1 stereo input multiplexer is included for selecting between line l
DTV (56)  ST TO-220 99145   The MSK 4370 is a complete 3 Phase IGBT Bridge Brushless Motor Con
DTW (31)  When 16/68# pin is at logic 1, this input is chip select B (active low)
DTZ (129)  ROHM 0805-4.7V 05+ 2. Tlow to Thigh = 0 to +125C for LM317MTlow to Thigh = − 40 to +1
D-U (3)  TVIA PQFP 2000 Low output skew: <270ps Switching frequency of 133 MHz Fast output ri
DU1 (22)  MA/COM HIGHFREQUENCY N/A The Blackfin processor instruction set has been optimized so that 16-bit
DU2 (16)  M/A-COM (LX)high-frequency Bay Linear products are not authorized for and should not be used within
DU3 (1)  DSP QFP 05+ The STTH60L06, which is using ST Turbo 2 600V technology, is specially
DU4 (1) 
DU6 (1)  Coev 2006+ Switch Enable into Heavy Load If a switch is powered-on or enabled into a
DU8 (1)  N/A N/A 06+ Maximum Sample Rate: 40MSPS 12-Bit Resolution No Missing Codes Power Di
DUA (5)  MCI AVSD QFP144 • Up to 10-A Output Current • 3.3-V Input Voltage • Wi
DUB (2)  STM SOP-16 02+ The Si5010 is a fully integrated low-power clock and data recovery (CDR)
DUC (6)  TI TSSOP56 01+   Composite type with a P-Channel Sillicon MOSFET (MCH3339) and a Sc
DUD (2)  Chapter 6, "Instruction Set," describes the features and convent
DUF (2)  EMKO 2005 Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .
DUG (2)  signal signal dc99 All rights reserved. No part of this publication may be reproduced, stored
DUH (5)  DSP QFP 05+Original ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operat
DUL (8)  DSP QFP 05+Original A host reads, programs, or checks the status of the bq2022 through the hi
DUM (82)  UNI SSOP16 07+ Tip/Ring Gain Select (Output). This is the output of the Tip/Ring connect
DUO (1)  structed as a multi-chip hybrid device. Actuation control is via an Inf
DUP (5)  NEC 06+ 625 Notes: 1. See test circuit and wave forms. 2. This parameter is guarante
DUR (1) 
DUS (32)  2000 Parameter REFERENCE INPUTS   REFIN(+) to REFIN(C) Voltage1, 9 &nbs
DUT (1)  The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and
DUW (1)  This new generation of trench MOSFETs from Zetex utilizes a unique struct
DUX (5)  4200 operations and low power and low noise applications. It can be interfa
DUZ (1) 
DV- (5)  HAR PLCC Symmetrical Switch Points Superior Temperature Stability Operation From
DV0 (7)  MICROCHIP 08+PBF Write Enable (WEN) When VCC is applied to the part it powers up in the W
DV1 (49)  MICROCHIP The MAX5942A/MAX5942B integrate a complete power IC for powered devices (
DV2 (47)  TC9208M includes a physical layer configuration / polling entity, which i
DV3 (22)  FUJITSU DIP-16 08+ The DS1809 will also support a command-initiated wiper storage operation
DV4 (6)  DIP 94+ - Low current consumption:   In operation: 100µA max.  
DV5 (6)  ICS SOP-20 03+ Synchronization input. Dual function pin which provides logic input to sy
DV6 (4)  MPEG PQFP N/A er clock, the master must have an open drain out- put, and a pull-up re
DV7 (55)  DV 96 International Rectifier's DV74HC04AN is an Integrated Power Module develop
DV8 (3)  FUJ N/A 08+ If the FIFO is configured to have two write enables, when Write Enable (
DV9 (4)  HARRIS PLCC-M44P 06+ • Separate Memory Banks by Address Space   C Simultaneous Re
DVA (35)  MICROCHIP 08+PBF The HT75XX-1 series is a set of three-terminal high cur- rent low voltage
DVB (2)  ST N/A 1) Worst case package. 2) Max number of outputs defined as (n). Data in
DVC (51)  98 • 1.27 mm (0.050 in.) pitch contact arrangement in two   rows
DVD (8)  TI QFP NOTE: Intersil Pb-free products employ special Pb-free material sets; mol
DVI (2)  ST SOT23 06+ Note 6: Junction-to-ambient thermal resistance is highly dependent on app
DVJ (1)  The i.MX processor features the advanced and power- efficient ARM920T&#
DVK (1)  The devices feature logic level input control and very low output on-r
DVL (1)  The IRU1117-18 is a low dropout three-terminal fixed out- put regulator w
DVM (7)  DEL 0551+ † Stresses beyond those listed under absolute maximum ratings may c
DVN (1)  N/A 3X3 可调密封 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
DVP (8)  TI 07+ The reset cycle continues for the first 18 clock pulses of the data outpu
DVR (4)  LOACON The TO-220 Fullpak eliminates the need for additional insulating hardware
DVS (10)  MOTOROLA SOP Designers must not rely on the absence or characteristics of any features
DVX (10)  N/A N/A N/A Single Voltage, Range 3V to 3.6V Supply 3-Volt-Only Read and Write Operat
DVZ (1) 
DW- (48)  DAEWOO DIP 07+ The transistor must be a small-signal type with a rela- tively high forwa
DW0 (52)  TOREX 2008 Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanst
DW1 (25)  ST QFP Delivers spacious 3D sound for a stereo system with such as cellular phon
DW2 (6)  06+ SOP-20 Fault protection is provided by an output overvoltage comparator and opti
DW3 (28)  MITSUBISHI QFP-100 08+ The LM5110 Dual Gate Driver replaces industry standard gate drivers wit
DW4 (2)  PANASONIC The Maximum allowable values of Cx and Rx are a function of leakage of ca
DW5 (4)  To protect against load faults, these ISRs incorporate output over-curre
DW6 (13)  sgs sgs dc79+ Low Frequency Vibration: Vibration shall consist of simple harmonic moti
DW7 (11)  CAN3 The MAX6746CMAX6753 low-power microprocessor (µP) supervisory circu
DW8 (25)  SANYO DIP-42 02+ INVALID OP-CODE: If an invalid op-code is received, no data will be shift
DW9 (28)  ZILOG Chip Select is a TTL compatible input which, when set HIGH, allows norm
DWA (10)  TOSHIBA SOT143 Read/write access to the four local buses C NS1, EW1, NS2 and EW2 C is
DWC (4)  TOSHIBA SOT143 The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail i
DWD (15)  96 The RDRAM device is a general purpose high-perfor- mance memory
DWF (52)  N/A Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-
DWG (1)  Notes: 1: Stresses above those listed in Absolute Maximum Ratings may cau
DWI (1)  N/A 0805L TC9208M provides evolved CoS with four levels of priority. The priority c
DWK (1)  The circuit of the TSOP11..SK1 is designed in that way that unexpected
DWM (22)  PHILIPS 06+ The attack and decay time constant of the AGC is set by the internal se
DWO (3)    The HF80 die type has been found to have all pins able to withstan
DWP (14)  SONY 1300 05+ When the regulator current exceeds the Overcurrent Threshold for a perio
DWR (10)  SANREX MODULE The digitized video and clocks provided to the decoder can be either loc
DWS (6)  DAEWOO 2008 POWER SUPPLY  Supply Voltages   AVDD   DVDD  Analo
DWT (1)  ???? 06+ The analog-to-digital converter (ADC) utilizes a fully differential and p
DX- (3)  - - - Shunt protection devices clamp voltage peaks at the VDD-pin together wi
DX/ (1)  Collector-emitter Breakdown (BVCEO) SFH600-0, 1, 2, 3, 4 SFH601-1, 2,
DX0 (4)  PMI 94 1) CPD is defined as the value of the ICs internal equivalent capacitance
DX1 (16)  LUCENT DIP For applications without standby or suspend modes, lower values of R1 a
DX2 (23)  INTEJ . . * Metal of silicon rectifier, majority carrier conducton * Guard ring for
DX3 (5)  LINIENTY PLCC-44 Supply voltage for LCD driver: 15.0 to 30.0 V Number of LCD driver output
DX4 (10)  LUCENT 04+ • 27 dB modulated gain 5.15 to 5.85 GHz band • 26 dBm output
DX5 (3)  DIP28 Per MIL-STD-202, Method 213, Condition E Per MIL-STD-833, Method 1011, Co
DX6 (1)  Trdent 00+ AEC-Q100† Qualified for Automotive Applications Customer-Specific
DX8 (2)  SPECIFICATION NOTES: 1 All parameters specified for Ta = 25 C, Vcc = 15V
DX9 (1)  ZILOG QFP-44 03+   Low-latency option Skew alignment support for multiple bytes of of
DXC (1)  If VBatt > 28.5 V (typ.), the voltage limitation of the IC is reduced
DXK (1)  Bild / Fig. 8 W3C - Dreiphasen-Wechselwegschaltung / Three-phase inverse
DXL (1)  DXLxx ON TSOP-5 over the full operating temperature range. Unless otherwise specified: VI
DXM (4)  Axial and Surface Mount Power Schottky rectifier suited for Switch Mode
DXO (42)  Stresses beyond those listed under Absolute Maximum Ratings may cause perm
DXP (1)  QFP 1996 † Stresses beyond those listed under absolute maximum ratings may c
DXS (1)  FUJSOKU 01+ I2C bus control items Contrast control: -38dB - Sub contrast control fo
DXW (1)  MURATA - Suspends erase operations to allow programming in   same bank Da
DXY (1)  ON SOP-8 04+ No license, express or implied, by estoppel or otherwise, to any intellect
DY0 (2)  HYUNDAI PLCC N/A This document is preliminary. As such, it contains data derived from func
DY1 (2)  DONG YANG NA The DY1S(5VDC) includes a programmable internal RISC processor core that
DY2 (2)  A new Power Management Mode (PMM) is useful for portable applications. Thi
DY3 (9)  These quadruple bus transceivers are designed for asynchronous communic
DY4 (2)  5V power supply 5V power supply 5V LNA power supply RF input LNA grou
DY5 (1)  Chapter 4, "Control Registers," contains overview tables for all
DY6 (4)  ESD damage can range from subtle performance degrada- tion to complete
DY8 (4)  INTEL 03/04+ When used as a position Auto Shut-Off module, several timing options are
DY9 (3)  J Collector-to-Emitter Voltage Continuous Collector Current Continuous
DYA (1)  Message and streaming status modes Raw cell mode (52 octet) 200 Mbps ha
DYB (1)  DIBCOM N/A 04+ NOTES: 1. Chip Enable references are shown above with the actual CE0 and
DYD (1)  EXAR 06+ 500 The clock source jitter and the aperture jitter combine in an rms manner
DYG (1)  This device operates from a single 3.3-V supply. The device has integrate
DYH (1)  N/A Hermetic Isolated Surface Mount Package Adjustable Output Voltage Elim
DYI (1)  16Pin 2007+ The high common-mode input voltage range and the absence of latch-up make
DYM (2)  SMD-8 04 05 To verify that the input offset voltage falls within the limits specified
DYN (6)  Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic conve
DYR (1)  N/A SMD N/A During the first 30 ms after enabling VCO1 the modulator phase comparator
DYS (1)  N/A MKK 05+ The information provided herein is believed to be reliable at press time.
DYT (1)  96 Under a forward bias (metal connected to positive in an n-doped Schottky
DZ- (4)  YOMRONS Axial and Surface Mount Power Schottky rectifier suited for Switch Mode
DZ0 (3)  SANYO NA • Three-phase bipolar PWM drive (high and low side   n-channe
DZ1 (29)  Totally Synchronous Operation All Outputs Buffered Single Supply Operati
DZ2 (88)  2 V-Infinity reserves the right to make changes to its products or to discon
DZ3 (2) 
DZ4 (4)  Boot Blocks : The two boot blocks are intended to replace a dedicated bo
DZ5 (7)  A static memory controller is included that supports up to four 16 MB Fla
DZ6 (13)  N/A The modular approach to implementing a USB interface device allows the de
DZ7 (2)    C High-performance 32-bit RISC Architecture   C High-density
DZ8 (8)  GS The low-cost ADS-930 is a high-performance, 16-bit, 500kHz sampling A/D
DZ9 (16)  SMB The HT24LC08 is an 8K-bit serial read/write non-volatile memory device us
DZA (19)  SOP32W 2007+ Turn-On Time Turning Q1 in Figure 1 off, removes the low-voltage signal
DZB (1)  *Stresses above those listed under Absolute Maximum Ratings may cause per
DZD (25)  SANYO 23 VGD: The VGD pin which is coarsely regulated around 9V and is primarily
DZN (1)  ADJ: In the adjustable version, the user programs the output voltage with
DZO (1)  accumulator or multiple multiplier array. One, two, and three-pass algor
DZP (5)  MOT 06+ 500 Addresses and chip enables are registered at rising edge of clock when ei
DZT (2)  PHILIPS Note 1: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V (MAX5143/MAX5
DZV (1)  UDZS 2001 3200 Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Ou
DZW (5)  ST 圆柱   The LX1991 features resistor settable output current. Connecting
DZX (3)  © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
DZZ (21)  Where VSAT = 0.25V (switch saturation voltage). The current overshoot wil
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