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  Mfg pack D/C Descrpion
C.P (1)  NEC/TOKIN The MCU provides the following features: 40K bytes of In-System Programma
C.T (2) 
C/2 (1) 
C/4 (1) 
C/C (23) 
C/D (4) 
C/E (2) 
C/H (1) 
C/U (1) 
C-0 (8)  EPSON When the JTAG interface in MAX 7000S devices is used for either boundary-
C0- (1)  Package drawings, standard packing quantities, thermal data, symbolizatio
C00 (24)  The POR remains active until the bandgap reference voltage (Vbandgap) sta
C01 (146)  IC SOP s 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 16 kB
C02 (40)  2008 The conversion process and data acquisition are controlled using CS and
C03 (35)  MIC SOT23-3 00+ 12 Bit Resolution 1.3 GS/s Sampling Rate 4:1 Input Multiplexer Master-S
C04 (372)  O402 KEMET 08+ The DC/DC converter is a programmable topology synchronized Buck conver
C05 (99)  kemet kemet dc02 Notes:  2. TA is the instant on case temperature.  3. See the
C06 (1078)  KEMET ELE AFEU processing begins after this shared session key is agreed upon. The
C07 (14)  MOT QFP-M44P 07+ High-Bandwidth Data Path (up to 500 MHz (1)) 5-V Tolerant I/Os With Devic
C08 (1139)  KEMET ELE Control loop When EN is high, the control circuits become active and th
C09 (84)  INTERSIL A range of silicon varactor diodes for use in frequency control and filt
C0B (1)  HYNIX 02+ DIP-8P Notes:  6. Parameters are guaranteed by design and characterization
C0C (2)  N/A SOT89 06+  The µPA1853 is a switching device which can be driven direct
C0D (1) 
C0E (3)  Specifications based on performance of units installed in an RF microstrip
C0F (1)  This pin represents the output of the charge pump. The voltage at this pi
C0G (7)  In the interest of memory transfer operation applications, the IS93C46A/
C0L (1)  BI 05+/06+ The designer can choose the internally generated reference voltages by co
C0M (5)  The C0M6M1 and C0M6M1 are 4,718,592 bits Syn- chronous Static SRAMs. The
C0N (1)  The following are trademarks of Skyworks Solutions, Inc.: Skyworks®, t
C0P (8)  SONY MP-80 06+ rising edge of the CLK pin. On the falling edge of the 8th clock the da
C0T (1)  These devices combine four popular functions, Power- on Reset Control,
C0X (1)  16 Single-Bit General Purpose I O ports (GPIO)   Modifiable address
C-1 (17)  LUCENT TQFP 1999   These devices employ the Schottky Barrier principle in a large are
C1- (26)  CRITCHLEY 1999 This circuit consists of four independent, high gain, internally freque
C1/ (2)  38 ST 01+ ESD damage can range from subtle performance degradation to complete devi
C10 (906)  TAIYOYUDEN 402 The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 5
C11 (140)  DLI 07+ Note 6: The input bias currents are junction leakage currents which appro
C12 (1190)  OKI 2007 125 kHz RFID Chip for Cards and Tags 256 Read/Write EEPROM Bits, Divided
C13 (119)  memory termination need to switch the load current from zero to full load
C14 (146)  FUJITSU TO-5 00+ By slicing the composite video waveform at 50% of the sync pulse amplitud
C15 (126)  MOT 03+ DIP The MAX5236/MAX5237 precision, dual, voltage-out- put, 10-bit digital-to-
C16 (1215)  TDK 07+ The device fully supports live-insertion with its Ioff and power-up/ dow
C17 (91)  1210 The ATR4258 is a highly integrated AM/FM front-end circuit manufactured u
C18 (343)  KEMET 08+ SelfCTest   The sensor provides a selfCtest feature that allows the
C19 (120)  SONY DIP-8 08+ The Hyundai HYM71V653201 H-Series are 32Mx64bits Synchronous DRAM Modules.
C1A (5)  kuan hsi kuan hsi dc98 2.5% output accuracy (25˚C) Low dropout voltage: 450mV @ 1A (typ,
C1B (1)  97+ TQFP FEATURES Allows Safe Board Insertion and Removal from a Live   C48
C1C (11)  93 3: Regulation is measured at a constant junction temperature using low du
C1D (1)  SOT-23 parts are shipped in tape. The carrier tape is made from a dissi
C1E (2)    The NJU8714 is a stereo BTL outputs switching driver for class D a
C1H (1)  SAMSUNG 0603-15NJ Connecting the Sense(+) and Sense(-) pins to the load circuit allows the
C1J (1)  KOA 05+ Chip Select Input. CS HIGH, deselects the device and the SO output pin is
C1L (1)  VeriFone O7+ The Input/Output logic timing diagram is shown in Figure 1. For proper op
C1M (2)  05+ All signals are TTL levels, including programming sig- nals. Bit locati
C1N (1)  MOT SOP MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to t
C1P (11)  CATELEC MODULE   16Logic low shuts down the converter; high or open for normal oper
C1Q (10)  N/A Notes: 1. All voltages are referenced to VSS. 2. Duty cycle is limited
C1S (1)  Note 1: Absolute Maximum Ratings are those values beyond which the life
C1U (1) 
C1Y (1)  (MAX2700/MAX2701 EV kit (Figure 3), VCC = +2.7V to +3.3V, SHDN = GAIN_SET
C1Z (2)  SEIKO 04+ Where   TJ = Junction Temperature   PD = Total Power Dissipati
C-2 (8)  C The C-2036GSL is a fast SRAM with a nonvolatile EEPROM element incorpor
C2- (3)  True Dual-Ported memory cells which allow simultaneous access of the sam
C20 (1187)  TDK 08+ Write Operation Status Detection The SST39VF160Q/VF160 provide two softw
C21 (122)  NEC 08+ Note 2: Absolute Maximum Ratings are those values beyond which the safety
C22 (129)  Notes: 1. Standard Deviation and Typical Data based at least 450 part sa
C23 (98)  三极管 The active polarity of SHP/SHD (active high or active low) can be chosen
C24 (34)  SMD-8 VTI 02+ Timekeeping supply voltage ranging from 1.45 to 5.5V Low power consumptio
C25 (161)  TO-220 06+ Wait or Transfer Acknowledge. When configured as wait, this signal is as
C26 (59)  MIT 00+   The RC4700 floating-point execution units support single and doubl
C27 (88)  N/A N/A N/A The LM89 is an 11-bit digital temperature sensor with a 2-wire System M
C28 (35)  AMI DIP28 8747 CEL Pb-free products have the same base part number with a suffix added.
C29 (44)  ROCKWELL The MAX 3000A device architecture is based on the linking of highCperfor
C2A (15)  00 A key component that follows the limiting amplifier in a receiver unit is
C2B (14)  40 ST 03+ The ADSP-21365/6 includes an on-chip instruction cache that enables thre
C2C (3)  JAPAN 2000 02+ Brooktree products are not designed or intended for use in life support a
C2E (1)  A/N DIP-8 • International standard package   JEDEC TO-247 AD • H
C2F (2)  SMD-8 VTI 02+ The HYM7V631601B F-Series are Dual In-line Memory Modules suitable for eas
C2G (2)  SMD-8 VTI 02+  Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260 (2
C2H (3)  00 Monitors two analog voltages or thermistor temperature   inputs On
C2K (2)  Hynix HYMD264646B(L)8J-J series is designed for high speed of up to 166MHz
C2M (5)  (LX)high-frequency This MOSFET is an enhancement-mode silicon-gate power field effect tran
C2N (1)  铁帽 • 10-bit, up to 8 channel Analog-to-Digital   Converter (A/D)
C2Q (5)  BEL 0805-1.25A 05+ Reference voltage input. This pin should be driven from an accurate, st
C2S (1)  C1 Commutation Capacitor Negative Terminal. C2 Commutation Capacitor Po
C2Z (1)  This chip, when properly assembled, displays characteristics similar to T
C-3 (27)  MOT 04+ s Anyone purchasing any products described or contained herein for an abo
C3- (34)  N/A ROM space is restricted to 1 kbyte for the PCF84C12A, 2 kbytes for the
C3. (1)  SIEMENS PLCC68 Very low VCE(sat) 1.5 V (typ.) Maximum Junction Temperature 175 C Short
C30 (105)  SANYO TO-92   The power dissipation of the SCC70/SOTC323 is a func- tion of the
C31 (182)  KEMET 05+ The ALUs perform a standard set of arithmetic and logical oper- ations.
C32 (1202)  TDK 2006+ 1) Mount the 0.01µF decoupling capacitor on the component side of
C33 (361)  EPSON BGA 349   Requires 150 Ω resistor in GND connection. The reverse load
C34 (171)  KEMET 05+ NOTES: 1Stresses above those listed under Absolute Maximum Ratings may c
C35 (153)  Note (Read Cycle) 1. tCHZ and tOHZ are defined as the time at which the o
C36 (103)  SANYO TO-126 06+ How to Minimize Aperture Induced Errors As we have seen in the preceding
C37 (86)  06+ SOP-14 The designed amplifier has a measured -1dB input compression point of -24d
C38 (52)  SANKEN 2008 speed 3.3V applications; it can be interfaced to 5V signal environment
C39 (116)  ROCKWELL PLCC-84 07+ The Z86LXX family of IR (Infrared) CCP™ (Consumer Con- troller Pro
C3A (2)  International Rectifiers RADHardTM HEXFET® MOSFET technology provid
C3B (1)  62 ST 03+ • Four Crystal modes, up to 40 MHz • 4x Phase Lock Loop (PL
C3C (7)  TECHNICS SOP 03+ TA = Ambient Temperature TC = Case Temperature TL = Lead TemperatureTJ =
C3D (1)  08+ The PI3C16215 is a 20-bit bus switch with low ON-State resistance. The bu
C3G (1)  toko toko dc03 When low, "A" & "B" data is present on its respec
C3K (1)  MITSUBISHI 603 V+ - Is the power connection for the top of the output bridge. These pin
C3L (1)  • Combine Step-Up and Step-Down for   90% Efficient Boost-Buc
C3N (1)  06+ SOP-5 DC bus capacitor filter with NTC inrush   current limiter IR2132
C3P (10)  06+ SOP-5 Each port has a current-limited 100-mΩ N- channel MOSFET high-sid
C3R (2)  All instructions in the C3R93CNT100UAM perform the same functions as th
C3U (6)  SIEMENS PLCC-68 05+ Bild / Fig. 7 Transienter innerer Wärmewiderstand Transient thermal
C3V (2)  Data Inputs/Outputs: Inputs array data during program operation, when CE
C4- (37)  N/A Systems calibration Electronics level setting Mechanical Trimmers® r
C40 (99)  NEC TO220-3 01+ Due to technical requirements components may contain dangerous substances
C41 (174)  KEMET ELE   100-µA per input   Includes error due to references. T
C42 (104)  EPSON   4.3 Screening. Screening shall be in accordance with MIL-PRF-19500
C43 (124)  KOA 4X4可调   This 18-bit universal bus transceiver is built using advanced dual
C44 (46)  SANKEN TO-3P 06+ The MAX4762CMAX4765 dual SPDT (single-pole/double- throw) switches featur
C45 (246)  TDK SMD 2008 The HYM75V32M636(L)T6 Series are 32Mx64bits Synchronous DRAM Modules. The
C46 (59)  FSC A reset signal is issued if the power supply voltage drops below a preset
C47 (33)  TOS TO-3P 06+ The APA4863 also served well in low-voltage appli- cations , which provid
C48 (28)  TOS TO-220 04+ The high (VH) and low (VL) terminals of the device are equivalent to th
C49 (30)  NEC T0-220 02+ The ADP3181 is a highly efficient multiphase synchronous buck-switching
C4A (2)  The C4ATFBW4400A30K/20/40 supports the SPI bus data transmission protoc
C4B (3)  IR TO220 01+ Discontinuous mode operation provides high efficiency operation at light
C4C (1)  Once the feature is enabled, the data in the boot block can no longer b
C4D (2)    These N-Channel power MOSFETs   are manufactured using the
C4E (1)  DENSO 05+ SMD 5.1 Module Interface Connectors 5.2 Module Connector Pin Configuration 5
C4F (1)  00+  TAOperating free-air temperatureC4085C NOTE 3: All unused inputs o
C4G (2)  The C4GAFUC4400AA1J and C4GAFUC4400AA1J are general-purpose dual channel P
C4H (3)  INTERFACE COMMUNICATION: The IC pin determines which interface is operati
C4I (2)  Unless otherwise noted, VCHG-IN = VDD = 5V, VBATT = 4V. Typical values a
C4K (1)  N/A The ADS8509 is specified at a 250-kHz sampling rate over the full tempe
C4O (4)  Inductance: Measured at 1 volt with no DC current. Inductance Tolerance:
C4P (8)  HAR 92+ PLCC-44P H : High level L : Low level X : Immaterial : Low to high transition
C4R (1)  EBEN selects the functionality of Port 5 and Port 6 When EBEN is low the
C-5 (20)    Designed for broadband commercial and industrial applications with
C5- (38)  N/A The AVR core combines a rich instruction set with 32 general purpose work
C50 (108)  NEC DIP22 0529+ High-side high current switch with active low Enable Up to 2.4A continuou
C51 (69)  SANKEN TO-3P The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory desig
C52 (53)  TOSHIBA TO-3PL 04+ The 80C186EB has integrated several common sys- tem peripherals with a C
C53 (62)  TOS TO3P 05 POWER MOS TECHNOLOGY 2A peak rating HIGH GAIN BANDWIDTH PRODUCT 150MH
C54 (50)  Stresses beyond those listed under Absolute Maximum Ratings may cause per
C55 (70)  CS DIP Compatible with:  • Bellcore GR-30-CORE, SR-TSV-002476,  
C56 (60)  TDK 08+ The module may be disabled by pulling PC below 2.3V with respect to the
C57 (93)  TDK 2220-105M 100V   This 16-bit transparent D-type latch is built using advanced dual
C58 (15)  MIT TO-3P 04+ s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-V
C59 (29)  0408+ • Low forward rise voltage (VF) and satisfactory wave detection &nbs
C5A (1)  4 SOP Pericom Semiconductor Corporations products are not authorized for use as
C5B (4)  21 ST 02+ Stability The IRU1050 requires the use of an output capacitor as part of
C5C (1)    The power dissipation of the TSOP−6 is a function of the dr
C5D (1)    2 MHz (typ.) PWM Switching Frequency   Operates from a single
C5L (1)  The oscillation circuit with the external register generate the clock for
C5V (1)  CLKDs output originates from the cross point switch and goes through a pr
C6- (15)  N/A Applications for the MCP300X family include data acquisition, instrumenta
C60 (40)  06+ SOP-8 The 4-wire serial interface directly connects to SPI™, QSPI™
C61 (17)  TI DIP/40 1999+ The AD5241/AD5242 are available in surface-mount (SOIC-14/- 16) packages
C62 (22)  N/A In a running motor, a current will flow through the resistor RSENSE resu
C63 (23)  FUJI TO-220 Address, data inputs, and write controls are registered on-chip to initia
C64 (23)  NVIDIA BGA 0130C2 † Full range (MIN or MAX) for LM193 is −55C to 125C, for LM29
C65 (70)  NEC SOP24M 2007+ • Plastic package has Underwriters Laboratory   Flammability
C66 (35)  NEC QFP C662GH is the two-wire serial interface EEPROM (Electrically Erasable and
C67 (30)  MODULE MODULE 08+ Input bus select / I2C clock input. The operation of this pin depends on
C68 (29)  2 SSOP Note 1) The specified condition Tj = 25C means that the test should be ca
C69 (53)  N/A DW 04+ This pin is the power side of the external inductor and must be connected
C6A (1)  2008 A start may be issued to terminate the input of a control byte or the i
C6B (2)  19 ST 02+ Notes: 1. Scale is approximately 5ns per division. Sampling rate = 10MHz
C6D (1)    The RA13H4452M is a 13-watt RF MOSFET Amplifier Module for 12.5-v
C6M (1)  Other 07+  Ground planes for the low power circuitry and high power circuitry
C6P (1)  PFC Driver Output. This pin must be connected to the PFC power MOSFET gat
C6R (2)  NSC N/A   Please be aware that an important notice concerning availability,
C6S (2)  EPSON TQFP1414 0104+ "Absolute Maximum Ratings" are those values beyond which the sa
C6V (1)  Functional Description   The internal crystal oscillator uses the ex
C6W (1)  23 VCC (Pin 3): Positive Input Supply Voltage. Supplies power to the interna
C-7 (3)  N/A N/A N/A • C40 to +85C operation • 18 to 36 VDC input   (19 to 3
C7- (5)  2008   Notes to the characteristics 1. The unweighted RMS noise output v
C70 (69)  TOSHIBA 2300 Stresses above those listed under "Absolute Maximum Ratings" ma
C71 (53)  MAXIM 04+ SMD This series of hermetically packaged products feature the latest advanced
C72 (10)  08+   Widebus  Family D A-Port Outputs Have Equivalent 25-Ω
C73 (23)  NEC 03/04+ • Extended Data-Out (EDO) Page Mode access cycle • TTL compa
C74 (38)  MAX SMD 07+/08+ The MSK 5115-00 is an adjustable version in the series of high performan
C75 (13)  CONEXANT QFP 00+   When heavy loads require the OUT pin to sink large currents being
C76 (17)  N/A CAN4 N/A ERASURE: Before a byte/word can be reprogrammed, it must be erased. The
C77 (26)  TI SOP 06+ The device is organized as a 16-bit switch. There are two 8-bit switches
C78 (23)  microsoft microsoft dc02 attributes through memory-mapped control registers (MMRs) an extension
C79 (9)  NEC TO-66 08+ • FT pin for user-configurable flow through or pipeline   ope
C7A (1)  Background An industry leader in high brightness LED technology, Agilen
C7C (3)  SOJ CYPRESS 00+ Device Addressing Following a start condition the master must output the
C7D (2)  Notes: 1. The nominal thermal resistance of a display mounted in a socke
C7L (5)  INTEL PLCC 07+ Once set, SDP will remain active unless the disable command sequence is i
C7P (1)  SOP24 10MHz, 16V, 16V/µs, 8.5nV/Hz at 1kHz 8MHz, 36V, FET Input, 20V/&m
C7S (1)  I2C-bus specification Data transfer I2C-bus pull-up resistors Frequenc
C7V (1)  JPN 2000 05+ Use a high quality ceramic capacitor with low ESL and ESR for best resu
C7W (1)  NSC QFN-10 01-04+ Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
C7Z (1)  LATTICE 00+ PLCC44 Operating with update rates of up to 200 MSPS, the DAC5662 offers excepti
C8- (6)  1. Corrected the errataJan. 10, 2005 2. Revised typical value of ISB from
C80 (426)  SILICON LQFP32 06+ SUC8051F317C8051F317ARY DESCRIPTION The C8051F317 is a 64 C8051F317bit (
C81 (60)  N/A DIP-18 08+ 160´8 data memory RAM Halt function and wake-up feature reduce po
C82 (55)  FUJI TO-3P 05+ The ADM integrates a standard 40- or 44-pin female connector for easy a
C83 (24)  NEC TO-66 08+ DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer
C84 (34)  NS SOP-28 00-01+/SX The PCM1780/81/82 is a CMOS, monolithic, inte- grated circuit, which in
C85 (21)  ROCKWELL QFP1420-100 96+ The IRU1015 is a low dropout three-terminal adjustable regulator with min
C86 (5)  The ARM7TDMI processor operates in little-endian mode in the C868 micro
C87 (33)  QFN-12 04 The CP3SP33 contains a CR16CPlus CPU core. This core improves upon the
C88 (29)  N/A NSC 04+ The disk drive adapter functions of W83877TF include a floppy disk control
C89 (16)  NS 06+ 500 In case the HT9142 is battery powered, when the power supply voltage goes
C8A (2)  AT BGA 99 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis
C8B (2)  N/A 1812 Address, active High. In word mode, these 19 inputs select one of 524,288
C8C (2)  27 ST 02+ The C8C077 is a 3-channel DC/DC converter IC which is designed primarily
C8D (5)  The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary
C8F (9)  mitsumi mitsumi dc The bq2085 uses an integrating converter with continuous sampling for t
C8V (1)  The device is entirely command set compatible with the JEDEC 42.4 single
C9- (1)  Inhibit: The Inhibit pin is an open-collector/drain negative logic input
C90 (49)  BGA 1.2.3 Bit-Level Control Bit-level control over many of the microcontroll
C91 (26)  AMI 04+ I. Devices are 100% production tested at 25C and guaranteed   by de
C92 (13)  97 Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting
C93 (23)  TO-92 08+ NOTES 1VIL is the Logic Control Input. 2Current tested at V IN = 0 V. Th
C94 (19)  ROHM QFP 1999+ Transmitter includes on-chip pulse shaper, B3ZS/ HDB3 Encoder. Pulse leve
C95 (10)  NEC CAN3 The B-port has an output enable, OEB0, which affects all seven drivers.
C96 (11)  NEC CAN3 Unlike conventional keypads, where data is entered by pressing a mechanica
C97 (13)  MicroSemi SOP 97+ To avoid artefacts in moving parts of the picture a motion detector is im
C98 (32)  IMT SMD The TLV245x is a family of rail-to-rail input/output operational amplifie
C99 (11)  SANYO TSSOP20 07+ The BS62LV1024 is a high performance, very low power CMOS Static Random A
C9D (1)  The D2Pak is a surface mount power package capable of accommodating die
C9P (2)  In FM mode the FM mixer, the FM RF-AGC and the 1st IF FM amplifier at pi
C9R (1)  The CY7B9950 RoboClock is a low-voltage, low-power, eight-outpu
C9T (2)  94 SOP The UCCx84-x family of negative low-dropout linear (LDO) regulators provi
C9V (1)  The AHF Series of DC/DC converters feature single or dual outputs over
C-A (3)  AT&T PLCC-84 Display RAM, Character Generator, OLED Driver as well as a wide range of
CA- (73)  TOPPA LIGHT 0102+ Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserv
CA0 (221)  HARRIS DIP 9749 Any existing analog speaker set can easily be upgraded to USB by just i
CA1 (223)  JAT 2520-6脚 05+  1.1 Scope. This specification covers the performance requirements f
CA2 (292)  RCA 03/04+ Floating bootstrap supply pin for the upper gate drive. Connect the boo
CA3 (2114)  HAR 2008 10 years minimum data retention in the absence of external power Data is
CA4 (78)  TRW (LX)high-frequency Input / Output port A. Input / Output port B. Input / Output port C. Ou
CA5 (157)  TRW (LX)high-frequency 6. The Bypass Mode test conditions are required only for the production t
CA6 (55)  N/A N/A N/A The adjustable version of the FAN2502/03 includes an input pin ADJ which
CA7 (140)  PHI 07+ The ISD5008 ChipCorder product can be config- ured via software to opera
CA8 (86)  未提供 2008 The AUTO ON-LINE® feature allows the device to automatically "wak
CA9 (153)  AT TSOP 99+ Note: Some revisions of this device may incorporate deviations from publ
CAA (25)  N/A QFP Writing to the device is accomplished by taking Chip Enable (CE) and Wri
CAB (23)  ADI 07+   The 17517 can drive two motors in two directions one at a time or
CAC (8)  DIP The DAC8551 is a small, low-power, voltage output, 16-bit digital-to-ana
CAD (21)  AMPHENOL 05+ 200-mA RF Low-Dropout Regulator With Enable Available in 1.8-V, 2.5-V, 2
CAE (3)  05/06+ Notes: 1. For Max. or Min. conditions, use appropriate value specified u
CAF (33)  N/A Synchronizer and Baud Rate Selection Linear Receive Strength Signal Indic
CAG (9)  N/A • On-board single power supply (VCC): VCC = 2.7 V to 3.6 V • Or
CAH (8)  TEXAS SOT-153 05+ FEATURES lOptions :-   10mm lead spread - add G after part no. &n
CAI (5)  N/A N/A N/A Local Bus interface Multiplexed with ISA/DMA interface. Low latency as
CAJ (3)  U/ D - Up/Down Control. This input sets the direction of wiper movement.
CAK (34)  N/A TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another
CAL (35)  SIPEX SOT-23 05+ The CP3BT10 connectivity processor is complete micro- computer with all
CAM (20)  N/A (VIN1 = VIN2 = 3.7V, PWR_ON = IN1, L = 2.2µH (LQH31CN2R2M53), CFF =
CAN (20)  00+ The design and specifications are subject to change without prior notice.
CAO (2)  The program cycle has addresses latched on the falling edge of WE or CE,
CAP (113)  yageo 0313+ • Power-on Reset (POR), Power-up Timer (PWRT),   and Oscillat
CAQ (2)  Industry Standard Surface Mount Packages Low Capacitance Diodes Low Re
CAR (37)  05+ SOP-5  − Dynamic Range: 113 dB  − THD+N: 0.001%  &#
CAS (45)  06+ SOP-5 PHASE and ENABLE input terminals are provided for use in control- ling
CAT (3196)  CATALYST 05+ For the most current package and ordering information, see the Package Op
CAU (1)  TI 07+ The transistor must be a small-signal type with a rela- tively high forwa
CAV (12)  AMG SOP16 SOP16 HY57V1294020 is offering fully synchronous operation referenced to a posit
CAW (2)  Hot SwapTM Controller for Positive and Negative Supplies Supply Tracking
CAX (9)  ALPS QFP   A wide input voltage range and integrated thermal and overcurrent
CAY (72)  0402X2   In addition, there is a function below as a PROTECT circuits. &nb
CB- (60)  ENE LQFP-144L 08+   The MP7652 is ideal for digital gain control of high frequency an
CB0 (88)  N/A SOP-20 n BTL mode for mono speaker n 2-cell 1.5V to 3.6V battery operation n
CB1 (108)  MODULE MODULE 08+   The output is capable of supplying 200 mA to the load while confi
CB2 (51)  MOTOROLA 06+ DIP-16 The KA431/KA431A/KA431L are three-terminal adjustable regulator series
CB3 (126)  N/A Two typical applications of the CB322513B are shown in Figures 3A and 3
CB4 (11)  N/A   The TC55V400AFT is a 4,194,304-bit static random access memory (SR
CB5 (9)  98 2A Charge Current USB Compliant Charging States Low RdsON in Discharge
CB6 (17)  IMI TSSOP-16 Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with int
CB7 (23)  PHILIPS O7+
CB8 (11)  PHIEIPS O7+ 5. Dropout is defined as either the minimum control voltage (VCONTROL) or
CB9 (7)  FUJi system under rapidly changing current load conditions, designers general
CBA (7)  N/A INPUT FRAME OFFSET SELECTION   Input frame offset selection allows t
CBB (6)  The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 9
CBC (30)  TAIYO YUDEN 2007+PB The input capacitor CI is necessary for compensation of line influences.
CBD (13)  PHI SOP8S 2007+ Careful design of the output regulator amplifier assures loop stab
CBE (2)  NSEM QFP 06+ Complete implementation of Plug n Play standard   Direct interface
CBF (1)  N/A 0603B   By pulling the VREF/ENABLE lead below 2.0 V typically, (see Figure
CBG (26)  N/A Couples AC and DC signals 0.01 % Servo Linearity Wide Bandwidth, >
CBH (2)  Place component C3 0.080 inches from the package pin. The dc resistance o
CBI (1)  CT: For UCC381-3 and UCC381-5 versions, this is the shutdown pin which,
CBJ (2)  Notes: 1. Operation of this device above any one of these   paramet
CBK (33)  ALPS QFP64 The MT8816 is an analog switch matrix with an array size of 8 x 16. The sw
CBL (12)  MINI 08+ n 100% compatible with VxWorks™, VRTX™, QNX™   Ne
CBM (34)  N/A N/A N/A The tuning input is typically connected to the output of the PLL loop fil
CBN (4)  N/A N/A N/A The SRC input of the bq2060 measures battery charge and discharge current
CBO (20)  NS QFP 01+ • 8/10-bit A/D converter : 15 channels   • Resolution i
CBP (7)  MERRMAC DIP8 WP:Write Protect Input The WP pin when tied low prevents non-volatile wr
CBQ (2) 
CBR (19)  The DAC consists of 16 current sources configured to deliver a 10.24 mA
CBS (70)  ABCO 04+ Remote On/Off: This is an open-collector (open-drain) negative logic inpu
CBT (209)  *This is a stress rating only and functional operation of the device at t
CBU (1)    The safe operating area curves indicate ICCVCE limits of the tran
CBV (2)  HIGH SPEED : tPD = 4.1ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INP
CBW (5)    The MP7652 is ideal for digital gain control of high frequency an
CBX (1)    Each channel consists of a TTL/CMOS-compatible logic input gated
CBY (1)  When the DS1481 first powers up it is in a transparent mode in which th
CBZ (2)    It is general knowledge that different individuals have different
C-C (6)  LUCENT 96+ QFP The STK12C68-20 requires VCC = 5.0V 5% supply to operate at specified sp
CC- (41)  NS O7+ 1-Wire® to USB port adapter for direct connection to notebook and
CC/ (2)  TI TSSOP-24 &KDUDFWHULVWLFV The listed characteristics are ensured over the oper
CC0 (381)  YAGEO 2007+PB MBUS High Data Byte, Bits 8 to 15 Default power up states are defined b
CC1 (333)  NSC PSCK and ASCK are the clocks for the PCM and ADPCM data streams, respec
CC2 (144)  TI 07+   When a transition of the PHASE input occurs, CT is discharged to
CC3 (86)  PHILIPS 05+ All devices are manufactured and tested on a MIL-PRF-38534 certi- fied
CC4 (73)  CC Differential reference clock input. The reference clock input is used as
CC5 (22)  DVRDVS TSSOP 03+ The addition of a bias circuit in conjunction with this process results i
CC6 (49)  TDK new   : When assigning bit operand, K1~K4 are used for 16-bit and K5~K8
CC7 (14)  0402c If the system designer needs more than 16 outputs with the features just
CC8 (51)  S/PHI CDIP14 ——   The FPM transmits and receives at the full Fibre Channel rate of
CC9 (18)  CHIPCON SSOP28 00+ In an NTSC composite video signal, horizontal sync pulses are followed by
CCA (7)  IBM PGA 98+ The R1RW0416D is a 4-Mbit high speed static RAM organized 256-kword 16-b
CCB (6)  MOT PLCC52 05+ The USB specification defines the following five classes of devices, each
CCC (14)  Ground pin. This pin provides a ground for the controller circuitry and t
CCD (12)  BB 07+ This document states the current technical specifications regarding the S
CCE (4)  PHI DIP42 07+ The LM87 is a highly integrated data acquisition system for hardware mo
CCF (522)  KOA 2411 The core as delivered is warranted against defects for three years from p
CCG (2)  The oscillator uses an external, low-cost 32.768kHz crystal. All compen
CCH (7)  Seiko Epson QFP100 04+ Oscillation circuits • On-chip RC oscillation for system clock use.
CCI (19)  N/A 0805L Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Not
CCK (9)  TDK MODULE IN2 is connected to Pin 16 (VCCA). A ferrite antenna is connected between
CCL (14)  ABC SMB 2005 When used with an optocoupler, the AT431 is ideal voltage reference in
CCM (103)  IT 05/06+ The LCX16373 contains sixteen non-inverting latches with 3-STATE outputs
CCN (12)  N/A N/A N/A As the battery accepts charge and approaches the pro- grammed voltage, th
CCO (11)  03+ For the adjustment of the resonance frequency the capacitance of the pro
CCP (59)  N/A 1206   Two independent DMA channels   Programmable interrupt contr
CCQ (1)  N/A SMD-4Pin 08+
CCR (113)  2007   An analog to digital (A/D) conversion can be accomplished with ei
CCS (84)  FAROUDJA QFP 06+ The 16-bit digital output is multiplexed into an 8-bit out- put word that
CCT (32)  IN VISDA 2004 V+ - Is the higher voltage H-bridge supply. The MOSFETS obtain the drive
CCU (43)  ITT N/A The Texas Instruments (TI) translation voltage-clamp (TVC) family
CCV (3)  MIT SOP16S 2007+ * On products compliant to MIL-PRF-38535, this parameter is not productio
CCW (131)  The DAC consists of 16 current sources configured to deliver a 10.24 mA
CCX (1)  5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: tPD = 6.0 ns (MAX.) at VCC
CCY (7)  ST L9913 SMD28 Parameter Voltage input low Voltage input high Voltage output low Volt
CCZ (4)  • Operating temperature from - 55 C to + 110 C • No Base Te
CD- (30)  9 Note: The X prefix in a Motorola part number designates a Pilot Productio
CD0 (84)  HARRIS SOIC-14 07+/08+ NOTES:2911 tbl 09 1. "X" in part numbers indicates power ratin
CD1 (402)  N/A MicroClock has developed a patented technique to integrate a Voltage Co
CD2 (237)  BOURNS 05+ Figure 2 shows a typical test circuit for evaluation of the LM2462. This
CD3 (77)  CD SOP20 07+ Notes: 1. The luminous intensity is measured on the mechanical axis of t
CD4 (3280)  RCA CDIP14 8840 • HiPerFET TM technology   C low RDSon   C unclamped in
CD5 (936)  CDIP The HS-2870 Series of quartz crystal oscillators provide MECL 10K and 10K
CD6 (100)  N/A The EWEN/EWDS instruction will enable or disable the programming capabili
CD7 (3223)  HUAJING DIP-9 06+ Temperature :stg max Test duration : 1000h Temperature : Tstg min Test
CD8 (171)  HARRIS DIP TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another
CD9 (136)  QUALCOMM BGA pulses. This will result in some low frequency ripple, although the LED c
CDA (95)  muRata VOUT = adj (.7V min), 1.2, 1.5, 1.6, 1.8, 1.875, 2.5, 3.3V 2.5V VIN 5.
CDB (96)  COMCHIP 07+ DO-214AC As a member of the SWIFCDBA220L™ family of dc/dc regulators, the C
CDC (643)  Note 2: Operating ratings indicate conditions for which the device is fun
CDD (59)  CATELEC MODULE System and Device Block Diagrams Recommended Companion Components Device
CDE (39)  N/A HUSH LITTLE BABY LITTLE STAR LONDON BRIDGE DREAM OF HOME AND MOTHER
CDF (54)  microtech microtech dc01 This is Preliminary document release. All specifications are subject to ch
CDG (15)  TELEDYNE SOP-16 08+ VREFR− Rch Negative Voltage Reference Output Pin, 1.25V  Nor
CDH (56)  HARRIS 01+ Low Power Consumption Industry Standard Size Industry Standard Pinout C
CDI (15)  N/A DIP-14 08+ Note 2: Dual LDO contains 2 LDO, one is fix output voltage 2.5V or 3.3V (2
CDJ (3)  "Absolute Maximum Ratings" are those values beyond which the sa
CDK (2)  PHILIPS TSSOP20 Inverting analog signal Input. With a 2.0V reference voltage the ground-
CDL (24)  CLEARLOGIC PQFP100 02+ The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5
CDM (47)  INTERSIL DIP 02+ Note: 1. A write cycle occurs during the overlap of a low CS and a low WE
CDN (3)  2008 • High data rate, 1 MHz typical (NRZ) • Free from latch up
CDO (2)  N/A QFP Any existing analog speaker set can easily be upgraded to USB by just i
CDP (379)  HAR CDIP16钢面锡脚 9313 Vcc = 2.7V~3.3V, TA = 0C to 70C / -25C to 85C (E) / -40C to 85C (I), unle
CDQ (4)  QFN 00+ N/A Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, B
CDR (892)    2.1. General. The documents listed in this section are specified i
CDS (51)  COMCHIP 805 These devices, feature an enhanced automatic powerdown function which po
CDT (113)  PHILIPS 2008 Input MUX control input, hold high to select LHP IN or RHP IN (5, 20), ho
CDU (1)    The external compensation capacitor CC is connected between pins
CDV (48)  MICRONAS QFP 07+ 2.2 Initialization procedure After VCC has stabilized, the device will be
CDW (1)  The STK11C88-20 requires VCC = 5.0V 5% supply to operate at specified sp
CDX (11)  SKYSEIKO 5P 05+ † Stresses beyond those listed under absolute maximum ratings may c
CDY (3)  Single or Dual-Supply Operation Wide Range of Supply Voltages   2 V
CDZ (5)  ROHM /0402 Connecting the Sense(+) and Sense(-) pins to the load circuit allows the
C-E (2)  Transistor Q3 and diode D1 (shown in Figure 4) comprise the current mirr
CE- (17)  5 At the low state of the clock a RESET signal is generated which clears
CE0 (115)  MURATA 05+ Restart Interrupts: These three inputs have the same timing as INTR excep
CE1 (209)  HOKURIKU 0805-11.5K 1. Short across terminals Do not short circuit between terminals when r
CE2 (28)  06/07+ APPLICATIONS Ambient Temperature Monitoring (AD7816)   Thermostat
CE3 (17)  S DIP N/A   The MC74AC350/74ACT350 is operationally equivalent to a 4-input
CE4 (16)  NULL DIP- 132 For more detailed information on cabling options including RS485, transfo
CE5 (7)  BOSCH QFP100   When RESET is input during normal operation or during power-down m
CE6 (7)  TI PLCC 07+ 1. Absolute maximum continuous ratings are those maximum values beyond whi
CE7 (32)  PRX SOP The IRU1010 keeps a constant 1.25V between the out- put pin and the adjus
CE8 (12)  DIP28 The direction of counting is set by the watchdog or VCC over- and undervo
CE9 (36)  CET DIP-8 08+ The SSM2402/SSM2412 are dual analog switches designed spe- cifically for
CEA (23)  N/A 0306C The power detector is temperature compensated on the chip, enabling a sin
CEB (107)  SMD-8 04 05 A given load type will have specifications that set Vdc. Choose an availa
CEC (39)  WL TO92 Rise time Reverse recovery time Storage time Soldering temperature S
CED (29)  CET TO251 07/08+ AMDs Flash technology combines years of Flash memory manufacturing expe
CEE (85)  N/A Notes: 1 . Stresses outside the listed absolute maximum ratings may caus
CEF (55)  CET TO220/3 02+ Recovered Serial Data. These ECL 100K outputs (+5V referenced) represent
CEG (23)  CET O7+ FEATURES Allows Safe Board Insertion and Removal from a Live   C48
CEH (9)  NIPPON 2.5x5 NOTE: 8. Provide adequate decoupling capacitance as close as possible to
CEI (12)  sumida sumida dc02 The HT812L0 provides 32 melody/tone sec- tions at maximum. Each section i
CEJ (33)  N/A 0402X2 Potencia nominal asignadaW Tensin nominalVolt Velocidad en vacorpm P
CEK (15)  DAIWA TO92 07+ The small signal gain is larger than 15dB up to 2GHz at the nominal bias
CEL (131)  Spread Spectrum Clock Generator (SSCG) is a frequency modulation techni
CEM (253)  CEM SOP-8 05+ The CEM4946 is a high speed, super low power and 8Mbit full CMOS SRAM org
CEN (28)  CENTRAL SOT-23 05+
CEO (11)  SANYO non-repetitive data patterns. However, the transmission of SYNC patterns
CEP (175)  N/A 2002 TO-220 WRITE ENABLE ( W )   A write cycle is initiated on the falling edge
CER (30)  AMIS PLCC-44P 04+ 2. The inhibit control input is Not compatible with TTL   devices
CES (136)  CET SOT23 08+ This document is a general product description and is subject to change wi
CET (56)  TAIYO 06+ SMD COMPRESSED GCI MODE   In GCI compressed mode, one GCI frame consists
CEU (80)  CET TO The Fairchild Power Switch(FPS) product family is specially designed for
CEV (2)  PAN BGA 04+ • No External Bypass Capacitor Needed • Optimized for Fast Sta
CEW (6)  CET TO3P Piezo-resistive pressure sensors exhibit excellent sensitivity and reprodu
CEX (4)    To provide long life and to insure soft-starting of the lamp, the
CEY (1)    The TC58FVT160/B160A is a 16,777,216-bit, 3.0-V read-only electric
C-F (3)  AD 06+/07+ SUMMARY DESCRIPTION The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-v
CF- (19)  SONY If, after the ISL6118 has latched off, and the fault has asserted and the
CF/ (1)  NOTES 1See the Terminology section. 2Temperature range (A, B Version): C
CF0 (53)  ST QFN 06+ Loop enable. When LOOPEN is high (active), the internal loop-back path is
CF1 (385)  KOA n/a 98  Output current while on 1  Output current while on 2   T
CF2 (46)  N/A The Hynix HYM76V8C755AT8 Series are 8Mx72bits ECC Synchronous DRAM Modules
CF3 (94)  ERICSSON PLCC- Table as shown lists type numbers, which indicate a tolerance of +/-20% wi
CF4 (84)  N/A 1812 Memory interface  Can address up to 64 K bytes of External Program
CF5 (39)  RS Cycle Time RS Pulse Width(2) RS Set-up Time RS Recovery Time RT Cyc
CF6 (229)  TI 89 DIP塑封中片 The CY7C4261/71/81/91V provides four status pins: Empty, Full, Programma
CF7 (191)  TI PLCC 03+/04+ Note 2: ∆VOD and ∆VOC are the changes in VOD and VOC, respecti
CF8 (11)  The SOA curve should be interpreted as an absolute maxi- mum rating. Ope
CF9 (20)  ti ti dc91 The SiP280X family includes six high-speed, low power consumption, BiCM
CFA (4)  ST 03+ TQFP64 The on-chip 264-bit EEPROM (8 block, 33 bits each) can be read and writte
CFB (14)  9724 For enhanced performance, the VRE3041 has an external trim option for use
CFC (13)  QFP100 It supports 0 to 22.5 dB gain with 16 steps and 1.5dB/step. The gain valu
CFD (5)  95+ 10 Reset Input (RP). The Reset input provides hardware reset of the Flash c
CFE (11)  TDK This product is specifically designed as a final stage for 802.11a equipm
CFF (8)  ST 07+ To set the new VTRIP voltage, apply the desired VTRIP threshold to the
CFG (2)  MURATA The AUDOUT pin is always at 1.2 volts when the device is powered up. Wh
CFH (13)  3. Processing before Initialization Note: When power is first supplied,
CFI (1)  The 318 decoders are a series of CMOS LSIs for remote control system app
CFK (14)  CELERITEK (LX)high-frequency The HIP6601 and HIP6603 provide the user total flexibility in choo
CFL (5)  YAGEO 603 Output channel data strobe input terminal: in the Normal Mode phase, seri
CFM (17)  MURATA 99+ Stresses above those listed in Absolute Maximum Ratings may cause permane
CFO (2)  The XC4000E family is a superset of the popular XC4000 family. For a de
CFP (15)  CET TO220/3 The IEEE 1284 specification requires both termination and EMI filtering
CFR (349)  PH 07+ 3.3V Operation with 5V Tolerant Buffers ACPI 1.0b/2.0 and PC99a/PC2001 Co
CFS (45)  NS DIP-14 • Built-in five protection functions. (over-current, over-voltage, l
CFT (12)  TI QFP 07+ The fixed 2.5-V output controller uses an internal temperature-compensate
CFU (53)  N/A   Designed for PCN and PCS base station applications with frequencie
CFV (3)  Blackfin processors support a modified Harvard architecture in combinati
CFW (28)  MURATA Tip provides half of the two-wire connection to the telephone network, RJ
CFX (5)  muRata DIPP 03+ The LM3200 is a DC-DC converter optimized for powering RF power amplifi
CFY (9)  arco arco dc00 SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIM
CFZ (2)  There is an internal diode from each pin to VEE. This diode will conduct
CG- (7)  PS 2057 99+ Model AD5380BST-5 AD5380BST-3 AD5384BBC-5 AD5384BBC-3 AD5381BST-5 AD
CG0 (18)  BOURNS 603 05+ VDETDetection Voltage Compliance RDETMINMinimum Valid Signature Resistanc
CG1 (31)  ST 00+ TQFP-M100P The digital inputs are CMOS-compatible and equipped with a built-in pull-
CG2 (87)  H 00+ SOP-16 0.368 x 1.136 Microstrip 0.151 x 0.393 Microstrip 0.280 x 0.220 Micro
CG3 (53)  COPPERGATE 2005 BENEFITS EMI symmetrical (I/O) low-pass filter High efficiency in EMI
CG4 (37)  PHILIPS O7+ The MHF converters are switching regulators which use a quasi- square wa
CG5 (96)  CY SOJ ✔ ESD Protection > 40 kilovolts ✔ 500 Watts Peak Pulse P
CG6 (81)  PHI QFP64 07+ loaded into the device. After the last bit of the opcode is shifted in, t
CG7 (32)  Mono 1.5W BTL or stereo 300mW output Logic controlled headphone sense
CG8 (19)  HAR PGA Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Not
CG9 (8)  Sig DIP 91 The DRAIN SENSE input monitors the voltage at the drain of the external
CGA (25)  SIRENZA 2. Tolerance on the true position of the leads is 0.065 mm maximum. 3. P
CGB (6)  TRIQUINT MSOP10 03+ The HIP6017 provides the power control and protection for three output
CGC (3)  FUJITSU (LX)high-frequency Information contained in this publication regarding device applications
CGD (8)  NXP N/A 08+ The K6R4016C1C is a 4,194,304-bit high-speed Static Ran- dom Access Memor
CGE (1)  • Especially suitable for applications from   400 nm to 1100
CGF (7)  N/A The Intersil ISL83699 device is a low ON-resistance, low voltage, bidire
CGG (2)  The device provides a JEDEC-approved optional software-protected data writ
CGH (4)  N/A 1210 VCC is the positive power supply of the device core and input circuitry.
CGI (1)  Hynix HYMD264726B(L)8-M/K/H/L series incorporates SPD(serial presence dete
CGJ (1)    While the LH28F008SA requires an operation to com- plete before
CGL (2)  TAIYO 0603(圆柱) 05+ The device provides up to 16 inputs and 8 outputs. The PALCE16V8 can be e
CGM (2)  The CGM020M1 aligns the recovered data clock frequency to the reference c
CGO (7)  The MX841 is specifically designed to be operated from a single cell batt
CGP (4)  VISHAY FUNCTIONAL DESCRIPTION STAND-BY STATE The external capacitor,Cx, is ful
CGQ (1)  The CZ80CPU is designed to run at frequencies up to 80 MHz on a typical 0.
CGR (11)  NEC PLCC32 Picture Structure Improvement including Color Transition Improvement, L
CGS (121)  FAI SMD SMD The TLV2252/4 also make great upgrades to the TLV2322/4 in standard desig
CGV (1)  The IS93C46A/56A/66A is very popular in many high- volume applications
CGY (60)  PHILIPS SOP16 96+ The WEL bit controls the access to the CCR and mem- ory array during a
CH- (11)  NA 03+   Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)   Input
CH0 (78)  CHANGHO DIP A burst write access to an active row is initiated with the WRITE comman
CH1 (41)    This series of Zener diodes is packaged in a SOD−323 surface
CH2 (41)  ET1-1-75-3TR Serial Data (SDA) SDA is a bidirectional pin used to transfer data into
CH3 (43)  2000 90% Efficiency High Supply Capability to Deliver 3.3V 100mA  with
CH4 (58)  K 01+ 5. Diagnosis output (pin(25))   The diagnosis output terminal of pi
CH5 (36)  The figure below illustrates the relationships between the families. Co
CH6 (4)  CHENMKO SOD-323 05+ This is a dual function pin. In the IDT Standard mode, the FFC function is
CH7 (181)  TQFP Hynix HYMD132725B(L)8J-J series incorporates SPD(serial presence detect).
CH8 (24)  CHENMKO SOD-323 05+ The HY29F040A can be programmed and erased in-system with a single 5-vo
CH9 (99)  IC SOP The ISL422XE features an automatic powerdown function that powers down t
CHA (52)  NISSEI N/A State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera
CHB (38)  N/A 0603B TIMER (Pin 5): Timer Set Pin. The timer period is set by a capacitor (CTI
CHC (4)  JAT 4532-80R 05+ PLL1, CLKA, and CLKB each have multiple registers supplying data. Program
CHD (26)  SOSHIN 05+   Refer to Figure 20 for performance into a lighter load.   Se
CHE (23)  SAGE QFP 01+ Footnotes: 1) Standard frequency stability (20,25,50ppm & others avai
CHF (7)  N/A 0603L FEATURES • Internal Short Circuit Current Limit • Internal T
CHG (14)  JRC DIP 07+ Technology Corporation product best suited to the customer's application;
CHH (2)  N/A *7: V is input pulse voltage (refer to figure 8). *8: trf is the clock p
CHI (23)  N/A 0805L CHIP ENABLE The CE input is the device selection control. When the device
CHJ (3)  NEC 1997 The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector ca
CHK (3)  The bar antenna is a very critical device of the complete clock receiver
CHL (6)  N/A Decoupling capacitors of 0.01 µF should be connected between each
CHM (17)  SOP These devices operate from a single supply of +2V to +12V and are optimiz
CHN (18)  ST DIP 03+ Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
CHO (5)  = Essential Part Number = Standard Device = Top Threaded version = T
CHP (120)  COPAL SOT 05+ The clock driver serial protocol accepts byte write, byte read, block wri
CHR (28)  KOA SOP 00+ • Guaranteed AC performance over temperature and   voltage:
CHS (33)  COPAL SOP4 05+ Electrically-insulating, thermally-conductive "pads" may be in
CHT (60)  ChangHong DIP E1 is the hexadecimal address for the CMX866 Transmit Mode register, and
CHU (6)  The Automatic Shut-Off is a safety system which turns off the electrical
CHV (11)  N/A 4 channel 10-bit resolution A/D conversion time : 15.2 µs (MB899
CHW (2)  N/A The 312 decoders are a series of CMOS LSIs for remote control system app
CHX (5)  CALIBRE INC 00+ The voltage drop (VSR) across the sense re- sistor RS is monitored and i
CHY (3)  required to support 10 Mbps data transfer speeds. A compliant IEEE 1149
C-I (1)  Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Ope
CI- (108)  N/A 0402L The MAXQ3120 microcontroller is a high-performance, 16-bit microcontrolle
CI0 (5)  12 MRT 03+ The alternative devices are the recommended replacement devices for the ph
CI1 (15)  N/A 0603L This is a single positive-edge-triggered D-type flip-flop. When data at t
CI2 (14)  3. The standby control input is NOT compatible with TTL   devices
CI3 (13)  TRIO 1206-4R7K 05+   C High-performance 32-bit RISC Architecture   C High-density
CI4 (11)  4m-220 Information For further information on technology, de- livery terms and
CI5 (7)  N/A SOJ-28 99 POWER - Enciende o apaga el TV (la tecla POWER en el panel del TV debe pe
CI6 (24)  JAT 6M-8R2 05+ In the IDT Standard mode, the FF function is selected. FF indicates whet
CI8 (12)  N/A Single Voltage, Range 3V to 3.6V Supply 3-Volt-Only Read and Write Operat
CI9 (2)    This low failure rate represents data collected from Maxims reliab
CIA (14)  N/A NMOS linear image sensors are self-scanning photodiode arrays designed sp
CIB (12)  N/A 0805BEAD Notes: 1. With 50% of the outputs simultaneously sinking 12 mA, up to a
CIC (177)  ERSO 8625 PGND: This is the high current ground for the IC. The MOSFET driver tran
CID (8)  CIDC QFP 07+ s Digital Tuning of Crystal Frequency s PROM for Storing Frequency Corr
CIE (2)    The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS F
CIF (48)  sicsafco sicsafco dc00 The CD74AC623 is supplied in 20-lead dual-in-line plastic packages (E suf
CIH (76)  0402L The SDA is a Bi-directional pin used to transfer addresses and data into
CII (5)  N/A N/A   The performance over temperature is achieved by inte- grating th
CIJ (1)  MODULE MODULE 08+ † Not more than one output should be tested at a time, and the dura
CIL (58)  This IC functions in a variety of CPU systems and other logic systems, to
CIM (133)  A buffered output-enable (OE) input can be used to place the eight output
CIN (1)  Hynix HYMD216M726A(L)6-J/M/K/H/L series is designed for high speed of up
CIP (20)  ST 1660 05+   In the intended application, it is expected that the transmitter
CIQ (6)  1206 The product term allocator is a dynamic, configurable resource that shift
CIR (9)  - SMD 07+/08+ The noise of Q1A and Q1B would normally be quite signifi- cant about 6 n
CIS (46)  Midcom 00+ POWER GOOD COMPARATOR  Undervoltage Threshold  Overvoltage Thr
CIT (29)  TSSOP   voltage mode control • Vcc Over-voltage protection (latched)
CIU (1)  Infiniium has received eight industry awards to date, including EDNs Inn
CIV (4)  SYSTEMS 92+ The CIV1000 MK2 consists of a tuner section and an IF section, which ar
CIW (1)  NOTES:  1. Dimensions are in inches. Metric equivalents are given f
CIX (1)  TELCOM 01+ Three UART serial ports for data/testing/Bluetooth USB (version 1.1) Ana
CIZ (3)  AMIS PQFP-208P 02+ DATA POLLING: The AT49BV/LV040 features Data Poll- ing to indicate the e
CJ- (2)  Centillium Communications 03+ Integrated Multifunction PCI-To-ISA Bridge - Supports PCI up to 33 MHz
CJ0 (5)  HITACHI Modulus control output for controlling an external dual-modulus prescaler
CJ1 (63)  N/A N/A N/A This device is particularly well suited for portable elec- tronics (e.g.
CJ2 (17)  ICS SSOP-48 D Auto Selection of S/E or LVD SCSI Termination D 2.7-V to 5.25-V TERMPW
CJ3 (11)  ICS SSOP-48 Notes: 1. Exceeding the Absolute Maximum Ratings may damage the devices.
CJ4 (15)  SGS-THOMSON SIP15 94+ 1) Worst case package 2) Max number of output defined as (n). Data inpu
CJ5 (8)  9501+ tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setu
CJ6 (1)  45 ICS O3+   The two-tone IMD test signal can be generated by a number of mea
CJ7 (32)  ICS 2001 DESCRIPTION Input reference frequency, 5V tolerant input Buffered clock
CJ8 (10)  NS SOP-20 00+/SX Up to 10.7 Gbps operation Very low power: 670 mW (IBIAS = 40 mA, IMOD =
CJ9 (4)  ST 04+ QFP TEMPERATURE COMPENSATION   Figure 2 shows the typical output charac
CJA (2) 
CJB (1)  TV COMPOSITE VIDEO MUTE The TV composite video outputs can be muted by p
CJD (20)  2000 CEM 95+ also allows power consumption to be reduced by leaving the separate VEE
CJF (1)  cdil cdil dc0307
CJG (3) 
CJP (2)  The LTC ®1698 is a precision secondary-side forward converter control
CJR (3)  ICS SSOP28 07+ 1. Permanent device damage may occur if the ratings in Absolute Maximum R
CJS (3)  COPAL SALE--STOCK!! 08+ The Intersil ISL84715 and ISL84716 devices are low ON-resistance, low vol
CJT (4)  JIANGSU 04+ The UC1854 provides active power factor correction for power sys- tems t
CJV (9)    Surface mount board layout is a critical portion of the total des
CJY (2)  N/A SOP24W 07+ The CJY3P104 is a double input matched COMMON EMITTER broadband transist
CK- (7)  03 Stresses greater than those listed under Absolute Max- mum Ratings may
CK0 (108)  AVX CORP Power Good output. This is an open drain output and functions as a supply
CK1 (111)  avx avx dc72+ The short circuit current detection is programmable through a single resi
CK2 (36)  QFP 2001 - Single 10V to 40V Supply Application - 1.25V + 2.0% Voltage Reference.
CK3 (22)  SOP16 06+ International Rectifiers R5 TM technology provides high performance pow
CK4 (36)  CANON BGA N/A • Low Dropout Voltage 1.2V at 1.2A • Adjustable or Fixed Volt
CK5 (5)  SOP24 06+ 2) A single check bit error will cause that particular check bit  
CK6 (5)   The CK62000J is a high speed, super low power and 4Mbit full CMOS
CK7 (8)  N/A N/A Timer T2 may be read on the fly but possesses no extra read latches, an
CK8 (1)  † Design targets only. Not tested in production. NOTE 4: In the e
CK9 (1)  ICC1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates
CKA (2)  • 10-bit Analog-to-Digital Converter module (A/D)   with: &n
CKB (24)  ST SOP28 The bq2083−V1P2 contains 512 bytes of internal data flash memory,
CKC (122)  The S-Bus is a four wire, full duplex, time division multiplexed transmis
CKD (47)  N/A The amplifier family has an output that swings within 50mV of either supp
CKE (3)  Fujitsu Flash technology combines years of Flash memory manufacturing exp
CKF (6)  TI TSOP24 2007+ In software control mode (only when using external trigger), if the START
CKG (14)  TDK 1812 0545   The SOA curves combine the effect of these limits and allow for i
CKK (2)  HYNIX 00+ The step-down controllers minimize power loss and noise by operating the
CKL (3)  Comparator hysteresis can be increased with the addition of resistor RH.
CKP (19)  may be accessed by hardware or software operation. The hardware operatio
CKR (129)  AVX DIP 6 Since the device will not acknowledge during a write cycle, this can be u
CKS (9)  01+ SOP   Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.  
CKT (2)  TQFP 04+ n 20 to 75 MHz shift clock support n 50% duty cycle on receiver output
CKU (1)  TEXAS When accessing the FM25L16, the user addresses 2,048 locations of 8 dat
CKV (16)  TI SMD8 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
CKX (1)  TDK 05+ Notes: 1. The luminous intensity is measured on the mechanical axis of t
CKY (1)  skyworks 07+ Caution: A low DC resistance ground may not be a good ground. Lightning c
CL- (779)  TAICHAN SMD 06+ • Reverberation and echo effects of audio equipment such as radio &
CL/ (1)  CL SOP- 8 500 MH z Gai n Noi se Fi gure Output IP3 Output P1dB Input Return Los
CL0 (154)  N/A 0402c SDA is a bidirectional pin used to transfer data into and out of the de
CL1 (438)  SAMSUNG 4K/R RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Near
CL2 (537)  SAMSUNG 0016+ PGND(Pin 8):Connect all power ground components to a PGND plane which sh
CL3 (272)  SAMSUNG 08+ The DS1543 also contains its own power fail circuitry which automatically
CL4 (141)  96+ SOP-8 AP1604 can be soft-start with a proper capacitor connected between CE/SS
CL5 (37)  NS SOP8 N/A 1.1 AM/FM-Receiver • High flexibility with an external preamplifier
CL6 (42)  XLINK DIP 06+ The MicroMonitor is a precision temperature-compensated reference and comp
CL7 (25)  CORELOGIC BGA 04+ AD0CAD7 - Multiplexed Address/Data Bus N.C.- No Connect MOT- Bus Type Se
CL8 (34)  CORELOGIC 06+ These unconditionally stable amplifiers are designed for use as general
CL9 (23)  CL 04+ Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
CLA (381)  MITEL DIP 97+ This integrated circuits is manufactured on a CMOS process. It can be dama
CLB (15)  GONGJING N/A The product identification mode can be used to identify the device and
CLC (533)  03+ Once the initial conditions have been satisfied, both pulsing methods will
CLD (101)  2008 PCM input C 102 dB of Stopband Attenuation C Supports Sample Rates up to
CLE (23)  SMD 04+   Unit-to-Unit Propagation Delay Skew POWER SUPPLY   Positive
CLF (8)  This package is fully binned by color and intensity, except for red c
CLG (75)  N/A NSC 04+   This low failure rate represents data collected from Maxims reliab
CLH (47)  N/A 0603L Tominimizetotalpowerconsumption,the CLH1608T-56NK-S/CLH1608T-56NK-S auto
CLI (12)  caldera caldera dc01 The ADP3041 is a fixed frequency, PWM step-up dc-to-dc switching regulat
CLK (14)  N/A N/A N/A The MAX4380CMAX4384 family of op amps are unity- gain-stable devices that
CLL (35)  TDK DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs  
CLM (64)  CAL The OPA820 provides a wideband, unity-gain stable, voltage-feedback amp
CLN (3)  XC9500XV CPLDs are also 1.8V I/O compatible. The X25TO18 setting is provi
CLO (2)  QFP-100 When read enable input RE is L, the contents of memory are output to da
CLP (107)  ST SMD SOP8 DESCRIPTION The 74LCX257 is a low voltage CMOS QUAD 2 CHANNEL MULTIPLEX
CLQ (39)  N/A   The RST pin is normally driven high and will be clocked low when
CLR (20)  GPS 94-95+ Signal Processor (DSP) TMS320C6701 C 8.3-, 6.7-, 6-ns Instruction Cycle T
CLS (78)  N/A -1774.50 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -177
CLT (185)  MITEL QFP1420-100 00+ The component placement around the LDO should be done carefully to achie
CLV (60)  TI 07+ Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock
CLX (57)  AD 93 DIR input. The enable input G can be used to disable the device so that
CLY (14)  SEME This input is used to place the NCP631 into shutdown mode. The NCP631 is
CLZ (1)  The TPS2148 meets USB 2.0 bus-powered peripheral requirements. An integ
C-M (2)  N/A PQFP-144 99 All output buffers provide a programmable Open-Drain option which allow
CM- (21)  N/A USB specification v.1.0 compatible Intel UHCI (Universal Host Controller
CM. (1)  NOTES: 1. All typical values are at VCC = 5 V, Tamb = 25 C. 2. This is
CM0 (327)  KYOCERA 02+ 8 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board ea
CM1 (766)  AVX 4K/R The M25PE80 is an 8 Mbit (1Mb x 8) Serial Paged Flash Memory accessed b
CM2 (617)  AVX 805 The DVI processor includes a low jitter PLL for generation of the high
CM3 (481)  CAMD SOT23 04+ Voice within each group are combinations of different fixed memory secti
CM4 (214)  N/A Reading from the device is accomplished by taking Chip En- able (CE) an
CM5 (136)  PRX SOP Short lead time, since the P2ROM is programmed at the   final stage
CM6 (92)  N/A DIP 94 The brightness of the LEDs can be easily controlled by injecting a PWM
CM7 (136)  06+ DIP-24 The RC2207 is designed to operate over a power supply range of +4V to 1
CM8 (166)  NULL SMD 117 This module generates a slow System Clock (32.768 kHz) from an optional
CM9 (19)  1735 Input and Output Voltages With 3.3-V VCC) Typical VOLP (Output Ground Bou
CMA (115)  N/A N/A N/A † Stresses beyond those listed under "Absolute Maximum Ratings&
CMB (32)  N/A PLCC 06+ Device programming occurs by executing the program command sequence. Th
CMC (107)  TOSHIBA 07+ :3 LQSXW ² :ULWH SURWHFW :3  IXQFWLRQ DOORZV SURWHFWLRQ RI
CMD (282)  N/A Driving SNOOZE low, programs the device into the snooze mode. In this mod
CME (27)  SHINDENGEN DIP 07+ This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configurat
CMF (629)  N/A The LTC6903/LTC6904 feature a proprietary feedback loop that linearizes t
CMG (6)  TOSHIBA 1210 04+NOPB7700 A differential analog voltage input allows increased common-mode rejectio
CMH (13)  FAIRCHILD SOD123 In order to facilitate data busing, three-state outputs (Q0 to Q3) are p
CMI (64)  E3DX QFP100 The READ command selects the bank from BA0, BA1 inputs and starts a bur
CMJ (5)  NS PLCC 99+ The Solutions960® program features a wide variety of development too
CMK (22)  03+   The MPC92429 is a 3.3V compatible, PLL based clock synthesizer ta
CML (27)  N/A
CMM (93)  N/A 05+ 3808
CMN (1)  H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelev
CMO (157)  SOP8 The CMO1078 supports two hardware interfaces: The FWH/LPC interface for I
CMP (403)  AD DIP 01+ Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserv
CMQ (2)  QFP44 NOTE: Intersil Pb-free products employ special Pb-free material sets; mold
CMR (99)  CENTRAL SMA 06+ Data is clocked on the negative transition of the CLOCK waveform. If less
CMS (150)  MHS PLCC-52 N/A Active Low Control Input. This is the frame synchronization signal for th
CMT (76)  CET TO-   Guaranteed Low Skew < 25ps (max)   Very low duty cycle dis
CMU (9)  MHS SMD 96 C 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-   er (activa
CMV (6)  • Viewing Angles Match   Traffic Management Sign   Requi
CMW (62)  N/A The MGA-71543 is designed for CDMA and W-CDMA receiver systems. The IP3,
CMX (105)  CITIZEN 2007+PB Audio Performance −90dB SNR (A weighted @ 48kHz) ADC −100dB
CMY (11)  TRIQUINT 04+HOT   These devices are designed to be used as encoder/decoder pairs in
CMZ (13)  Centralsemi 07/08+ Two external power supplies are required to operate the RB-TK2051: VCC (re
C-N (1)  During discharge and charge, the bq2050 monitors VSR for various threshol
CN- (4)  N/A 1.2 ARCHITECTURE The COP8SAx family is based on a modified Harvard archi
CN. (1)  DESCRIPTION The 74VHCT03A is an advanced high-speed CMOS QUAD 2-INPUT
CN0 (31)  S+M 0603-17V 05+ Note 1: Absolute Maximum Ratings are those values beyond which the life
CN1 (371)  KOA 05+ 3V to 14.5V input voltage range Adjustable output voltage down to 0.8V
CN2 (235)  KOA 05+ Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input
CN3 (40)  0603X5(10P8R) A constant 500nA current source ramps up the switchs gate causing a volta
CN4 (29)  SIG DIP-24 08+ Notes: 1. Propagation Delays and Enable/Disable times are with Vcc = 3.3
CN5 (16)  1 CANUM O4 Enables the associated DDR2 SDRAM command decoder when low and disables th
CN6 (22)  04 FLAG2 options - 3Hz flash - 6Hz flash - Busy output - OFF 2 keys Key
CN7 (19)  VIA BGA 07+ !Features 1) Built-in overvoltage protection circuit, overcurrent protect
CN8 (96)  MINDSPEED BGA 07+ • HFBR-5701L: Dual specified 1.25   GBd Ethernet (1000BASE-SX)
CN9 (11)  CONEXANT BGA 02+ While the TLV320DAC23 supports the industry standard over-sample rates of
CNA (17)  Panasonic Also See: • HEDS-9000/HEDS-9100   Encoder Module Data Sheet
CNB (28)  PAN SOP-4 Certain applications using semiconductor products may involve potential r
CNC (13)  PAN SOP16 01+ Load strobe input for a 12-bit address/data: A high level on the LD pin
CND (76)  0603X5(10P8R) An active high input from an external circuit which latches a Chassis I
CNE (5)  TEXAS BGA 06+ implement logic functions in the 500- to 800-gate-array complexity. Since
CNF (23)  603 NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Twos Comp
CNG (2)  QTC DIP-6 96年 The TLE 4476 is a monolithic integrated voltage regulator providing two o
CNH (14)  N/A The MAX1282/MAX1283 12-bit analog-to-digital convert- ers (ADCs) combine
CNJ (1)  Capacitance of Schottky diode quads is measured using an HP4271 LCR mete
CNK (9)  APLS QFP 00+   The SN74LS245 is an Octal Bus Transmitter/Receiver designed for 8
CNL (2)  ericsson ericsson dc00 Real-Time Sensing Quantitative Analysis† Internal Fault Detection&
CNM (5)  2007 The LS323 is an 8-bit universal shift storage register with TRI-STATE ou
CNN (4)  TDK SOP Controller (host) will send start bit. Controler (host) sends the read
CNO (1)  These devices can be used as two 8-bit transceivers or one 16-bit transce
CNP (3)  ON 02+ FEATURES The SP304 is a proprietary single-chip device that contain bo
CNR (10)  - - - The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS analog-to
CNS (10)  VISHAY ISSUE 2 - JANUARY 1996 FEATURES * Extremely low equivalent on-resistance
CNT (9)  The READ instruction will stream out data at a specified address on the D
CNV (1)  TI 07+ • Two processing elements, each made up of an ALU, Mul-   tip
CNW (38)  FAIRCHIL DIP6 07+ The intended application of this device and signaling technique is for po
CNX (130)  FAIRCHILD DIP-6 05+ The device incorporates auto-calibration and built in self test (BIST) ro
CNY (558)  Fairchi 05+ Offered in 64Mx8bit the K9F1208X0B is 512M bit with spare 16M bit capacity
CNZ (10)  N/A 0402X4 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value
CO- (13)  SUMIDA Transfer can be started from MSB or LSB Supports internal clock synchro
CO. (1)  The MAX5075 is a +4.5V to +15V push-pull, current-fed topology driver sub
CO1 (75)  infineon 03+ Standard Definition Programmable Features   16 Oversampling  
CO2 (8)  87 - Updated SPI electrical characteristics. - Updated Derivative Differen
CO3 (4)  NS A flexible clock generation system enables the software to control the cl
CO4 (60)  FAIRCHILD SOP-14 N/A The CO40938CMA biphase, current mode controller is de- signed to work wit
CO5 (7)  PHILIPS TSOP32 Ultra low dropout voltage (270 mV @ 3A typ) Low ground pin current Loa
CO6 (52)  raltron raltron dc03 How to Write: • Controller (host) sends a start bit. • Cont
CO7 (5)  Parameter Positive Supply Voltage (VCC) Voltage on +12 V VIN Pin Volta
CO8 (7)  TI SMD-8 99+00+
CO9 (1)  Note a: Stresses greater than those listed under "Absolute Maximum
COA (5)  PHI PLCC 2002 The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, powe
COB (12)  Fairchild SOP-8 07+ Supply voltage for the LNA, bias circuits, and control logic. External RF
COC (3)  95 Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supp
COD (11)  MOTOROLA SMD 05+ * On products compliant to MIL-PRF-38535, this parameter is not productio
COE (5)  15) Sweep the power supply to 5.5V. Verify that the LED   module rem
COF (42)  This pin provides a 6 µA current source to linearly charge an exte
COG (11)  Microchip 06+ 2400 Thermal Design The IRU1010 incorporates an internal thermal shutdown tha
COI (4)  0805L   The MSK 4362 is a complete 3 Phase MOSFET Bridge Brushless Motor C
COJ (4)  KYOCERA 3X3-100K 05+   Widebus  Family D A-Port Outputs Have Equivalent 25-Ω
COL (4)  SMD-16 Semelab Plc reserves the right to change test conditions, parameter limits
COM (256)  Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V 13 bidirec
CON (46)  HMIETEC 91+ When handling individual devices (which are not yet mounted on a circuit
COO (1) 
COP (949)  NS DIP 06+  − Provides 22 kbits dedicated melody ROM   − Prov
COR (16)  AMIS SOP N/A NOTES: • Use a 0.1 µF capacitor on VDD to decouple the power
COS (26)  COSMO SOP4 The reference included in the RC5051 is a precision band- gap voltage re
COT (9)  N/A DIP 1995   In order to maintain the lowest output resistance and output ripp
COU (4)  Ti QFP 96+ The MT3x7xBs are high performance and low power consumption DTMF receivers
COV (1)  The EMC1002 generates two separate interrupts with programmable thermal t
COW (1)  TRI-TRON Hynix HYMD216646(L)6-K/H/L series incorporates SPD(serial presence detect)
COY (4)  DIP 00+ Note 1: Absolute Maximum Ratings are those values beyond which the life
CP- (45)  SEAGATE SOP8 04+ Full piconet support. On board 4Mbit or 8Mbit external Flash. Very low p
CP0 (125)  AVX HY5V66GF is offering fully synchronous operation referenced to a positive
CP1 (133)  2008 Note A: All Characteristic data in the above graphs has been developed fr
CP2 (114)  MIT QFP 00+ Notes: 1. Stresses above those listed under Absolute Maximum Ratings may
CP3 (74)  rohm rohm dc94 − Two Full Function Serial Ports − High Speed NS16C550A Com
CP4 (25)  AGERE These 8-bit latches feature 3-state outputs designed specifically for dri
CP5 (135)  CHIPHOMER 0636(PB)   (16bit format, serial interface) - Long Frame / Short Frame are se
CP6 (51)  Case: JEDEC TO-220AC, ITO-220AC & TO-263AB molded plastic body Term
CP7 (8)  ROHM TO-92 95+ The read or write mode is selected through W. A logic high on W selects t
CP8 (117)  IT 450 Edition 07.96 This edition was realized using the software system FrameMa
CP9 (30)  QCOMM BGA N/A VIN = 5V VIN = 3V RL = 10Ω each output RL = 10Ω each output
CPA (15)  intersil intersil dc04 The LP2950-5.0 is available in the surface-mount D-Pak package, and in
CPB (9)  SMK 2002 use by multiple AHB Bus Masters 32-bit 66/33 MHz PCI Host and Satellite
CPC (276)  CLARE SOIC-16 0020 Erase Suspend enables the user to put erase on hold for any period of t
CPD (19)  CITIZEN 1206
CPE (5)  25 PIXELWORKS O4+ Fifth Generation HEXFETs from International Rectifier utilize advanced pr
CPF (95)  N/A N/A N/A Notes a. Room = 25_C, Full = as determined by the operating temperature
CPG (14)  GMICRO DIP/22 06+ Isolated Hermetic Package, JEDEC TO-257AA Outline Output Voltages: -5V,
CPH (447)  SANYO 2008 The LEDs are packed in cardboard boxes after packaging in anti-electrostat
CPI (5)  CS/HOLD (Pin 4): CMOS-Level Digital Enable Input for the Latch Holding F
CPL (43)  SAMSUNG DIP-20 08+ Motorola reserves the right to make changes without further notice to any
CPM (63)  N/A SOP16 07+ Digital-to-Analog Propagation Delay   to 90% of Output Digital-to-
CPN (24)  MITEL 2007 DESCRIPTION The 74V2T241 is an advanced high-speed CMOS DUAL BUS BUFFER
CPO (2)  ZILOG DIP 99+ values of COUT1 and Table 2b shows the output voltage ripple for variou
CPP (21)  samtec samtec dc00 Power   Supply: 2.5 V to 5.25 V operation   Normal mode: 75 &m
CPQ (1)  The 48-bit instruction word accommodates a variety of parallel operation
CPR (17)  BB 模块 08+ SMT Assembly Reliable assembly of surface mount components is a complex
CPS (17)  S SOP3.9mm 2006 Short-circuit current is internally limited. The device responds to a sus
CPT (54)  TDK The actual implementation of this technique produces a waveform that has
CPU (31)  AMI PLCC44 FEATURES D 11-Bit Resolution D 65-MSPS Maximum Sample Rate D 2-Vpp Diff
CPV (30)  IR MODULE N/A There is an internal diode from each pin to VEE. This diode will conduct
CPW (3)  99   PIN and NIN should be differentially driven, ac-coupled for optimu
CPX (6)  SONY The device employs Analog Devices iCoupler technology to combine a 3-c
CPY (1)  IOR SIP-11 08+ NOTES: 1. These power consumption characteristics are for all the valid
CPZ (2)  SMD0805 00+ The MC68307 is an integrated processor combining a static 68EC000 process
C-Q (3)  The MAX8722 integrated backlight controller is opti- mized to drive cold-
CQ- (1)  Specifications are for the output (OUTA or OUTB) of a single 2nd order sec
CQ/ (1)  The attached spice model describes the typical electrical characteristics
CQ0 (9)  MOT BGA Notes: 1. Test conditions assume signal transition times of 5 ns or less
CQ1 (9)  NAIS 04+ When M1083=Off, all interrupts (including external or internal interrupt
CQ2 (6)  HP 03+ Operating Temperature: - 55C to + 85C. (To + 125C with voltage derating.
CQ3 (2)  Motorola reserves the right to make changes without further notice to any
CQ4 (1)  The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic
CQ5 (1)  AKA 04+ 1. All characteristics are measured with C = 0.1µF from Pin 1 to GN
CQ7 (4)  . . . FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN
CQ8 (8)  QFP44 This ISOSMARTTM chipset is a pair of integrated circuits providing isol
CQ9 (3)  MOTOROLA SOT263-2.5 Supports PIO mode 4, both at 16.6 Mbytes/second theoretically Sustained
CQA (2)  SONY TQFP48 07+   These miniature surface mount MOSFETs low RDS(on) assure minimal
CQC (2)  PLESSEY 2008   The PT4140 power modules are a series of isolated DC/DC converter
CQF (58)  All signals, except WP#, are in compliance with the ATA specifications.
CQJ (1)  • Descriptor: The Descriptor byte determines if the SX2   load
CQL (1)  † Design targets only. Not tested in production.. NOTES: 5. Both
CQM (26)  Shift clock signal input for the PCMIN and PCMOUT signal. The frequency,
CQP (3)  N/A DIP N/A The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary
CQR (3)  sprague sprague dc87+ Operating Range 2-V to 5.5-V VCC Schmitt-Trigger Circuitry On A, B, and C
CQS (6)  The Am29LV160B is entirely command set compatible w it h t h e J E D E
CQT (9)  COMMQUEST 03+ A LOW on both pins initializes the FIFO read and write pointers to the fir
CQU (1)  The signal entering the DTMF detection circuitry is filtered by a notch fi
CQV (4)  SIEMENS The ERASE instruction erases data at the specified addresses in the progr
CQW (4)  Note 6: If the TO-263 or TO-252 packages are used, the thermal resistance
CQX (13)  2. The standby control input is Not compatible with TTL or   othe
CQY (22)  TEMIC DIP-6 07+/08+ Write protection in a user defined section of memory Sequential register
CR- (64)  N/A 6SDQVLRQŒ )ODVK PHPRU\ SURGXFWV FRPELQH \HDUV RI )ODVK PHPRU\ PDQXID
CR/ (2)  TI TSOP- 8 LCD Bias Adjustment PWM Signal Input C Connect to an RC filter allowing fo
CR0 (1388)  MITSUBISHI SOT-89 05+PB The TLC3541 and TLC3545 are a family of high performance, 14-bit, low p
CR1 (2182)  Description The ACPM-7833 is a fully matched CDMA Power amplifier modul
CR2 (1117)  N/A Collector power dissipation Junction temperature Input voltage of pow
CR3 (738)  AVX CORP • 27 dB modulated gain 5.15 to 5.85 GHz band • 26 dBm output
CR4 (53)    Octal bidirectional bus interface   Non-inverting 3-state out
CR5 (58)  TO252 02+ Complete PowIRtrain integrated power stage Specification and operating i
CR6 (65)  CHIPRAIL DIP8 08+ I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in
CR7 (47)  Chip-Rail ★Original and new, Special price! 06+/07+   Double Buffering of Data   Programmable Interrupt Generation
CR8 (50) 
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CRA (183)  VISHAY 0024+ Information Input Concerning Secondary Voltage. By comparing the regulati
CRB (94)  KYOCERA 2(0603)-4.7K 05+ High location function normally (see Figure 5). If bit 2 is 1, the assoc
CRC (6806)  VISHAY
CRD (32)  ck ck dc0337 maintaining the circuit density and reliability. For transient radiation
CRE (3)  INTEL PLCC The clock driver serial protocol accepts byte write, byte read, block wri
CRF (32)  TOSHIBA SOD-123 05+NOPB Input Data Mask: DM is an input mask signal for write data. Input data is
CRG (753)  N/A The Divide and Phase Select Matrix is comprised of five independent ban
CRH (15)  TOSHIBA SOD-12 06+ VDD GND PLL VCO IN PLL VCO OUT PLL Enable NC NC NC NC NC NC VDD
CRI (6)  ST 99+ BGA  This evaluation board is designed to have the maximum value of VG a
CRK (3)  murata murata dc81+ Not 100% tested. CB = total capacitance of one bus line in pF. As a tran
CRL (5)  CP CLARE N/A 08+ count in the count-down mode. Cascading of multiple packages is easily
CRM (88)  INFINEON 2008 The select-control (SAB and SBA) inputs can multiplex stored and real-t
CRN (16)  N/A 1206X5 Enables the associated DDR2 SDRAM command decoder when low and disables th
CRO (7)  CAUTION: Stresses above those listed in Absolute Maximum Ratings may caus
CRP (3)  Note 13: Maximum power dissipation (PDMAX) in the device occurs at an out
CRR (2)  CAUTION: These devices are sensitive to electrostatic discharge; follow p
CRS (92)  SMK 度金脚 6+   CAS -Before- RAS Refresh, Hidden   Refresh and Test Mode Ca
CRT (92)  N/A The 4 Mbit Flash memory array is organized into 11 blocks called sector
CRU (3)  NS SOIC-8 SX   C 2.7 (VCC = 2.7V to 5.5V)   C 1.8 (VCC = 1.8V to 5.5V) Inte
CRV (4)  MIC SOT143-4 05+ The HC164 and HCT164 are 8-bit serial-in parallel-out shift registers w
CRW (10)    The K4M51323LE is 536,870,912 bits synchronous high data rate Dyn
CRX (13)  TDK new This new IRK serie of MAGN-A-paks modules uses high voltage power thyri
CRY (27)  TOSHIBA 05+ Schmitt-trigger inputs ( nVT = 210 mV between positive and negative inpu
CRZ (19)  TDK DIP- 2+3 08+ The block logic functions are implemented by programmed look-up tables.
CS- (55)  06+ 7/TO-220 COMP: COMP is the output of the error amplifier and the input of the PWM
CS. (1)  Information For further information on technology, de- livery terms and
CS0 (105)  8+ Bild / Fig. 5 B2 - Zweiplus-Brckenschaltung / Two-pulse bridge circuit H
CS1 (467)  SEMTECH CORP 2007+   Please be aware that an important notice concerning availability,
CS2 (290)  CS DIP-18 04+
CS3 (301)  CIRRUS SOP-16 97+ This pin provides the output current range adjustment by means of a resis
CS4 (1025)  CRYSTAL TQFP100 07+/08+ The CM1450 comprises a family of inductor-capacitor (L-C) based EMI fil
CS5 (1344)  N/A N/A N/A High data rate, 5 MHz typical (NRZ) Free from latch up and oscilliation
CS6 (355)  CRVSTRL PLCC44 DESCRIPTION The SPN2302 is the N-Channel logic enhancement mode power
CS7 (65)  N/A N/A N/A ance state. The output control does not affect the in- ternal operation
CS8 (739)  INTERSIL PLCC ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2
CS9 (285)  CRYSTAL QFP The CS9233CQ and CS9233CQ are high-speed, high-precision, delta-sigma a
CSA (261)  N/A (1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle 10%. *Measurement mad
CSB (261)  muRata 陶瓷滤波 For more information refer to Xilinx XC4000E and XC4000X series Field P
CSC (282)  N/A SOP8 05/06+ Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
CSD (57)  COMSTREA.. 07+
CSE (8)  CRYDOM 2007 There are two modes both for read and write. These are summarized in Ta
CSF (45)  COMCHIP 07/08+   Parameter Forward Transconductance Total Gate Charge Gate-to-S
CSG (21)  CSG DIP48 07+ Ground Key Detection - A low active LS TTL - compatible logic output. Thi
CSH (22)  SMB 1.3.4 Interrupt Controller The CSH102700-010SXL interrupt controller con
CSI (232)  CSI S0P-8 05+ Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes
CSJ (2)    VCCI is the VCC associated with the data input port.   VCCO
CSK (3)  MuRata 2512 05+ The DSP supports nested and nonnested interrupts. Each inter- rupt type
CSL (30)  1500 Motorola reserves the right to make changes without further notice to any
CSM (293)  N/A DIP N/A   The AP2011 integrates Pulse-width-Modulation (PWM) control circuit
CSN (30)  N/A • High switching capacity 30 A for 1 Form A • 2 contact arra
CSO (18)  LINEAR 06+ 6 IRIS-A6331 is a hybrid IC consists from power MOSFET and a controller IC,
CSP (159)  AGERE BGA 01+ Edition 02.97 This edition was realized using the software system FrameMa
CSQ (1)  CHINA During the Program operation, the only valid reads are Data# Polling and
CSR (19)  kemet kemet dc70+ Software Data Protection (SDP) The SST39VF160Q/VF160 provide the JEDEC a
CSS (54)  TAIWAN 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature
CST (602)  N/A QFP 07+ NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating level
CSU (4)  SYNOPTICS QFP QFP As long as the LOCK register is not set, the output characteristic can
CSV (29)  SAMSUNG 00+ >85% Efficiency 350uA quiescent current in shutdown Fast transi
CSW (8)  94+ SOP Caution: Stresses beyond those listed under Absolute Maximum Ratings may
CSX (19)  CITIZEN 06+ RDY/BUSY: An open drain READY/BUSY output pin pro- vides another method
CSY (1)  The GS4882 and GS4982 determine odd/even field information by comparing v
CSZ (5)  Huajing TO-220 2002 † All typical values are at VCC = 3.3 V, TA = 25C. ‡ For con
C-T (11)  N/A QFP 9933+ • Two functions are incorporated in one package   (Useful for
CT- (224)  CENTILLIUM QFP208 PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt
CT0 (49)  N/A   Variations on this circuit could easily be made Simply by revers
CT1 (156)  CREATIVE PLCC 03+/04+ The AUP family is TIs premier solution to the industrys low-power needs i
CT2 (126)  MIT Device logic is automatically configured to the users speci- ʂ
CT3 (42)  PHILIPS TSSOP-20 N/A Input Termination Center-Tap: Each side of the differential input pair te
CT4 (43)  05+ The RC2207 has a typical drift specification of 20 ppm/C. The osci
CT5 (26)  04+ When executing a jump instruction, conditional skip ex- ecution, loading
CT6 (44)  98 Complete USB Hub Power Solution Meets USB Specifications 1.1 and 2.0 Ind
CT7 (18)  CT 04+ NOTE: EP circuits are designed to meet the DC specifications shown in the
CT8 (45)  CREATIVE QFP 01+ Parameter SUPPLY VOLTAGES   AVDD   CLKVDD   DVDD  
CT9 (39)  CHEERTEK QFP/160 03/0 The UCC381-3/-5/-ADJ family of positive linear series pass regulators is
CTA (10)  DIP Note A: All data listed in the above graphs has been developed from actua
CTB (46)  TOKO
CTC (35)  4. Design your application so that the product is used within the ranges
CTD (137)  CATELEC 可控硅模块 The circuit board used in the final application should use RF circuit des
CTE (6)  TOKO SOT 05+ Sector Read With sector read, a sector address is supplied with the rea
CTF (36)  The PHY uses the S5_LKON_DS2 terminal to notify the LLC to power up and b
CTG (29)  TOS/MIT TO-
CTH (16)  GLARY POWER SOP The bq24400 uses a peak-voltage detection (PVD) scheme to terminate fast
CTI (2)  PAYIONOO The MK1491-06 is a low-cost, low-jitter, high-performance clock synthes
CTJ (2)  The ADV7330 has separate 8-bit or 16-bit input ports that accept data in
CTK (1)  N/A N/A N/A These devices consist of four independent voltage comparators that are
CTL (39)  CENTILLI SSOP 01+
CTM (104)  SOP28 04+ This series of 500 W Transient Voltage Suppressors (TVSs) provides the hi
CTN (2)  ones and six zeros switching at the input clock rate. The transmission of
CTO (5)  PHI 05/06+ Six sigma quality Metallurgically bonded BKC's Sigma Bond™ plating
CTP (29)  The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to g
CTQ (3)  SMD-24 04 05 The 1N5333-5388B JEDEC registered series of axial-leaded 5.0 watt Zeners
CTR (9)  N/A NSC 04+ ICC and ICC are dependent on output loading and cycle rate. The specifie
CTS (89)  ph ph dc93 The voltage-controlled oscillator (VCO) receives the filtered error signal
CTT (127)  Features lInternational standard packages lLow RDS (on) HDMOSTM proces
CTU (20)  TOS/MIT TO- Test conditions unless otherwise noted 1. T = 25ºC, Supply Voltage =
CTV (61)  PHILPS DIP DIP AUXILIARY COMPOSITE OUTPUT The auxiliary port includes a composite video
CTW (3)  N/A N/A N/A Any information within this document that you feel is wrong, unclear or mi
CTX (168)  ★Original and new, Special price! DIP14 06+ *1: Is1 is specified as the 5% drop point of output voltage VO on the con
CTY (2) 
CTZ (86)  KYOCERA 3X4-5P 05+ If your computer is not connected to the Internet, NIST also provides Dial
C-U (7)  TVIA 01+ BGA Remote control input discriminant circuit built-in, build-in NTSC/PAL (BGH
CU- (91)  EUROTHERM An S-parameter analysis was performed in a network analyzer to optimize
CU0 (19)  SANYO 6M 05+ Supply Voltage Hall Input Voltage Range Output Current (Peak) Lock Alar
CU1 (136)  N/A SMD N/A The memory portion of the device is a CMOS serial EEPROM array with Xic
CU2 (53)  TI QFN 06+ • Low Jitter • Overtone technology • High Q Crystal ac
CU3 (60)  2007 The WRSR instruction also allows the user to enable or disable the writ
CU4 (79)  PHI SSOP24 07+ † All typical values are at VCC = 5 V, TA = 25C. ‡ The outpu
CU5 (15)  S/PHI CDIP14 —— address, and I/O pins that permit independent, asynchronous access for re
CU6 (6)  S/PHI CDIP —— RSL (Pin 4): The slew control resistor sets the maximum current and volta
CU7 (4)  N/A The M41T315Y/V/W is supplied in a 28-lead SOIC SNAPHAT® package (whi
CU8 (21)  SUNWHA 02+ Ground Supply voltage for logic Input voltage for LCD H : Data signal,
CU9 (6)  CUBICMOS DIP-16P 6+ In PCMCIA mode, the serial EEPROM stores the CIS, as well as the IEEE add
CUA (15)  The UC3702 requires a +5V logic supply as a reference. Two external re-
CUB (21)  N/A The 40105 can be cascaded to form longer registers simply by connecting
CUC (7)  Uniden O7+ Currents are positive into negative out of the specified terminal. Pulse
CUD (12)  FAIR SOT-23 • 64K bytes of flash EEPROM program memory (100K cy-   cles)
CUE (5)  sensor and thermistor can be used independent of each other if desired,
CUF (14)  Before registration of a decoded tone pair, the receiver checks for a v
CUH (6)  The VCO can operate option oscillation frequency by an external inductanc
CUI (6)  TheTC500/A/510/514 family are precision analog front ends that implemen
CUJ (1)  Notes: 1. This parameter is guaranteed but not tested on Propagation Del
CUL (3)  FSC CDIP16 9960 The PFC conversion can be enabled after the RUN/STOP switch is moved to t
CUM (5)  1735   The AP2011 integrates Pulse-width-Modulation (PWM) control circuit
CUN (1)  This ASIC provides up to 350mA of drive current for powering bulbs. Th
CUO (11)  OSICON 04+ The 16 uniform sections available form an 8-step dim- mer via 3-bit binar
CUP (60)  CPCLARE DIP 1992 Unlike serial EEPROMs, the FM25L16 performs write operations at bus spe
CUR (11)  T PLCC DESCRIPTION Siemens Solid State Relays (SSRs) are miniature, optically-co
CUS (25)  TOSHIBA 805 05+NOPB 5k   The MC74HC1G02 is a high−speed CMOS 2−input NOR gate
CUT (2)  Hynix HYMD116M645A(L)6-K/H/L series is designed for high speed of up to 13
CUX (6)  SANYO 4M 05+ The three-terminal port of the DS1804 provides an increment/decrement inte
C-V (2)   S1M8662A is fabricated on the Samsung's 0.5um high-speed, high fre
CV- (3)  100 SOP 00+ Ceramic Capacitors Above 150 kHz the performance of aluminum electrolyti
CV0 (59)  N/A   (Note 8) The following specifications apply for VA = VD = +2.7V
CV1 (124)  IDT 2005 IF input frequency at IFInP, IFInM is 130 MHz. IF differential input volt
CV2 (36)  XILINX BGA 06+ The LH1556FP is robust, ideal for telecom and ground fault applications
CV3 (15)  FUJ ZIP/16 98/0 Figure 5. Block diagram of 2 GHz production test board used for Noise Fig
CV4 (13)  PHILIPS DIP 1995 Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate
CV5 (50)  varicon varicon dc05 The CV5275K7R is a 9-digit LED driver which incorporates a shift registe
CV6 (10)  This latched Schmitt input signal is inverted and routed to D7 of the dat
CV7 (74)  Texas Instruments n/a NOTES: A. CL includes probe and jig capacitance.   B. All input pu
CV8 (26)  N/A 127 HEXFET technology is the key to International Rectifiers advanced line
CV9 (46)  LUCENT SOP 06+ -VIN = +VlN200mV Difference in Reading for Equal Positive and Negative I
CVA (140)  * This device is protected by U.S. patent numbers 4,631,603, 4,577,216, a
CVB (5)  94 Summary The demand of white and blue LEDs will dramatically in- crease
CVC (8)    Designed for PCN and PCS base station applications with frequencie
CVD (7)  C-CUBE QFP 97+ Motorola reserves the right to make changes without further notice to any
CVF (33)  DP is a 12-bit data register which can store the program ROM address to b
CVG (1)  MARUWA 05+ SMD  • Asynchronous/Isosynchronous Modes C Standard CAN Controller
CVH (2)  N/A N/A N/A The TICPAL22V10Z has 12 dedicated inputs and 10 user-definable outputs. I
CVK (1)  stock The CVKA100-01 is a fully integrated programmable voltage manager IC, p
CVL (1)  The low-cost CVL16C451-QL is a 14-bit, 10MHz sampling A/D converter. Th
CVM (36)  SANREX SOP • Extended Data-Out (EDO) Page Mode   access cycle • T
CVN (2)  An inhibit/sync pin is standard on all models of the HR700 Series conver
CVO (25)  SMD SANYO 05+   The charge pump circuit converts the variable width up and down p
CVP (4)  ITT DIP 96+ Temperature Error Using Remote Diode of 0.13 micron Pentium 4 with typi
CVR (229)  AXX 3X3可调电阻 The Hitachi HN58S65A series is electrically erasable and programmable ROM
CVS (7)  N/A 04+ • Four crystal modes up to 40 MHz • Two external clock mode
CVW (1)  General-purpose applications are greatly enhanced by the large address sp
CVX (24)  N/A 1. Rating applies when surface mounted on the minimum pad size recommende
CW- (23)  DLE   2-bit bidirectional input/output lines with pull-high resis- Wake
CW0 (45)  N/A 0603X510P8R   Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm (one layer, 70&mi
CW1 (22)  NOTES: 1. See Test Conditions under TEST CIRCUITS AND WAVEFORMS. 2. Thi
CW2 (27)  CW 模块 08+ The select-control (SAB and SBA) inputs can multiplex stored and real-t
CW3 (11)  98+ SOJ50 The set/reset line (SR) is an asynchronous active High con- trol of the
CW4 (24)  CHIPWRIGHTS 06+ 40 The IR2130/IR2132(J)(S) is a high voltage, high speed power MOSFET and
CW5 (11)  UTC TO92-2 08+ 3. Processing before Initialization Note: When power is first supplied,
CW6 (5)  CONWISE Reader Response: Conexant strives to produce quality documentation and we
CW7 (9)  N/A N/A 2006+   The MSK 5115 series voltage regulators are available in +3.3V, +5.
CW8 (1)  • 1024 Resistor Taps C 10-Bit Resolution • SPI Serial Interfa
CW9 (3)  N/A 00+ Unless otherwise specified, the following specifications apply for AGND =
CWA (20)  • Low power consumption: (typical with VDD = 3V)   - 14 mA tr
CWB (10)  SIPEX 04+
CWC (2)  After application of the VCC supply, an initial pause of 200 µs is
CWD (20)    Please read Application Note 1 "General Operating Considerati
CWH (25)  N/A 0805L Guaranteed by design but not tested. Typical parameters are representativ
CWI (2)  N/A 3225 This center tap Schottky rectifier has been optimized for very low forwa
CWM (4)  N/A P&S 04+   Main CLK(Hz)Under 3.58M7.16M10.74M14.3M   Operating Voltage(m
CWN (2)  The LM34910 Step Down Switching Regulator features all of the functions
CWP (15)  N/A PLCC 07+ Internal Timing C With external components as indicated on the application
CWR (55)  KTC 2001 The CCR-33 Switch is a broadband, SPDT, electromechanical, coaxial switch
CWS (15)  N/A The Master begins a transmission by sending a START condition. The Mast
CWT (12)  SOP 05+ Delivers up to 5 A continuous 6 A peak current Optimized for DC motor m
CWW (3)  Cirrus Logic, Inc. and its subsidiaries (Cirrus) believe that the informat
CWX (11)  CONNOR 2007+PB CE is for power control and chip select. OE controls the output buffer to
CX- (84)  SONY ZIP 05+ 275MSPS maximum conversion rate 64 interpixel sampling positions Low lon
CX0 (101)  CmoX The C-suffix devices are characterized for operation from 0C to 70C. The
CX1 (223)  SONY 金属帽 4G-001 As with any semiconductor device, some of the characteristics of HEXFET P
CX2 (961)  SONY QFP48 07+ Notes: 1. For conditions shown as Max. or Min., use appropriate value sp
CX3 (15)  SONY 02+ This specification contains information about the Samsung Electronics Comp
CX4 (82)  N/A QFP The PHSTR pin has two functions. When the sync_phstr register is 0, a hig
CX5 (79)  SONY DIP 02+ Most Significant Data Bit (MSB) Data Bits 10C1 Least Significant Data Bi
CX6 (24)  MINDSPEED QFP The HYM71V16M755HC(L)T8 Series are Dual In-line Memory Modules suitable fo
CX7 (184)  SKYWORKS 03+ Notes: 1. The algebraic convention, where the most negative value is a m
CX8 (212)  SKYWORKS 06+ BGA The PIC12C67X devices have special features to reduce external componen
CX9 (20)  CX SOT89 07环保 Hynix HYMD564M646(L)6-K/H/L series is unbuffered 200-pin double data rate
CXA (2395)  SONY SOP 98+ (1) This data is based on using the JEDEC high-K board and topside traces
CXB (39)  SONY STK 2003+ When the Deserializer PLL locks to the embedded clock edge, the Deseria
CXC (7)  SONY DIP 94+ The NE251 is a dual gate GaAs FET designed to provide flexibility in it
CXD (1672)  SONY TQFP7*7 0030+ Hynix CXD1390AR-T4-H/L series is unbuffered 184-pin double data rate Synch
CXE (34)  SWITCHCORE BGA 02+ The trigger condition for the time stage is determined by the two input
CXF (2)  SONY SOP N/A   The RC4700 also incorporates a two-entry instruction TLB. Each en
CXG (115)  SONY MSOP MSOP The 312 decoders are a series of CMOS LSIs for remote control system app
CXH (3)  ADC 00 The HEF4015B is a dual edge-triggered 4-bit static shift register (seria
CXI (6)  Maximum Average Forward Current at TC = 55C Peak Forward Surge Current
CXK (1318)  SONY 2008   The RC4700 incorporates a complete floating-point co-processor on
CXL (159)  SONY 06+ MN662790RSC is a signal processing LSI for CDs which is applicable to 4x-
CXM (45)  SONY 2008 The ZL30414 is an analog phase-locked loop (APLL) designed to provide jit
CXN (8)  SONY 06+
CXO (43)  KSS DIP-4 08+ When output current demands exceed the maximum output current rating by 1
CXP (1826)  SONY 01+ QFP Out Short Circuit to GND Duration (VIN< 12V)...Continuous Out Short Ci
CXQ (26)  SONY 3225-12脚 04+ 1) CPD is defined as the value of the ICs internal equivalent capacitance
CXR (34)  JAT 51- For packing material that is returned to us un- sorted or which we are
CXS (3)  CONEXANT 00+ BGA3535 − One Assembly/Test Site, One Fabrication   Site Extended Tem
CXT (43)  Central 06+ 1000 The ISD MicroTAD-16M ChipCorder® Product pro- vides high-quality, 3-v
CXV (2)  SONY 90 Note: Some revisions of this device may incorporate deviations from publ
CXW (1)  The HT9142 local oscillator circuit is of Colpitts type os- cillator comp
CXX (3)  sil sil dc96 1. Test conditions: T = 25º C, Supply Voltage = +6 V, Device Voltage
CXY (1)  The UC3825A,B has dual alternating outputs and the same pin configuratio
CXZ (7)  N/A (1) Stresses in excess of those listed above may result in permanent dama
CY- (16)  00+  TXD_0[1]  TXD_0[0]   TXEN_0 CRSDV_0 RXD_0[0] RXD_0[1]
CY0 (7)  CYPRESS SOP28 The A-to-B enable (CEAB) input must be low to enter data from A or to o
CY1 (156)  CYPRESS N/A 00+ Note 3: Absolute Maximum continuous ratings are those values beyond which
CY2 (3123)  CY 0025+ 1780   Operating temperature range is C40C to +85C.   Guaranteed by
CY3 (627)  CYPRESS 08+ The CLC425's combination of ultra-low noise, wide gain-band- width, high
CY4 (27)  CYPRESS 28 SOJ 08+   The NL17SZ07 is a high performance single inverter with open drai
CY5 (108)  CY • Microchips Worldwide Web site; http://www.microchip.com •
CY6 (1076)  CY 03+ NOTES: 1. Designators in TYPE: P: power supply and ground, DI: digital in
CY7 (11591)  CY SMD48 97/98+ Internal VREF Voltage. Decouple to GND with 0.1 µF capacitor. Diffe
CY8 (270)  CYPRESS 2006PB Note 1: At TA = -40C, DC characteristics are guaranteed by design and char
CY9 (40)  CYP SOP 03/+04+   The LH543601 has two 36-bit ports, Port A and Port B. Each port
CYB (100)  TRIDENT BGA2727 Pin-for-Pin Compatible with UCC280X Controllers Enhanced Performance UC
CYC (47)  sop CYPRESS 05+ Direct-Memory-Access (DMA) Controller With an Auxiliary Channel Flexible
CYD (119)  CYP BGA 0212+ The SN74GTL16923 is an 18-bit registered bus transceiver that provides
CYE (1)  NOTES: (1) Test levels: (A) 100% tested at 25C. Over temperature limits b
CYF (10)  CYPRESS 97+ VIN: Supplies the current to the collector of the output power transistor
CYG (10)  CPCLARE Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA o
CYH (3)  NS SMD 2006 200 MHz, 5 instruction/clock cycle 32-bit VLIW processing core (TM32 CPU)
CYI (69)  CYPRESS SSOP-28 07+ This pin goes low when the TH set point is exceeded by 10oC (typical).
CYK (18)  CYpress BGA-48D The H-Bridge contains integrated free-wheel di- odes. In case of free-w
CYM (68)  CDIP32 00+ These features make the 4405x Series ideally suited for high-bandwidth
CYN (42)  F 04+ PDIP6 Features • Supports 510H/760H system CCD image sensors • Sup
CYO (4)  Configurations or a Single Bidirectional Configuration Working Peak Reve
CYP (81)  CY 07+ Maximum ratings are those values beyond which device damage can occur. Ma
CYR (17)  migitem migitem dc80+   This device contains protection circuitry to guard against damage
CYS (12)  TI 00+ TSSOP48 ANALOG I/O   8-Channel, 400kSPS High Accuracy, 12-Bit ADC   O
CYT (14)  N/A SOP-14 04+ For maximum output regulation, the HR301-2805 is provided with external
CYU (1)  Port A also serves as a low-voltage 8-bit bi-directional I/O port with in
CYV (34)  CY 05/06+ Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs
CYW (81)  CYPRESS SSOP20 03+ The MAX5075 is a +4.5V to +15V push-pull, current-fed topology driver sub
CYX (1)  Reader Response: Conexant strives to produce quality documentation and we
CYY (2)  1. All high speed inputs and outputs are differential to improve performa
CYZ (3)  CY 2007 b Shift right examine and correct after each shift until the   leas
CZ- (2)  24 01+ The PCI-Express differential clock outputs of the ICS557-03 are open so
CZ0 (1)  A HIGH level on MBB chooses a mailbox register for a Port B Read or Write
CZ1 (5)  SSOP 97/P4 The HEF4093B consists of four Schmitt-trigger circuits. Each circuit fu
CZ2 (3)  PHILIPS MP-70 08+ NOTE 4: Unused Rext/Cext terminals should be left unconnected. All remain
CZ3 (1)  PHILIPS QFP 2000 Control Signal Output. This signal indicates the ODD/EVEN field of the v
CZ4 (2)  CRYSTAL STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions
CZ5 (4)  SOP-28L • 200MHz Clock, 400Mbps data rate. • VDD= +2.6V + 0.10V, VDDQ
CZ7 (1)  2000 PHILIPS 00+
CZ8 (4)  2000 PHILIPS 00+ TX2 operates at two of the rates defined in the USB Specifi- cation 2.0,
CZ9 (4)  飞利浦 03+ The DH71000 series abrupt tuning varactor are offered in a large selectio
CZA (6)  Vishay 07+ The special function registers include the indirect ad- dressing register
CZB (5)  KOA 0603B Data Bit 5 (D7), Channel A Data Bit 4 (D8), Channel A Data Bit 3 (D9)
CZD (1)  The treble network consists of R7, R8, R9, R10, C7, C8, C9, and C10. Res
CZM (3)  CURRENT COMMAND (+,-) - are differential inputs for con- trolling the mod
CZP (5)  KOA High Efficiency: Up to 95% Very Low Quiescent Current: Only 40µA 2
CZR (50)  JAT LL35 05+ 2.0% output accuracy (25˚C) Low dropout voltage: 250 mV @ 500mA (t
CZS (1)  © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, regi
CZT (52)  CENTRAL SOT-223 05+ The maximum available current can be calculated based on the open circuit
CZV (3)  2008 Configurable Logic Blocks A number of architectural improvements contrib
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