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  Mfg pack D/C Descrpion
3.0 (129)  JYQX 9811 Using commercially available, low-cost peripheral devices, the ACE Flash
3.1 (21)  172 94+ • SuperWIDE HIGH-DENSITY IN-SYSTEM   PROGRAMMABLE LOGIC  
3.2 (8)  —— DIP14晶振 92/93+ A microcontroller can be monitored by a digital window watchdog which acc
3.3 (37)  Built-in VCO coil for intermediate frequency signal processing AFT adjus
3.4 (4)  Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2
3.5 (31)  MOT PLCC44 07+   The SY10/100EL11V are 1:2 differential fanout gates. These device
3.6 (19)  SARONIX 模块 Ruotare il selettore su OC . Quando lalimentazione a ON e si applica i
3.8 (6)  EPSON SMD 0537 Designed for Digital Photography, Graphic Arts, Medical and Scientific App
3.9 (15)  AMIS PLCC68 Integrated Peripheral Controller 2X8237/AT compatible 7-channel DMA &nb
3/5 (1) 
3-0 (22)  MOT 95+ TO-39 RFR6000 Device Features • Compatibility with QUALCOMM's radioOne Z
30- (32)  HIT DO-35 05+ The baseband filters are 5th order Chebychev and provide excellent matchin
30. (9)  CRYSTAL 3-analog input terminals. Only the input from one of these is input to th
30/ (1)  05+ DIP Chip Select (Pin 23)   Chip Select Input. A high on this input prod
300 (596)  Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t
301 (240)  IR DO-205AB (DO-9) 00+ NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating level
302 (222)  07+/08+ The addition of a bias circuit in conjunction with this process results i
303 (319)  STM SOP-24 04+ When RESET goes active as a result of a low voltage condition or Watchd
304 (227)  SIEMENS 07+ A low level at the preset (PRE) or clear (CLR) inputs sets or resets the
305 (260)  HYUPJIN The output enable multiplexer (MOE) controls the output enable signal. Ea
306 (118)  AA SOP-16 06+ WP#/ACC input accelerates programming time   (when high voltage is
307 (69)  EXAR SOP24M 2007+ It contains two groups of 2 bit latches controlled by an enable input (
308 (58)  IC 集成电路 ADC10040CIMT/NOPB The LS323 is an 8-bit universal shift storage register with TRI-STATE ou
309 (80)  NS SOP16S 2007+   Updated values in Current Consumption per Power Supply Pin, Table
30A (6)  SANYO 01+ This input is used to charge the rechargeable alkaline cells and power th
30B (49)  NS 00+ TOP BOOT SECTOR LOCK: When the TBL pin is held low, program and erase ope
30C (101)  IR TO220 05+ The V 6108 is a CMOS integrated circuit that drives LCD. The circuit dri
30D (22)  TAIWAN N/A DIP These Ultrafast, soft recovery diodes are optimized to reduce losses and
30E (20)  VISHAY/IR 2007+ Other considerations are the Fanout and Loading tables. Some manufacture
30F (32)  SMD Any offset and/or gain calibration procedures should not be implemented
30G (21)  TOS TO-220 05+ 1. Continuous operation with 12 volts or more under extreme temperature a
30H (29)  ST TO-3P 02+ NOTES: 1. This parameter is warranted but not production tested. The pro
30I (2)  CAUTION: These devices are sensitive to electrostatic discharge; follow p
30J (7)  N/A   C 4-MHz Crystal Oscillator   C 32-kHz Crystal Oscillator &nb
30K (10)  NIEC TO-3P 03+ The device also provides the functions of receive equalization (optiona
30L (35)  东芝 00+ N/A The Atmel cell implements a rich and powerful set of logic functions, s
30M (7)  TI SOP/16 02+ The problem can be understood by checking the SEG dp entries in Table 1 f
30N (16)  The ICS601-01 requires a minimum number of external components for proper
30P (14)  Infineon 04+ • Compact Package • 8 mm (0.31 inch) Character   Height
30Q (9)  N/A ‡ Unless otherwise noted, voltages are reference to ground and curr
30R (22)  LITTLEFUSE 20000 PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD
30S (11)  NES DO-5 In addition to an enable input to turn on or off the regu- lator, the 30S
30T (6)  IR 07+ Fifth Generation HEXFET® power MOSFETs from International Rectifier
30U (8)  TOSHIBA MODULE N/A NOTES: 1. Skew specifications apply under identical environments (loadin
30V (15)  ROHM SOD523 Output Voltage   Pulse testing techniques are used to maintain the
30W (40)  IR 00+ This input pin determines whether the DVI link is connected to a DVI mon
30X (2)  PRX MODULE Notes: 1. For Max. or Min. conditions, use appropriate value specified u
30Y (1)  Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output
30Z (1)    CAUTION: These devices are sensitive to electrostatic discharge; f
3-1 (203)  AMP/TYCO N/A HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects
31- (133)  FUJ DIP/40 Notes: 1: Starting TJ = 25C, L = 21mH, IAS = 7A. 2: RJA is the sum of th
31. (34)  KINSEKI 94 Note 1: Absolute Maximum Ratings are those values beyond which the life
310 (180)  NEC SOP-8 The SC16C2550B is a two channel Universal Asynchronous Receiver and Tran
311 (145)  MICROCHI.. 06+ 2200
312 (130)  94   Pb−Free Packages are Available*   Integrated Power Swit
313 (139)  01 Only few external Components required Input Undervoltage Lockout 67kHz
314 (83)  1465 Measuring Diode Linear Parameters The measurement of the five elements
315 (119)  MICROCHIP SOP-7.2-18P 6+   HDPlus devices are an advanced HDTMOS™ series of power MOSF
316 (109)  N/A 1206 APPLICATIONS Precision Data Acquisition Systems Battery-Powered Equipme
317 (51)  IC 集成电路 ADS1110A0IDBVT cation code as determined by inventory requirements (Just-In Time inven
318 (61)  AMP/TYCO 0133+ International Airport Industrial Park • Mailing Address: PO Box 1140
319 (46)  SYMBIOS 04+ When the PAR/SER pin is low the chip is in serial mode. Serial data is in
31A (18)  88 DIP Each channel consists of an ultralow noise preamplifier (LNA), an X-AMP&
31B (3)  Notes:  1 Monitoring time is the time from the last pulse (negative
31D (24)  原装无铅 07/08+ = Essential Part Number = Standard Device = Top Threaded version = T
31F (24)  S/PHI CDIP24 —— CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
31G (15)  VISHAY If the synchronous enable (ES) is being used, the outputs will go to the
31H (1)  TI 98 This IC detects battery voltage and displays the remaining power in the ba
31L (3)  OmniVision Technologies, Inc. reserves the right to make changes without
31M (1) 
31N (4)  The KM68V1000B and KM68U1000B families are fabricated by SAMSUNGs advance
31P (2)  The information provided herein is believed to be reliable at press time.
31T (5)  TI BGA 01+ 5.2.2 Framing Functions The ST20196 incorporates framing functions for t
31V (1)  MOTOROLA DIP Write Protect, active Low/Accelerate (VHH). W r it e Pr ot ect Funct ion
31Y (4)  UNISIAJECS 00+  tr, tf0.11.0ns0.55 to 2.4V AC characteristics apply for parallel o
31Z (1)  Short-Circuit Output Current is a parameter that has appeared on digital
3-2 (9)  41 INTERSIL 200 (2) Master Clock (MCK)   Input 1-bit audio signals such as PWM or P
32- (36)  MOT 02+ EBEN selects the functionality of Port 5 and Port 6 When EBEN is low the
32. (37)  SEB SMD 2002   Operating temperature range is as follows: 0C to +50C.   Fre
32/ (1)  The ISL6537A provides a complete ACPI compliant power solution for up to
320 (277)  AMP/TYCO N/A s Flyback Operation with Quasi-Resonant Soft Switching   for Low Po
321 (221)  BOURNS 3224-100K 05+ The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Module
322 (287)  PANAS 03+ NOTES:2606 tbl 01 1. Stresses greater than those listed under ABSOLUTE M
323 (81)  IC 集成电路 AM29F010B-90JD The application circuit examples are only to explain the representative a
324 (126)  ATV 00+ PLCC-84 NOTES:  1. Dimensions are in inches.r.0070.18  2. Metric equi
325 (90)  N/A N/A N/A • Miniature Size • Smooth Turning and   Detented Opti
326 (304)  N/A READ CLOCK (RCLK)   Data can be read on the outputs on the LOW-to-HI
327 (123)  05+ BGA A. These materials are intended as a reference to assist customers with t
328 (64)  IC 集成电路 AS2B 3 OHM 5% • 64-bit Password Security • One Array (112 Bytes) Two Passwo
329 (558)  BOURNS 55000 Note 2: Without PCB copper enhancements. The maximum power dissipation mu
32A (6)  MOT 06+ 500   Swap Drives A and B   Non-Burst Mode DMA Option   Det
32B (3)  SILICON 05+ Note 1: Absolute Maximum continuous ratings are those values beyond which
32C (111)  PHI 06+ • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide outp
32D (88)  MOT QFP-32 99+ tPLDhOutput enable time3⋅T + tPD4⋅T + tPDnsT=CLK period &nbs
32F (49)  94 SOP Three RealTek RTL8100 10/100 Based LAN Fast PCI ATA/33/66/100 IDE contro
32G (2)  IBM 06+ This latched Schmitt input signal is inverted and routed to D7 of the dat
32H (45)  97  Analog input signal power at C1 dBFS; signal-to-noise (SNR) is the
32J (3)  Notes: 1. Test conditions assume signal transition times of 5 ns or less
32K (9)  N/A SOP8 On the multiple-input devices (32KHZ and 32KHZ), these pins select the
32L (9)  ON LCC 03 Note: 1. Commercial Product: TA=0 to 70C, otherwise specified.   In
32M (16)  COILCRAFT Honeywell reserves the right to make changes to improve reliability, funct
32N (18)  MOTOROLA Short-Circuit Output Current is a parameter that has appeared on digital
32P (92)  INF SSOP36 • HiPerFREDTM diode   - fast reverse recovery   - low op
32R (152)  SILICON Life Support Policy: HY-LINE does not authorize the use of any of its prod
32S (5)  .SAR 2003+ The LT®5519 mixer is designed to meet the high linearity requirements
32T (5)  N/A 3225 In on-hook Caller ID, such as CND, CNAM and CLIP, the information is typi
32V (3)  † All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25C.
32W (4)  N/A 1210 *1. AC for 1 minute, R.H. = 40 ~ 60%   Isolation voltage shall be m
32X (4)  N/A 00+ SSOP Note 1: See thermal regulation specification for changes in output voltage
32Y (14)  The SSM2120 contains two independent level detection circuits. Each circ
32Z (1)  N/A SOP-16P 07+ • Two standard 16-bit timer/counters • 512 8 RAM, expandable
3-3 (47)  MOT CAN6 The MSA-2111 is a low cost silicon bipolar Monolithic Microwave Integra
33- (19)  OMRON 95 With its outstanding high-speed performance, the ADS1610 is well-suited
33. (26)  爱普生 10.5×5(SG3030JC) SMD 4P tively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time will also
330 (332)  KYOCRA 1812 Input offset voltage is trimmed to less than 60µV. The low drift an
331 (417)  1250 The EL5120, EL5220, and EL5420 also feature fast slewing and settling tim
332 (271)  BOURNS 300  Maximum ratings are those values beyond which device damage can occ
333 (112)  MOTOROLA 06+ SOP 2) Verify that a shunt is installed on jumper JU3 (SYNC). 3) Connect a +2
334 (80)  F DIP 06+ The HYM72V32M656T6 Series are gold plated socket type Dual In-line Memory
335 (103)  MOT SOP the transmitted frequency to exceed its 0 01% tolerance The frequency ma
336 (271)  BOURNS 05+ Passivated high commutation triacs in a plastic full pack envelope inte
337 (96)  AMD PLCC 05+ NOTE: 1.Stresses greater than those listed under Absolute Maximum Rating
338 (375)  BOURNS 11500 BENEFITS  Enables equipment to meet IEC 61000-4-5  High off-s
339 (30)  EVERLIGHT 409 Notes: 1. Junction capacitance is determined by measuring total device ca
33A (5)  NSC 01+ SSOP-16 When 16/68# pin is at logic 1, it selects Intel bus interface and this i
33B (6)  TSOP10 02+   3.7 Certificate of conformance. A certificate of conformance as re
33C (17)  CSI 00+ SOP-8 † Stresses beyond those listed under absolute maximum ratings may c
33E (1)  The 'LS502 is an 8-bit register with the interchange logic necessary to p
33F (9)  AMD PLCC 03+   C High-speed logic and Interconnect   C Low power consumption
33G (5)  N/A N/A N/A Additionally, the ASLIC device and ASLAC device have integrated self te
33H (2)  The shaft locking device consists of a tapered nut tightening a slotted
33I (1)  Notes: 1. For max. or min. conditions, use appropriate value specified u
33J (16)  FS8S0965RCB is a Fairchild Power Switch (FPS) that is specially designe
33K (5)  FLEX 33K-5 device package types include thin quad flat pack (TQFP), plast
33M (2)  This family consists of two DC current regulators connected internally in
33N (15)  MOTOROLA TQFP1414-100 Two Instructions/clock Execution Load/Store Architecture Sixteen 32-bi
33O (1) 
33P (38)  MOTOROLA 03+ Load Regulation Since the 33P04 is only a 3 terminal device, it is not p
33R (6)  TEXAS QFP 0027+ Information furnished by Analog Devices is believed to be accurate and r
33S (4)  The F1, F2 and F3 Series were developed as timing extraction filters for
33T (4)  NS TSSOP 02+   Capacitor mounted close to the power module helps ensure stabilit
33U (29)  KEMET The UCC39421 family of synchronous PWM controllers is optimized to oper
33V (7)  ROHM SOD323 FEATURES * Extremely low on state voltage * No need to derate for higher
33W (1)  256-position TTP (two-time programmable) set-and-forget resistance &nbs
33Z (1)  96 Outputs Plasma Display Driver 95V Absolute Maximum Rating Reduced E
3-4 (16)  NS 96/95+ CAN/3 These devices provide eight two-input buffers in each pack- age All empl
34- (27)  BGA N/A
34. (96)  N/A Guaranteed 1% output voltage tolerance (LM317A) Guaranteed max. 0.01%/V
340 (247)  MOTOROLA DIP 98+   Description 34017-2P is a sound processor for CD/MD radio casset
341 (295)  MOT SOP28W 2007+ Note 1: All devices are production tested at +25C. All temperature limits
342 (169)  INTERSIL DIP 00+ Master/Slave Synchronization. When it is open, a signal synchronous with
343 (305)  MOT PLCC Controller (host) will send start bit. Controller (host) sends the writ
344 (140)  Parameter VDD to GND RFB, ROFS, R1, RCOM, and VREF to GND Logic Inputs
345 (72)  IC 集成电路 AT24C64AN-10SU-2.7 The internal circuit is composed of 3 stages including buffer output, w
346 (38)  05+ SMD Memory D Up To 32kB Flash Memory D Flash Memory Partitioning D Enduranc
347 (33)  XR SOP Note: These are stress ratings only. Stresses exceeding the range specifi
348 (53)  NATIONAL SOIC8 03+ A single PGOOD signal is issued when soft-start is complete on both PWM c
349 (31)  IC 集成电路 AT25320AN-10SI-2.7 n Analog function block with   Analog comparator with seven input
34A (16)  LM 03+ SOP-8 AMDs Flash technology combines years of Flash memory manufacturing expe
34C (43)  ST SMD-8 The 'LVTH16373 devices are 16-bit transparent D-type latches with 3-state
34D (5)  ST SMD-8 Pixel select C Selects between one or two pixels per clock output modes.
34F (6)  CSI TSSOP8 05+ The bank reserve in SDP load sequence is reserved by the bus cycle of com
34G (11)  SOP16M 2007+   Switching behavior is most easily modeled and predicted by recogn
34H (7)  TI SMD 02+ Monitors two analog voltages or thermistor temperature   inputs On
34I (3)  LT
34K (1)    The 5T929 will lock to, and track, a valid CLKIN signal; LOCK wil
34L (10)  SEC SOP44W 2007+ Wait or Transfer Acknowledge. When configured as wait, this signal is as
34M (2)  ST SOP 99+ Œ All power supplies must be on before applying a start convert puls
34N (7)  F TOP220 O5 † All typical values are at VCC = 2.5 V, TA = 25C. ‡ The bus
34P (28)  TI 98 Semelab Plc reserves the right to change test conditions, parameter limit
34R (14)  CSI TSSOP8 05+ The MT9T001 produces extraordinarily clear, sharp digital pictures, and
34S (9)  MX SOP44W 2007+ * All specs and applications shown above subject to change without prior
34T (8)  ST SMD-8 The UCC3941 family of low input voltage single inductor boost converters
34V (2)  CSI . 05+ Byte Write In the Byte Write mode, the Master device sends the START co
34W (15)  CATALYST 03+ DIP-8P • Drives N-channel High-Side and Low-Side MOSFETs in   a sync
34Y (3)  CSI TSSOP8 05+   PARAMETER Serial Clock Frequency Bus Free Time Between a STOP a
34Z (7)  CSI . 05+  TAOperating free-air temperature−4085C ‡ Defined by th
3-5 (65)  Signal input pin. An internal matching circuit, configured with resisto
35- (14)  MO 05/06+ Sending the WREN op-code causes the internal Write Enable Latch to be s
35. (57)  XDUCOA "Advance" product information describes products that are in de
350 (637)  00+ Device bus operations are initiated through the internal command regist
351 (311)  MOT DIP 00+ The LVTH16543 devices are 16-bit registered transceivers designed for low
352 (270)  LSI BGA 99 This megapixel CMOS image sensor features Digital- ClarityMicrons breakt
353 (183)  NO 04+ X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor
354 (100)  BB CAN8 While Atmel provides four options for implementing a gate array design,
355 (112)  BB 00+ Schottky Barrier Chip Guard Ring Die Construction for Transient Prote
356 (58)  UTC SOP8 08+ The LTC®3901 is a secondary side synchronous rectifier driver designe
357 (138)  NSC SMD-8 03+ In order to reduce the power dissipation of the FET and to increase the l
358 (99)  BB CAN CAN NOTES: 7. When the POLLMODE input level changes before the rising edge of
359 (118)  PHI QFN 05+ Configuration Register Set Compatible with ISA Plug-and-Play Standard &
35A (7)  NO Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog
35B (4)  EVERLIGHT na Can Be Used in Three Combinations: C OR-AND Gate C OR Gate C AND Gate
35C (27)  N/ 05+   The entire series has Underwriters Laboratory Recognition for the
35D (5)  GPS 96+ PLCC SOT-23 and SOIC Packages 0.5% Voltage Reference Initial Accuracy (IRU431
35F (6)  NS PLCC-68 07+/08+ Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading S
35G (19)  ERICSSON stock Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
35H (2)  SMD   The THAT 1510 and 1512 are high perfor- mance audio preamplifiers
35L (3)  BSM 0 6 Note 1 . Specifications are tested for production at TA = 25ºC . Sp
35M (29)  N/A N/A N/A crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed e
35N (6)  (空白) 252 The members of this family are single power supply distribution controlle
35P (7)  ST SOP8 07+ Many applications require manual-reset capabilities, allowing an operator
35R (17)  Reset: A high on this pin for two machine cycles while the oscillator is
35S (11)  IR TO-254AA 00+ The MAX1533/MAX1537 include on-board power-up sequencing, a power-good (P
35T (17)  ST SO-14 Hynix HYMD564G726(L)8-K/H/L series is registered 184-pin double data rate
35U (5)  MOT BGA 2 Designed for DDR200/266/333/400 PC mother board clock buffering Supports
35V (19)  RUBYCON 电解电容 00+ The FIFO contains overflow circuitry to disallow additional writes when
35W (38)  The 35WXA1000MTA16X16 is a stand-alone high-performance microcontroller
35X (1)  NS TSSOP 02+ DESCRIPTION The ST24/25E64 are 64K bit electrically erasable programmab
35Y (38)  RUBYCON N/A 10,648 (5) When designing your equipment, comply with the guaranteed values, in
35Z (1)  The XC9500XV family is a 2.5V CPLD family targeted for high-performance,
3-6 (274)  AMP 07+ 1. Corrected the errata 2. Added Data Protection flow chart. 3. Removed
36- (7)  MO 05/06+ The bq2060 uses a fully differential, dynamically bal- anced voltage-to-f
36. (19)  Q-TECH 晶振 1M Home Phoneline Network physical-layer, single- chip transceiver Suppo
360 (83)  N/A CAN N/A † Package drawings, standard packing quantities, thermal data, symb
361 (76)  Winbond PLCC 1998
362 (61)  MOTO SMD SMD This document contains information on products under development by INES.
363 (23)  N/A N/A N/A 32-position digital potentiometer 10 kΩ, 50 kΩ, 100 kΩ
364 (43)  NOKIA 311 Low IR (<100nA @ 1V, <500nA @ 3V) Designed for High Volume, Low
365 (25)  BB 00+ CONNECTION MEMORY   Data to be output on the serial streams may come
366 (8)  BB CAN8 04+ DESCRIPTION The M74HC166 is an high speed CMOS 8 BIT PISO SHIFT REGIST
367 (10)  IC 集成电路 AT76C120H-MU1-JZ208 The QuIET device includes on-chip filtering for both transmit and
368 (17)  2000 INTERSIL 300 Hynix HYMD264726B(L)8-M/K/H/L series is unbuffered 184-pin double data rat
369 (51)  GPS 90 • 13 I/O pins with individual direction control • High curre
36A (6)  TI TQFP64 2007+ Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Curr
36C (11)  NSC 08+ The SMPTE 259M standard requires that the output of a cable driver have a
36D (19)  International Rectifier’s RADHard HEXFET® technol- ogy provides
36E (6)  晶振 stream. EEPROM emulation (bit or byte alterability) is easily handled wit
36F (2)  JST N/A 2003 &ontroland safety devices for airplanes, trains, automobiles,  
36H (3)  ELMOS SMD The M95040 is a 4 Kbit (512 x 8) electrically eras- able programmable m
36L (1)  ST BGA 07+ The AT49SN/SV12804 is a 1.8-volt 128-megabit Flash memory. The memory is
36M (32)  IR D-34A 00+ 1) Worst case package. 2) Max number of outputs defined as (n). Data in
36N (4)  ON TO-263 00+ CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB thr
36P (2)  NJRC QFP 04+ (3) The products described in this book are intended to be used for stand
36T (2)  two circuits are interconnected at the upper eight memory locations to
36U (1)  (1) S/N can be improved for common mode noise on internal and external sig
36V (7)  ROHM SOD323 • Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns • Battery Bac
36X (1)  !Features 1) 4 -input 1-output switch. 2) Built-in 6dB amplifier and 75&
36Z (4)  03 To validate the data transmitted from the bq2022, the host generates a CR
3-7 (17)  Notes: a. Room = 25C, Full = as determined by the operating suffix. b.
37- (5)  PLCC 07+ Caution: The BiCMOS inherent to the design of this component increases th
37. (4)  TRAN SMD 04+ pins 3 & 7 connected See application schematic See application schem
370 (116)  IC 集成电路 AT89C2051X2-24PI The functionality of each circuit block is customized during configurati
371 (47)  EVERLIGHT na S3901/S3904 series do not require any DC voltage supply for operation.
372 (86)  stock There is no provision to abort an Erase or Program operation, once initia
373 (31)  IC 集成电路 AT89C51ED2-SLSUM Except for the TLC7701, which can be customized with two external resisto
374 (34)  01 Repetitive peak reverse voltage Recommended AC input voltage DC output
375 (32)  SOP-28 98+ Hynix HYMD232M646A(L)6-J/M/K/H/L series is unbuffered 200-pin double data
376 (35)  02+ Flexible bit assignment is foreseen to support ADSL overlay over POTS and
377 (33)  IC 集成电路 AT89LV55-12PC rising edge of the CLK pin. On the falling edge of the 8th clock the da
378 (36)  2000 05+ • Extended Data-Out (EDO) Page Mode access cycle • TTL compa
379 (40)  IC 集成电路 AT89S52-24JU PGND(Pin 8):Connect all power ground components to a PGND plane which sh
37A (3)  SMD-8 05+ The A128 devices have a 10-bit-resolution sample-and-hold MibADC. The Mib
37B (1)  The NetPHY™ 4LP devices on-chip input filtering and output waveshap
37C (15)  05+ DIP TOTAL HARMONIC DISTORTION + NOISE The key specification for the PCM58P i
37D (2)  This calculation was derived from laboratory measurements of an XC9500XV
37E (1)  CAT 07+ Fully self-contained 12 channel GPS receiver Fully EMI shielded SiRFs
37F (22)  PHI 96+ Reduces power, board space, cost due to level of integration System reco
37H (1)  ELMOS SMD Each PIC block encompasses two PIOs (PIO pairs) with their respective sys
37K (1)  Two data address generators (DAGs) provide addresses for simultaneous du
37L (22)  57 MICROCHIP Figure 5 shows the effects of a fast transient on the output voltage of t
37N (5)  PH TO:220   Higher Efficiency and Extends Battery Life   − RDS(on)
37R (6)  1210-37.4R The LH1526 relay is two SPST normally open switches that can replace el
37T (6)  MOT . clock stream is corrupted during a transmission. In these two modes the
37U (1)  TI SOP/16 03+ in a low state on their next high-to-low transition. The REF and USB clo
37V (24)  SST TSOP Where DC bias is not available, a zero bias Schottky diode is used to
37Z (1)  TI SOP14 04+ There are two kinds of logic blocks, the Programmable Functional Unit (PF
3-8 (65)  AMP/TYCO 0019+ slew-rate control structure with four configurable options for each indi
38- (15)  The Sidac is a silicon bilateral voltage triggered switch with greater p
38. (15)  The on-chip PLLs are a standard frequency- and phase- locked loop archi
380 (111)  TOYOCOM SOT 05+ Low stand-by current 0.3µA (typ.) Directly TTL compatible : All i
381 (49)  IC 集成电路 AT89S8253-24PI The AIC111 IC design specification serves to provide product development
382 (100)  AMP/TYCO N/A The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8
383 (36)  tolerance voltage regulation. Through the use of external resistors, the
384 (67)  NEC The Direct Rambus™ RIMM™ module is a general purpose high-pe
385 (112)  NS TO-263   The 385BXM-1.2L74385BXM-1.2 is identical in pinout to the L385BXM-
386 (47)  84 During packet reception the TPA and TPB transmitters of the receiving cab
387 (42)  IC 集成电路 AT93C46-10SU-2.7 A sense FET monitors the current supplied to the load. The sense FET meas
388 (26)  VISHAY 04+ 05+ SOP8 Data pin for I2C circuitry 5V tolerant Clock input of I2C input Analog
389 (14)  IC 集成电路 AT93C86A-10SI-1.8 The K9K1G08X0B is a 128M(134,217,728)x8bit NAND Flash Memory with a spare
38A (3)  FAIRCHILD QFN 06+ This series of products offers a positive and a negative fixed voltage re
38B (1)  ATMEL BGA0608 00+   Please be aware that an important notice concerning availability,
38C (19)  M/A-COM (LX)high-frequency Some confusion exists in the area of defining and specifying reference v
38D (1)  SHARP A force of 1.0 Kg shall be applied to each terminal in the direction of th
38E (2)  N/A N/A N/A If the transient performance requirements exceed that specified in the d
38F (9)  N/A SSOP 07+ The instruction that sets PCON.0 is the last instruction executed before
38G (1)  The 1.8 Volt Intel® Wireless Flash Memory (with 3 Volt I/O and SRAM)
38H (27)  95+ SOP/8 The architecture of the Direct RDRAM allows the highest sustained bandw
38K (1)  IN2 is connected to Pin 16 (VCCA). A ferrite antenna is connected between
38L (15)  IBM QFP-64 00+ The input capacitor CI is necessary for compensation of line influences.
38N (2)  FAIRCHILD TO-3P 06  The HYM72V32656B(L)T8 Series are Dual In-line Memory Modules suitab
38Q (1)  DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50
38S (1)  New high voltage technology designed for ZVS-switching in lamp ballasts
38T (5)  TI 865 (MAX2700/MAX2701 EV kit (Figure 3), VCC = +3.0V, TA = +25C, SHDN = GAIN_SE
38V (3)  99 Specified for 79C, 112C and 132CChannel Loading Mirror Image of MHW9188
3-9 (19)  SWR - Is the pin for controlling the deadtime between the top and bottom
39- (413)  Molex 08+ Differential or single-ended clock input signal. For differential, LVPECL
39. (15)  The SN74AVCH20T245 is designed for asynchronous communication between dat
390 (131)  AMP/TYCO 0101 Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output
391 (43)  IC 集成电路 ATF1502ASV-15AC44 Reading from the device is accomplished by taking Chip Enable (CE) and
392 (112)  AMIS PLCC-68P 03+ POWER - Enciende o apaga el TV (la tecla POWER en el panel del TV debe pe
393 (114)  320 ZILOG 00+ The RAMified Timekeeper provides full functional capability when VCC is gr
394 (25)  SSOP 05+ Complementary clock of differential SRC clock pair. True clock of diffe
395 (71)  Molex 08+  tsk(p)See Figure 350 † All typical values are at VCC = 3.3 V
396 (19)  IC 集成电路 ATMEGA162-16AU • Untinted non diffused lens • Utilizing ultrabright AllnGa
397 (17)  N/A N/A N/A When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it
398 (27)  IC 集成电路 ATMEGA169P-16AU Universal, 3 way terminals: push-on, wrap around or solder High therma
399 (26)  IC 集成电路 ATMEGA32-16AU High Efficiency Over Wide Load Current Range 0.8% Output Voltage Accuracy
39A (4)  FUJ 2002+ TSOP-24 (1) LED CURRENT CONTROL   The NJU6052 incorporates the LED current c
39C (6)  AMI DIP-32 94+   ON Semiconductors e2 PowerEdge family of low VCE(sat) transistors
39D (1)  Hynix HYMD264646A(L)8-M/K/H/L series incorporates SPD(serial presence dete
39E (2)  N/A N/A N/A Conditions Measured from input terminals to output terminals, shortest
39F (11)  JST 07+ The Spartan series is the result of more than 14 years of FPGA design e
39G (3)  AMD PLCC The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to g
39H (5)  IBM 08+ Serializer/Deserializer Independent Channel Operation 2.5-V Power Supply
39J (1)    Guaranteed Low Skew < 25ps (max)   Very low duty cycle dis
39K (4)  TOKO 99 Notes: 1. Failure criterion ; IR 100 nA at VR = 60 V   2. Please
39L (18)  MICR 99+ SOP-8 Note 11: This specification is guaranteed but not tested. The limits repr
39M (12)  MOT DIP-20P 9531+ Parameter DC INPUT CHARACTERISTICS   Input Voltage Range   In
39N (2)  Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not pro
39P (2)  Two different interfaces are supported on the network side. The first is
39R (2)  N/A 3225 Collector-emitter voltage peak value Collector-emitter voltage (open ba
39S (75)  SST TSSOP32 39SF01070-4C-WHhe 39SF01070-4C-WHC, 39SF01070-4C-WHI, and 39SF01070-4C-WH
39T (2)  MOT The HT99C810 is an 8-bit high performance RISC-like microcontroller whi
39U (2)  Disclaimer Alcor Micro Corp. reserves the right to change this product w
39V (149)  SST TSOP 03+ Incorporating a successive approximation architecture with on-board sampl
3-A (1)  Oscillation circuits • On-chip RC oscillation for system clock use.
3A0 (7)  TSSOP 05+ High output accuracy of 1% Output Adjustable from 1.24V to 26V Output Cu
3A1 (11)  HIT 07+ A six-byte command (Enter Single Pulse Program Mode) sequence to remove t
3A2 (6)  HIT DO-35 05+ The autostore configuration is designed to provide wiper position storage
3A3 (1)  ANAREN   Description Numeric, Right Hand DP Numeric, Left Hand DP Over
3A4 (5)  N/A N/A N/A -REF IN - is the input pin for applying power to the internal -15V DC -
3A5 (1) 
3A6 (3)  3 HITACHI O2+ 1. Featuring exceptional intermodulation   characteristics - optima
3A7 (1) 
3AA (11)  38 2005 Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3
3AB (4)  N/A SOP-24 08+ VDDQ - I/O Power Supply This feature is available only on the SST39VF160
3AC (2)  ROHM 03/04+ External circuitry consists of an opamp, a common PLD, and a quad fet swi
3AD (4)  4) Input thresholds are measured directly between the input pin and the t
3AE (1)  The output of this device is generated and filtered by narrow-band quartz
3AF (1)  NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD
3AG (10)  TOKO 5650 05+ Wide supply voltage range3 0V to 15V High noise immunity0 45 VDD (typ )
3AI (1)  ST 08+ > 90% Maximum Efficiency Low Quiescent Supply Current Externally Prog
3AL (1)  2. Using a CAS-before-RAS refresh cycle. CAS-before-   RAS refresh
3AO (1)  9000 IR 02+ Total Power Supply and Zener Current Output Current Source or Sink (Not
3AT (3)  NS O7+ Note 13: Comparator thresholds are expressed in terms of a voltage differ
3AU (1)  PHILIPS 2008 The LCX16373 contains sixteen D-type latches with 3-STATE standard outp
3AW (2)    The SC5388 is a 2-channel and 5-Mode digital preset equalizer with
3AX (1)  NEC SOT-89 06+ State of the art Hyperfast recovery rectifiers designed with optimized per
3B- (3) 
3B/ (1)  Philips Semiconductors FAST data sheets have been configured with an eye
3B0 (7)  ADI 07+ The combination of narrow nonlinear range and low limiting offset allows
3B1 (20)  98 Care should be taken before applying power and signals to the evaluation
3B2 (8)  LATTICA BGA 04+ stream. EEPROM emulation (bit or byte alterability) is easily handled wit
3B3 (32)  ADI 07+ Address Latch Enable/Program Pulse: Output pulse for latching the low byt
3B4 (39)  ADI 07+ Description   The 3B40-00AKE is an interline CCD solid-state image
3B5 (3)  98 This device combines four popular functions, Power-on Reset Control, Wa
3B8 (1)  Tachyon TS provides the highest levels of concurrency via numerous in
3BA (2)  Fast transient response Input voltage range: VIN 1.65V to 5.5V 1.0% ini
3BC (1)  KINSEKI 02+   Widebus  Family D A-Port Outputs Have Equivalent 25-Ω
3BD (1)  SMD 07+ROHS The output capacitor must meet the requirements for mini- mum capacitanc
3BE (2)    The information in this book has been carefully reviewed and is be
3BK (5)    Typical specifications represent average readings at +25C and VDD
3BM (1)  BVDSSDrain-to-Source Breakdown Voltage-200 ∆BV DSS /∆T J Tem
3BN (1)  monyama TSOP30M 2007+
3BO (1)  11881 IR 02+   When only the S0 pin is at a logic one the pressure measuring cir
3BS (2)  AMIS PQFP80 SOFT START Soft Start is engaged when the device is taken out of Shut-
3BT (1)  43 TI O5 Bild / Fig. 6 B6 - Sechpuls-Brckenschaltung / Six-pulse bridge circuit H
3BW (1)  19 TEMIC 99+ These octal transparent D-type latches feature 3-state outputs designed
3BX (1)  N/A module 2005+ Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V
3BZ (2)  TOSHIBA * All specs and applications shown above subject to change without prior
3C- (1)  SONION 03+ cal sync pulse; a burst gate or back porch clamp pulse; and an odd/even
3C0 (11)  CAN4 To improve total system throughput and reduce part count, board size and
3C1 (27)  HYUNDAI 00+ The CS4344 family is based on a fourth order multi-bit delta-sigma modula
3C2 (2)  HIT DO-35 05+ The GS4882 and GS4982 are precision sync separators for extracting timing
3C3 (6)  HIT DO-35 05+ The Burst Read command is initiated by applying logic low level to CS and
3C4 (7)  ST N/A Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15
3C5 (1)  ST SMD 02+ The UC1854 provides active power factor correction for power sys- tems t
3C6 (1)  Table 5 shows FLEX 3C623 performance for some common designs. All perfor
3C7 (9)  SAMSUNG 44798 MH, MR, and MMR compression and decompression are provided in hardware.
3C8 (40)  LGVWKR SOP32 07+ The fan speed is measured by counting the number of the CLK pin period be
3C9 (14)  N/A N/A N/A Rectifier circuit Receives radio wave via the (external) antenna circuit
3CA (3)  ALPS 08+ Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE   
3CC (3)  KINSEKI 02+ This is a dual purpose pin. During Master Reset, a HIGH on BE will select
3CD (3)  4 SOP-8 When the IC is enabled (TXEN high) a phase locked loop locks the output
3CG (12)  N/A N/A N/A The VCS features the high peak current capability and low On- state volta
3CI (1)  3. Flexible Power/Serial Clock Speed Management.   The conversion r
3CK (1)  Figure 1 shows a high-level block diagram of a 128 macro- cell device i
3CM (1)  Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient
3CN (12)  Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA F
3CO (37)  N/A QFP 1. When ordering, use the entire part number. Add the suffix 96 to
3CP (1)  36 SAMSUNG Applications • Data communication   C PDAs   C Notebook
3CQ (3)  ATLINRS 04+ QFP100   3.3 Electrical performance characteristics and postirradiation par
3CR (3)  2.9V to 14V input voltage range 400kHz oscillator frequency PWM curren
3CS (1)  Widebus  Family Output Ports Have Equivalent 22-Ω Series R
3CT (29)  • Integrated 10BASE-T/100BASE-TX/1000BASE-T transceivers • 1
3CW (1)  2008 Low power RS-485 systems Network hubs, bridges, and routers Point of
3CZ (1)  The e1217X contains two push-pull output buffers for driving bipolar step
3D- (5)  TI Figure above shows the topology of a protected analog subscriber line a
3D0 (2)  Current Feedback Interface   The IRMCK203 has a built-in interface
3D1 (3)  N/A When the PC is turned off, the hardware clock runs from a battery. When th
3D2 (9)  96+ QFP requires that the differential linearity error not exceed 1 LSB in the n
3D4 (2)  A buffered output-enable (OE) input can be used to place the eight output
3D5 (4)  As the market for handheld phones continues to increase, so has demand fo
3D6 (2)  YCL 9236 This small, power-efficient PA has a full 1700 to 2200 MHz bandwidth cove
3D7 (6)  NULL SOP-16P 05+ The ISSI IS62C1024L is a low power,131,072-word by 8-bit CMOS static RA
3DA (38)  N/A CAN-3P 08+ The SA2400A is a fully integrated single IC RF transceiver designed for
3DC (4)  LUCAS DIP 82 The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-perform
3DD (26)  TO-3 NEW The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clo
3DE (1)  N/A N/A N/A With PC1, the capture range depends on the low-pass filter characteristi
3DF (4)  98 The 3DF500-0004-02 is a quad 2-input multiplexer with 3-state outputs, w
3DG (27)  CAN3 Full clock cycle timing is guaranteed at all times after the system has i
3DI (5)  98 OPTI-LOOP compensation allows the transient response to be optimized over
3DJ (7)  N/A N/A Features: •Programmable ouput frequency. •Programmable oup
3DK (8)  CAN3 • Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGUR
3DL (9)  WED 03/04+ n Up to fourteen multi-source vectored interrupts servicing   Exte
3DP (2)  ST 06+ Input Filter: To facilitate the high output fast trqansient performance,
3DR (7)  D 99 To prevent data corruption and inadvertent write operations during powe
3DS (2)  Infineon 06+ 480 During the rise and fall time interval when switching a resistive load,
3DT (1)  NEC SOP-28 08+ Serialized data bits are output from the DO output, starting in ascending
3DU (10)  YC The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Rec
3DZ (2)  SHARP SOT 00+ • 2.7VC3.6V operation • CMOS for optimum speed/power •
3-E (2)  TDK N/A 0302+ CNY17-1/2/3 are also available in white package by  specifying -M s
3E0 (1)  Notes: 1. Junction capacitance is determined by measuring total device ca
3E1 (1)  Notes: (1) All parameters, except nominal output voltage are specified f
3E3 (2)  N/A TSOP12 N/A The HYM7V63401B R-Series are Dual In-line Memory Modules suitable for easy
3EA (1)  MT BGA 04+ The HET is an advanced intelligent timer that provides sophisticated timi
3EB (4)  high-frequency tube ROHM 04+ The LM136 series voltage references are much easier to use than ordinary
3EC (4)  (空白) 1808 Notes: 1. Scale is approximately 5ns per division. Sampling rate = 10MHz
3ED (1)    DESCRIPTION   The IS66_ series are optically coupled isolato
3EE (1)  The EM78M612 is implemented on a RISC architecture. It has five-level stac
3EF (3)  The integrated high performance USB transceivers allow the ISP1563 to han
3EH (1) 
3EK (1)  The CY7C245A replaces bipolar devices and offers the advan- tages of low
3EP (1) 
3ER (1)    For application flexibility, a CAS latency, a burst length, and a
3ET (1)  The 256 Kbyte Flash memory array is organized into seven blocks called
3EX (1)  The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated w
3EZ (61)  EIC DO-41 07+   When the external oscillator is connected to XI/XO pins, check the
3F0 (6)  S SOP8 07+ Edition 01.2001 Published by Infineon AG , Marketing-Communication, Bal
3F1 (1)  The CYP(V)15G0401DXB[1] Quad HOTLink II™ Transceiver is a point-to-
3F2 (1)  Demonstrating almost identical dynamic performance at analog input freque
3F4 (6)  MAXIM If high inductance values and low capacitor values are used, the additio
3F8 (7)  SAMSUNG TQFP 03+/04 In this mode, CS is active (low) between serial I/O CLOCK transfers and e
3F9 (11)  IC 01+ PLCC52 A buffered output-enable (OE) input can be used to place the eight output
3FD (33)  NEC DIP28 00+ The MSA-series is fabricated using HPs 10 GHz fT, 25 GHz f MAX, silicon
3FL (18)  These devices contain two independent positive- edge-triggered D-type f
3FS (35)  calls, and loops on the 24-bit program counter (PC). In direct addressin
3FT (3)  Current Limit Protection Isolation Test Voltage 5300 VRMS Typical RON
3FW (1)  Intersil products are sold by description only. Intersil Corporation rese
3G2 (1)  256 x 8-bit organization array (3G2PD) 512 x 8-bit organization array (3G
3G3 (53)  E1, T1, AND SUBRATE OPERATION COMPLIES WITH G.SHDSL AND HDSL2 16-BIT, DE
3G4 (4)  fai SOT-23 05+ (1) An export permit needs to be obtained from the competent authorities
3G5 (1)  Maximum rating 3G502A01R00he maximum ratings are the limit values which
3GB (1)  Description Reserved PCI6 Output Control 1 = enabled, 0 = forced LOW P
3GJ (1)  HARDWARE DATA PROTECTION: Hardware features p rotect ag ain st ina dvert
3GS (1)    The CSPU877A is a PLL based clock driver that acts as a zero delay
3GT (2)  Conforms to CAN Specification Version 2.0 Part A and B Automatic re-tra
3GU (1)  TOSHIBA 03+ DIP
3GW (2)  The 3GWJ2 are non-inverting drivers. The outputs are configured into 2 gr
3GX (1)  01 Using the latest high voltage technology based on a patented strip layo
3H0 (1)  Open-Load Detect The open load detect resistor is an external high-value
3H1 (2)  DRD DIP 07+ Pin Selectable Gain of 1 or 10 High Common Mode Voltage Range:   85
3H2 (1) 
3H3 (1) 
3H7 (4)  SHAPR SOP4 02+ 26dB small signal gain 26.5dBm output power @ 1dB compression 2.5% EVM
3H9 (3)  MOTOROLA BGA 00+ Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with
3HA (2)  CAOUT: This is the output of the wide bandwidth current amplifier and on
3HC (1)  Stresses beyond those listed under absolute maximum ratings may cause per
3HE (1)  The OPA675 and OPA676 are wideband monolithic operational amplifiers wit
3HG (2)  SAMSUNG DIP-36 00+ The shutdown circuitry consists of a quad comparator IC (IC2), a lamp res
3HI (1)  Ratio of output level with 1-kHz full-scale sine wave input, to the outpu
3HM (1)  This would allow the system to always power-up to a preset value stored
3HN (1)  • The basic gate function is lined up as Renesas uni logic series.
3HP (7)  AGILENT BGA 00+ Performance Motion Devices, Inc. assumes no liability for applications as
3HX (1)    ON Semiconductors e2 PowerEdge family of low VCE(sat) transistors
3I0 (1)  The SNIC supports 192 kbit/s (2B+D + overhead) full duplex data transmiss
3I5 (1)  3i techs Features   • Especially suited for use in electret condenser m
3JA (7)  TI SOP 03/+04+ Palladium plating is used on the terminal pins. A pin temperature (Tp) in
3JD (1)  ALPS QFP-44 08+ The device includes a complete analogue signal processing channel contain
3JU (1)  05环保 In addition to the standard output configuration, the outputs of the is
3-K (1)  PLL division factors for different clock inputs The word select PLL Th
3K0 (1)  1812 Note 11: CPD is defined as the value of the internal equivalent capacitan
3K2 (3)  The 5-volt device is fully accessible and data can be written and read on
3K3 (4)  ESD damage can range from subtle performance degradation to complete de
3K4 (1)  FAIRCHILD 05/06+ Description The HFBR-5710L optical transceiver is compliant with the
3K5 (1)  * The information contained herein is presented only as a guide for the ap
3K6 (1)  15. I2C-bus   When power is first applied, the contents of an exter
3K8 (1)  • Solid-state Relay (Equivalent to AQW210S)   - Typical RON 2
3K9 (3)  ParameterMin. Typ. Max. Units ISContinuous Source Current (Body Diode) -
3KB (3)  HY57V281620HC(L)T is offering fully synchronous operation referenced to a
3KE (2)  EIC DO201AD 05+   The most common application for charge pump devices is the invert
3KH (1)  A hardware RESET# pin terminates any operation in progress. The interna
3KP (52)  PANJIT P-600 2008+ The output voltage transient comparators provide a quick response , first
3KT (7)  The FDC10 and FDC10-W series offer 10 watts of output power from a 2 x 1
3KV (16)  WM Y5P 05+   The R4700 is upwardly software compatible with the IDT79R3000͐
3L- (1)  The 3L-X9361-TR7 can easily be interfaced to a baseband processor such as
3L0 (3)  ST 05+ SOP Built-in overvoltage protection prevents the output from going above 115%
3L2 (1)  The ADC12081 is a monolithic CMOS analog-to-digital con- verter capable
3L3 (1)  Notes:  2. X =Don't Care. H = Logic HIGH, L = Logic LOW. BWx = 0 si
3L4 (1)  TI 03+ During the preamble, each period of the carrier signal decreases the gain
3L9 (1)  The extremely low operating power along with the two reduced power modes
3LC (1)  Notes a. Surface Mounted on 1 x 1 FR4 Board. b. See Reliability Manual
3LD (1)  2008   Please be aware that an important notice concerning availability,
3LM (1)  SANYO SOT-523 05+
3LN (36)  SANYO SOT-23 05+ The A0, A1, and A2 are the device address inputs that are hardwired or
3LP (22)  SANYO SOT-23 05+ Formato Singola Europa 100x160 mm; interfaccia al BUS Industriale ABACO&
3LT (1)  A/D converters are calibrated by positioning their digital outputs exact
3LU (1)  Source current: In stand-by condition Source current: While detecting l
3LV (1)  The signal-to-noise ratio (S/N) unit detects the noise components of the
3LX (1)  Flexible control options for power management are available when the seri
3-M (2)  • Fast access time: 7, 8, 10, 12 ns • CMOS low power operat
3M- (2) 
3M0 (7)  SHAEP SOP8 The following is a list of advisories on modules in this version of silic
3M1 (2)  4000 05+ Continuous Power Dissipation (TA = +25C) SOT23-5.....520 mW Operating Te
3M3 (1) 
3M4 (4)  N/A N/A N/A
3M6 (1)  • 5 Ω switch connection between two ports • TTL-compatib
3M7 (4)  QFN 99+ 4. Design your application so that the product is used within the ranges
3M9 (1) 
3MB (9)  04+ VCCL, VCCR, VLC0L, VLC0R, VLC1L, VLC1R, VLC4L, VLC4R, VLC5L and VLC5R Re
3MG (1)  19 AMIS Pin-compatible upgrade of TMC2242B User-selectable interpolate d.c. gain
3MM (11)  AMKOR 01+
3MN (1)  Notes: 1. These displays are recommended for high ambient light operatio
3MT (1)  N/A   To prevent oscillations, place the output capacitor between the ou
3MX (1)  TOREX N/A 2006 The 3MX6202PF02MRN is designed to appear to the systems designer as a mic
3N0 (11)  JRC SOP 03+ This is an N-Channel enhancement mode silicon gate power field eff
3N1 (125)  MOTOROLA CAN4 The ISP1563 is a Peripheral Component Interconnect (PCI)-based, single-ch
3N2 (48)  MOTOROLA CAN4 This new generation of trench MOSFETs from Zetex utilizes a unique struct
3N3 (14)  MOT Maximum ratings are those values beyond which device damage can occur. Ma
3N4 (7)  MOT Widebus E Family Output Ports Have Equivalent 25-Ω Series Resistor
3N5 (12)  MOT This data sheet has been carefully CORPORATION • 5980 NORTH SHANN
3N6 (12)  AAT TO-220/F 08+ Applications include point-to-point (single termination) and multi- poin
3N7 (12)  DSI n/a The Power Trends PT6670 ISRs are a series of convert- ers that operate f
3N8 (11)  MOT CAN3 01+ / 99+ Operating Temperature: - 55C to + 85C. (To + 125C with voltage derating.
3N9 (10)  MOTOROLA CAN4 Ultra Low Current Consumption Upgrade and Compatible to the LMX2370 2.
3NA (1)  ST TO-220 0728vgc+ Programmable up to 60 fps Programmable up to 150 fps 10-bit, on-chip 1.
3NB (2)  • Undervoltage Lockout • Low Profile Package (12mm) •
3NC (2)  OFFSET VOLTAGE, initial OFFSET VOLTAGE, vs. temperature OFFSET VOLTAGE
3NE (2)  N/A N/A N/A Synchronous Controller plus 3-LDO controllers Current Limit using MOSFET
3NF (2)  SOT-223 The ICS clock generator is a slave/receiver, I2C component. It can read
3NK (4)  ST TO-220 03+ 1. By clocking each of the 2,048 row addresses (A0   through A10) o
3NV (3)  ST SMD-8   The maximum power package dissipation is the power dissipation le
3OP (1)  Clock Input. CLK provides the reference signal to the internal PLL. Feed
3P- (1)  This new generation of TRENCH MOSFETs from Zetex utilizes a unique struct
3P0 (3)  MC O7+ The two-wire bus is defined as a Serial Data line (SDA), and a Serial Cl
3P1 (2)  N/A SOP/8 05+ The OPA725 and OPA726 series op amps use a state-of-the-art 12V analog
3P2 (8)  SAMSUNG 04+ In AM mode the AM mixer, the AM RF-AGC and the 1st IF AM amplifier at pi
3P3 (5)  MOT 04+ SOP-8   CAUTION: These devices are sensitive to electrostatic discharge; f
3P4 (13)  SAMSUNG Other features include low quiescent current, typical- ly 70µA, and
3P5 (1)  be accessed in less than 70ns/90ns with respect to Spec. This eliminates
3P6 (5)  N/A The TO-220 Fullpak eliminates the need for additional insulating hardware
3P7 (11)  SAM SUNG 0047
3P8 (16)  SAM QFP 01+ The MAX8722 integrated backlight controller is opti- mized to drive cold-
3P9 (13)  SAMSUNG 00+ AMBE-2000™ Vocoder Chip is a registered trademark of Digital Voice
3PA (2) 
3PC (5)  SAGAMI 04+ SMD Beneficial comments (recommendations, additions, deletions) and any perti
3PF (1)  Note 2: This IC contains a zener clamp structure between the chip VCC and
3PH (3) 
3PI (1)  The L5970AD is a step down monolithic power switching regulator with a
3PL (1)  The host communication expansion connectors on the EVB555 are designed fo
3PM (1)  The bq2060 accepts an NTC thermistor (Semitec 103AT) for temperature meas
3PP (2)  . . . designed for broadband applications requiring low distortion charac
3PS (1)  Note: (6) IX is measured under the following conditions with one diode s
3QA (1)  Features • Ultra small surface mount   package • Minim
3QE (1)  MICRON 04+ BGA8*14
3QF (1)  N/A BGA already. In many cases, this is the only change required. Systems that
3QL (1)  Reference voltage for the I and Q mixer. This voltage should be the same
3R0 (2)  204 98+ Once the feature is enabled, the data in the boot block can no longer be
3R2 (1)  All DATEL sampling A/D converters are fully characterized and specified
3R3 (9)  N/A 3225 An analog overcurrent detection circuitry is built into the ISP1521, whic
3R4 (1)  SOP 06+ Note: (1) This parameter is tested initially and after a design or proce
3R5 (1)  Note: Both regulators can be bypassed if external regulation is desired.
3R7 (1)  1.1 ARCHITECTURE The COP8 family is based on a modified Harvard architec
3R8 (1)  Note 2: All characteristics are measured with capacitor across the input
3R9 (1)  n CMOS design for low power n 0.2V sensitivity over input common mode
3RA (1)  PLCC 87 HT1626 make it suitable for multiple LCD applications including LCD modul
3RD (1)  The devices operate in the newly developed LinSkip mode. In this operatin
3RE (1)  While the LM2936 maintains regulation to 60V, it will not withstand a s
3RH (1)  MOT PLCC52 06+ FEATURES Precision 1.200 V Voltage Reference Ultracompact 3 mm 3 mm SOT-
3RM (1)  is provided by an active LOW Chip Enable (CE), an active LOW Output Ena
3RN (4)  NEC 06+ 219 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD
3RP (1)  When the enable input is high, all four analog switches are off. The su
3RT (1)    The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synch
3RU (1)  The 3RUS2150 MultiKey has three, 384-bit read/write data partitions, ea
3RW (2)  Note 2: LED is on when input signal is high, and off when it is low. &nbs
3S0 (19)  N/A SSOP 07+ Recovered Clock. These ECL 100K outputs (+5V referenced) represent the re
3S1 (6)  FOXCONN 2306   High voltage line feeding   Internal ring and metering signal
3S2 (1)  TXC 08+ Hynix HYMD232726B(L)8-M/K/H/L series is unbuffered 184-pin double data rat
3S4 (5)    Output current rating may be limited by duty cycle, ambient temp
3S5 (2)  N/A N/A N/A The internal circuit is composed of 3 stages including buffer output, w
3S6 (6)  S.S.S 02+ QFP The AD581 can be easily connected with power pnp or power Darlington pnp
3S7 (1)  94   The PTH05050 is one of the smallest non-isolated power modules fr
3S8 (1)  N/A SOP The bq2060 supports the smart bat- tery data (SBData) commands and charg
3SA (1)  The HMJ1 is a high dynamic range, GaAs FET mixer. This active FET reali
3SB (3)  BEL 0502 14 Isolated Hermetic Package, JEDEC TO-257AA Outline Reference Voltages Se
3SC (1)   (ang) -176.77 -176.95 -176.88 -176.62 -176.51 -176.15 -175.84
3SD (8)  SHARP DIP5 As the input voltage ramps up to 8 to 10 volts, the internal HUMMER modu
3SE (1)  SHARP 05+ DIP/6 Preface Thank you for choosing Deltas high-performance 3SE21 Series. 3SE2
3SF (2)  SHARP N/A   C Address translation unit   C Some internal configuration r
3SH (2)  SHARP DIP4 07+ The 3SH11 has two modes of operation. When the SET pin is connected to gr
3SI (3)  RSDRD QFP 02+ • New specifications   • Dual frequency standard for indu
3SJ (2)  NEC CAN4 N/A
3SK (518)  HIT CAN 04+ Note 4: The absolute maximum junction temperature (TJmax) for this device
3SM (1)    4.4.3 Group C inspection. Group C inspection shall be conducted in
3SO (1)  Loop enable. When LOOPEN is high (active), the internal loop-back path is
3SQ (1) 
3ST (7)  A decoupling capacitor of 0.01µF must be connected between VDD an
3SW (1)  N/A 7X5 The clock input is differential and TTL/CMOS-compatible. The 10-bit digi
3SX (1)  NOTE 1: All voltages are with respect to Logic Gnd pin. All currents are
3T- (2)  CTC Note 4: When VREF > 1.2V and VREF x3 > VIN, the P-channel FET will b
3T0 (11)  N/A Unicorn shipping package includes a complete set of field proven software
3T1 (3)  † Stresses beyond those listed under absolute maximum ratings may c
3T2 (2)  SHARP 01+ SOP-8 The SMSC 4-port hub controller supports the Session Request Protocol (SRP)
3T3 (2)  CONCORD 07+ DO-214AA   Description  Reference Voltage 1 Voltage Adjustment 1 &nbs
3T8 (1)  The scaled-down output voltage is internally monitored and a power good
3TA (1)  MT BGA 04+ By changing the time constant C1 and C2, the response, attack and release
3TC (7)  N/A This location is reserved for the Timer/Event Counter interrupt service p
3TD (1)  N/A 1206 When VPP is low (VPP = V PPL), the contents of the command latch are fix
3TE (1)  N/A 100 FEATURES • Current Limit Protection • l/O Isolation, 5300 VR
3TH (2)  Figure 7 shows the BUF12800 in a typical configuration. In this configu
3TP (1)  XIL 99   The µPD75P316A is a product of the µPD75316 with on-chi
3TR (1)    The output voltage accuracy in the PWM mode is well within 3% of
3TS (2)  ROHM Two serial outputs (QS1 and QS2) are available for cascading a number
3TZ (1)  SHARP SOT-5 They are intended for applications in the RF front end, in wideband ap
3U0 (3)  TEMIC O7+ The 1 Mbyte Flash memory array is organized into nineteen blocks called
3U3 (3)  The on-chip DPLL meets Telcordia GR-1244-CORE stratum 4 specifications (St
3UF (2)  "Write Disturb" means a phenomenon that frequent write cycles ex
3UK (1)  Each MECL 10,000 series circuit has been designed to meet the dc specific
3UR (1)  Note: Stresses greater than those listed under MAXIMUM RATINGS may cause
3V0 (3)  TOSHIBA SOD523 The PCM1780/81/82 is a CMOS, monolithic, inte- grated circuit, which in
3V1 (2)  N/ 05+ • 5 Ω typical ron • Pull-up on B port • Undershoot
3V2 (2)  PANASONIC SOT23 • Thyristor controller for AC (circuit   W3C acc. to IEC) for
3V3 (12)  01+ SOP   PAGE operations allow faster data operations (READ, WRITE or READ
3V4 (1)  LEXMRK BGA 07+ • Fully supports PowerPC™ 60x bus protocol, include PowerPC 6
3V5 (4)  ST SMD 02+ For Schottky barrier diodes, thermal run-away has to be considered as in
3V9 (9)  01+ SOP-14 8 kinds of time base/WDT clock sources 32´4 LCD driver Built-in 3
3VB (1)  FEATURES   High Ripple Rejection70dB typ. (f=1kHz,Vo=3V Version) &
3VH (7)  A/N SOP-16 01 WE\ is high in read cycle. Device is continuously selected when CE\ = VIL
3VN (3)  Two fully-programmable operation modes, Mode0 and Mode1, allow fast switc
3VP (1)  MICROCHIP QFN-8P小体 6+
3VS (1)  The phase of VS relative to HS and the active picture content is measured
3VT (11)  TIE Circuit Reset (Input). A logic low at this input resets the Time Inter
3W0 (6)  N /A 00+ N/A SRAM. The DM9601 has interfaces to the UTP3, 4, 5 in 10Base-T and UTP5 in
3W1 (2)  The HT93LC46/56/66 is accessed via a three-wire serial communication inte
3W7 (2)  TeIecHIZ QFP 2001 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
3W8 (1)  The ISL6614A integrates two ISL6613A MOSFET drivers and is specifically d
3WC (1)  SEEQ 01+ N/A † Stresses beyond those listed under absolute maximum ratings may c
3X1 (8)  The FM1233A is a supervisor circuit that monitors a micropro- cessor pow
3X2 (2) 
3X3 (2)  HOKURIKU 05+ 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 10 Clock Outputs: D
3X7 (1) 
3XO (1) 
3Y2 (2)  IC SOP Digital feedthrough error is defined as the area of the impulse injected
3Y3 (1)  Note 1: Absolute Maximum Ratings are those values beyond which the life
3YV (2)  Note 1: Absolute maximum ratings are those beyond which the safety of the
3Z1 (1)  TOSHIBA DIP-2
3Z3 (1)  This N-Channel MOSFET is produced using Fairchild Semiconductors advanc
3Z4 (2) 
3ZA (1)  MICROCHIP QFN-8P小体 6+ The SDA is a Bi-directional pin used to transfer addresses and data int
3ZI (1)  MICROCHIP QFN-8P小体 6+ Supply Voltage (V+ = AVCC = DVCC) Voltage at Any Input or Output Input
3ZP (1)  MICROCHIP QFN-8P小体 6+ The analog outputs are designed to directly drive a dual 50 or 75 ohm lo
3ZS (1)  MICROCHIP QFN-8P小体 6+  TESTCONDITIONS  Thermal CyclingWithstands - 55C to +125C &nb
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