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  Mfg pack D/C Descrpion
1(P (1)  NOTES 1Temperature range from C40C to +85C. 2Operational from V DD = 2.0
1.0 (46)  TELEFONICA PQFP-240 01+ Supply voltage input for left channel and for primary bias circuits Mute
1.1 (26)  LUCENT 97 = Essential Part Number = Standard Device = Top Threaded version = T
1.2 (21)  00+ DIP-4 Device programming is performed a byte/word at a time by executing the
1.3 (12)  991 HARRIS 9736 • State-of-the-art architecture   Non-volatile data storage
1.4 (7)  dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circ
1.5 (954)  ITT The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM i
1.6 (13)  TOSHIBA 04+ Terminal nos. 3 and 8 are soft start terminals. Connect a capacitor to th
1.7 (7)  S3 BGA 2001 Electrical These devices use a modified 4 x 7 dot matrix light emittin
1.8 (23)  N/A 0603L Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0CP0.2 are open drai
1.9 (4) 
1.S (2)  Case: JEDEC ITO-220AB molded plastic body Terminals: Plated leads, solder
1/1 (2) 
1/2 (1) 
1/8 (1) 
1/N (1) 
1/P (2) 
1-0 (77)  圆柱 The LM45 series are precision integrated-circuit temperature sensors, w
10- (290)  Molex 08+ † Stresses beyond those listed under absolute maximum ratings may c
10. (39)  SUNNY 95+   VOLTAGE OUTPUT versus APPLIED DIFFERENTIAL PRESSURE   The di
10/ (1)  04+ Notes: 1. The algebraic convention, where most negative value is a minim
100 (3127)  N/A This applies to SAA7120 only. The device is protected by USA patent num
101 (748)  AMIS QFP160 • Viewing Angles Match Traffic   Management Requirements R
102 (710)  07+ Package drawings, standard packing quantities, thermal data, symbolizatio
103 (788)  N/A 0805T Microchip received QS-9000 quality system certification for its worldwid
104 (629)  N/A 805 Receiving and Inspection This 104Z AC drive has gone through rigorous qua
105 (397)  N/A 0603c Its low-IF architecture highly integrated RF/IF sec- tions include a lo
106 (242)  06+ Common Mode Voltage. The voltage output at this pin is required to be t
107 (140)  MOT 8302 Although the main application of VIPer53E is in AC/DC converters for co
108 (266)  仙 童 TO-252 04+ • SuperBIG HIGH DENSITY IN-SYSTEM   PROGRAMMABLE LOGIC  
109 (214)  PHILIPS 00+ SSOP20 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
10A (48)  SSOP-8P 38503 INTERSIL 6. CPD is defined as the value of the internal equivalent capacitance whi
10B (43)  SMB The LF147 is a low cost, high speed quad JFET input operational amplifier
10C (36)  IR 07+   The MX826 is a µProcessor controlled full-duplex audio proc
10D (30)  TOS TO-220F 04+ The 10DL2CZ47A features three independent power supplies. These are the
10E (74)  2008 • The use of twin crossbar contacts en- sures high contact reliabil
10F (30)  TOSHIBA TO- Ringing is applied to the line by disconnecting pin 8, RF, from pin 9, RV,
10G (20)  TOS TO-220F 04+ The EB-2100x features local power regulation to facilitate operation from
10H (127)  02+ Notes: 1. Permanent damage may occur if any of these limits are exceeded.
10J (15)  HITACHI TO-220 02+   If any input pin (S1, S0, DATA, or CLK) is driven HIGH while the
10K (36)  97+98+99 SOP16 Wireless Base Station Receiver Multi-Carrier Digital Receiver UMTS (4 Ca
10L (27)  Input-Output Saturation Resistance (10LI5-01100B-26A): This is a measure
10M (63)  SOP 05+ The AT91X40 Series features a direct connection to off-chip memory, inclu
10N (38)  原装ST TO-220 10000 Boundary scan instructions and associated data registers support a stan
10P (31)  N/A BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS /∆T J Temperat
10R (24)  IR TO-208AA (TO-48) 00+ 1. This drawing measure is a standard value. All dimensions are in millim
10S (41)  MOT SOP 03/+04+ The LM78LXX series of three terminal positive regulators is available w
10T (48)  IR TO-   This network is less than 2% of the overall network resistance so
10U (57)  cn 6 In an M68300 family component, the major functions and glue logic are all
10V (26)  SQFP48 2007+ COL A, COL B (Pins 3, 14): These are the open collectors of the output po
10W (7)  IR 07+   functional operation of the device at these or any other condition
10X (23)  TOSHIBA SOT23-3 Xtal/clock operation Operation of any MX-COM IC without a Xtal or clock
10Y (33)  TOSHIBA 23-10V 05+ Note 1: INSEL=0 > SCLK, SDI, and LOAD pins are active for serial progr
10Z (4)  The LCX16373 contains sixteen D-type latches with 3-STATE standard outp
1-1 (916)  AMP 07+ Any input can be modulated by a pulse train of variable duty cycle (&aum
11- (47)  SOP28W 2007+ This document contains information on a product under development at Adva
11. (34)  JAT In a given application, the magnitude of peak-to-peak jitter at the pha
110 (421)  100 天龙伟业 靳先生 2 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature
111 (342)  SOP In 1969, the first triple operational transconductance ampliᤙ
112 (230)  TOS DIP42 98 Multilayer ceramic capacitors are manufactured by mixing the ceramic powd
113 (235)  SMD-8 04 05 These display devices are designed to provide an optimum ON/OFF contr
114 (196)  DIP8 2007+ Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORP
115 (180)  USI SOP20W 2007+ EPIC™ (Enhanced-Performance Implanted CMOS) Process Schmitt-Trigge
116 (121)  98+ PLCC44脚 1. Stresses above those listed under Absolute Maximum Ratings may cause
117 (163)  WSI QFP-44P 97+ The devices low VCC detection circuitry protects the users system from
118 (136)  BBINA SOP-8 98+
119 (66)  AD SOP8 02+ The AC ACT843 bus interface latch is designed to elimi- nate the extra p
11A (16)  HIT DO-35 05+ Single chip low power UHF transmitter 369.5 MHz to 395.9 MHz frequency o
11B (11)  IDTAGON BGA 248   Temperature range TMIN to TMAX: C20C to +85C.   Guaranteed by
11C (65)  N/A 1206 for each channel of each device listed in this data sheet, absolute ma
11D (28)  IR 07+ Digital Signal Processor (DSP) Block • Playback mode which support
11E (17)  SANKEN High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC =
11F (7)  high-frequency tube SANKEN 04+ The KESRX05 is a single chip ASK (Amplitude Shift Key) Receiver IC. It
11G (3)  SHARP DIP The HYM71V65801 X-Series are Dual In-line Memory Modules suitable for easy
11H (8)  MICROCHIP QFN-8P小体 6+ CS falling edge to first SCLK falling edge SCLK logic high pulse width S
11I (1)  TXENABLE has two purposes. In all modes, TXENABLE must be high for the DA
11J (5)  LEXMARK 0020 Devices sold by AMI are covered by the warranty and patent indemnification
11K (10)  PHILIPS 05+ PLCC Note 3 a) In addition the voltage between the V a pin and either input pin
11L (16)  ST BGA 00+ Transmit data, K-generator channels A and B. In multiplexed channel mode,
11M (12)  N/A N/A N/A In general, if tAOH is greater than the minimum required input hold time
11N (25)  These devices can be used as two 8-bit transceivers or one 16-bit trans
11P (5)  MICROCHIP QFN-8P小体 6+ 2. Use only a true open-collector device (preferably a discrete   t
11S (22)  NEC SOD-123 05+ Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee
11T (21)  05+ SMD Rectifiers advanced line of power MOSFET transistors. The efficient geo
11U (2)  • 1/2x, 1x, 1x, 2x Ref • 10 MHz to 166.67 MHz operating rang
11V (3)  ROHM LL34   Input Current, IIN   Input Capacitance, CIN2, 3 LOGIC OUTPUT
11W (1)    Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS
11X (2)  PANASONIC BGA 2004 SPI Serial Memory The memory portion of the device is a CMOS Serial EEP
11Y (1)  SANYO SOT-23 * On products compliant to MIL-PRF-38535, this parameter is not productio
11Z (2)  The A0, A1, and A2 are the device address inputs that are hardwired or
1-2 (101)  AMP 07+ T510 capacitor series are suggested over many other tantalum types due t
12- (54)  EVERLIGHT 08+ 7575 (*) R-L Filter to be used according to EUTELSAT recommendation to impleme
12. (49)  KSS N/A Because the PMOS device behaves as a low-value resistor, the dropout volt
120 (2105)  AVX 6992   4.4.2 Group B inspection. Group B inspection shall be conducted in
121 (725)  BGA 9700HF Electrical Characteristics Absolute Maximum Ratings Recommended Operat
122 (159)  05+ PLCC The MAX3873A is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery a
123 (113)  ON 00+ Dielectric: Polyethylene terephthalate film. Capacitor electrodes: Vacuum
124 (99)  NPC SOP During discharge and charge, the bq2050 monitors VSR for various threshol
125 (233)  ST QFP The DC restoration function is achieved through the use of a strobed oper
126 (76)  TSSOP 05+ State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera
127 (112)  TSSOP 05+ These three functional blocks are identical in operation, so only a single
128 (146)  37 LUCENT 00+ The standard shipping format for serial types includes a lower or upper fa
129 (147)  NS SOP-16 9842+ Specifications Outline Dimensions Pin Connections and Short Description
12A (27)  MHS Digital-to-Analog Propagation Delay   to 90% of Output Digital-to-
12B (14)  9925 will cause large currents to flow which can result in a de- stroyed unit
12C (183)  MICROCHI SOP-8 04+ Notes: (1) The isolated RFx port has a return loss of approximately -3 d
12D (45)  01+ Theseversatile devices are usefulfor driving a wide range of loads incl
12E (3)  05+ DIP   AD5382-5 is calibrated using an external 2.5 V reference. Temperat
12F (94)  MICROCHIP QFN-8P 6+ s FEATURES   q Operating Voltage4.7 to 13V   q Stereo mode &
12G (2)    Operating temperature range is C40C to +85C.   Guaranteed by
12H (8)  QFP QFP A host reads, programs, or checks the status of the bq2022 through the hi
12I (6)  MELCHER N/A Two different interfaces are supported on the network side. The first is
12J (1) 
12K (10)  富士通 Figure 1 shows a typical bq2060-based battery pack ap- plication. The cir
12L (24)  SST 04+ As long as store input is low, data is continuously transferred from the
12M (10)  100 天龙伟业 靳先生 • Two digitally controlled potentiometers and two   voltage co
12N (21)  FAIRCHILD QFN 05+ PARAMETER Supply Voltage VCC Supply Current VCC Undervoltage Lockout Re
12P (14)  BOTHHAND N/A 0612+ Each of these Schottky-clamped data selectors multiplex- ers contains in
12R (5)  It contains 8 bidirectional and digitally controlled analog switches. A
12S (43)  WP 220 06+   As the beams attached to the central mass move, the distance from
12T (27)  N/A module 2005+ The ADS8381 is an 18-bit, 580 kHz A/D converter. The device includes a
12V (11)  TOSHIBA The MC68307 (shown in Figure 1) contains a static EC000 core processor, m
12W (4)  2. Using a CAS-before-RAS refresh cycle. CAS-before-   RAS refresh
12X (1)  TOSHIBA 23-12V 05+ Separate ground pins are provided for each BTL output to minimize induc
12Y (1)  TOSHIBA 23-12v 05+ † Pulsed-output patterns are tested during  AC switching at 2
12Z (1)  CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Bo
1-3 (125)  TYCO 641 NOTES:   1. Dimensions are in inches.   2. Metric equivalents
13- (30)  ★★★ 03+ NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI
13. (23)  TXC   The K4S161622D is 16,777,216 bits synchronous high data rate Dyna
130 (312)  N/A The output power as a function of the supply voltage is measured on the o
131 (206)  HARRIS SOP   The RC4700 incorporates a complete floating-point co-processor on
132 (175)  PHI QFP 00+ Stresses above those listed under Absolute Maximum Ratings may cause pe
133 (151)  70 BBADS Fujitsus Flash technology combines years of EPROM and E2PROM experience
134 (99)  SENSYM Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LST
135 (142)  FUJ 04+ QFP   One 64 x 8 (512-bit) Configuration Zone   Three 64 x 8 (512-
136 (101)  INTEYSIL DIP 99 • Supply of instruction fetch memory addresses; the   sequenc
137 (121)  FUJ QFP properties. Used for insulation and protection of cables, harnesses, and
138 (46)  PHI 2007 C40 >Ta > +85 C Over Vin range Over Io range Includes set-point,
139 (102)  TO126 Thereareadditionalprovisionsfor demonstrating DDX-2000 functionality.The
13A (8)  05+ DIP Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and
13B (4)  PLHLIPS 99+ SOP-24 A burst write access to an active row is initiated with the WRITE comman
13C (11)  798 This protection function is splitted in 2 stages. As shown in Figure A3,
13D (5)  QTC DIP OVUVSEN (Over-Voltage/Under-Voltage SENse) Pin 19 - This analog input pi
13E (1)  Panasonic SOP14S 2007+ The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of da
13F (4)  The COP87LxxCJ/RJ Family OTP (One Time Program- mable) microcontrollers
13G (6)  Infineon TQFP144 03+ presented in straight binary or twos complement formats. An out-of-range
13H (6)  AMD PLCC Notes: 1. For Max. or Min. conditions, use appropriate value specified un
13J (2)  The frequency characteristic for the phase locked loop is established by
13K (3)  2008 The EP7311 is designed for ultra-low-power operation. Its core operates
13L (3)  97 QTC 051Q The EL2244 and EL2444 are dual and quad versions of the popular EL2044.
13M (3)  N/A 4.5xX2.5 • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883
13N (12)  SEC 07+ The following document specifies Spansion memory products that are now of
13P (5)  FAIRCHILD QFN 05+ The MSM514262 supports three types of operation : random access to RAM por
13R (2)    NCS2510 is a 1.0 GHz current feedback monolithic operational ampl
13S (3)  FAIRCHILD QFN 05+ When the CY7C42x1V is in a Width-Expansion Configuration, the Read Enabl
13T (11)  ZILOG N/A 95+ All part numbers end with a place code, designating the silicon-die revis
13U (7)  05+ SMD Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when
13V (4)  PANASONIC SOD323 Product of input modulation: f = 44MHz, Df = 135MHz p-p and f = 6MHz,Df =
13W (4)  07+ Parameter SENSOR INPUT   Measurement Range1   Nonlinearity &
13X (2) 
13Z (4)  TSOP8S 2007+ Notes: 1. See test circuit and waveforms. 2. This parameter is guarant
1-4 (209)  AMP/TYCO N/A Two Instructions/clock Execution Load/Store Architecture Sixteen 32-bi
14- (113)  接触开关 Collector-Emitter Saturation Voltage  IC = 10 mAdc, IB = 1.0 mAdc
14. (55)  KSS Figure 6 on page 6 shows a correct trigger sequence. The positive edge of
140 (335)  PHI 2007 1A Peak Output Drive Capability 0.8V Reference Voltage Shuts off both dr
141 (139)  LUCENT Command Prefix - Commands, except A/, begin with the AT prefix. The &quo
142 (188)  HONEY MODULE N/A
143 (163)  POWEREX SOP This combination of excellent dc performance with a common-mode input vol
144 (197)  e ( eurosil ) 8623Y CAUTION: These devices are sensitive to electrostatic discharge; follow p
145 (314)  TI SOP16S 2007+ Collector-to-Emitter Voltage Continuous Collector Current, each IGBT C
146 (226)  LUCENT It also has a microprocessor compatible input configuration, which provid
147 (126)  NS SMD 00+ Information furnished is believed to be accurate and reliable. However, S
148 (181)  TY 220   Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (t
149 (84)  05+ SMD
14A (13)  151 CYERESS 01+ This pin is the positive supply pin, and should always be the most posi
14B (6)  05+ SMD n Complete specifications at 1A load n Output voltage tolerances of 2%
14C (8)  HAR SOP-3.9-16P 6+ This IC is a sync detection circuit for obtaining the best reception state
14D (61)  FEVTI DIP 99 Rectifier circuit Receives radio wave via the (external) antenna circuit
14E (2)  The HY29F080 can be programmed and erased in-system with a single 5-vol
14F (10)  J.S.T N/A 2006 The exposed paddle (EP) 48-pin TQFP has features that provide a very low
14G (4)  AT&T The MAX1737 EV kit is a fully assembled and tested surface-mount board. F
14H (3)  LEXMARK 01+ 474 This program is presented in a format that includes several hands-on labo
14J (1)  CONTINUOUS BURST READ: During a continuous burst read, any number of addr
14L (11)  N/A 00+ DIP-14 32-position digital potentiometer 10 kΩ, 50 kΩ, 100 kΩ
14M (9)  SOP 05+ The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x1
14N (15)  TO-252 06+ 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters Independent Tra
14P (8)  96 The Am29LV652D offers access times of 90 and 120 ns and is offered in a 6
14R (2)  Infineon TQFP144 03+   This device is designed for FM tuning, general frequency control
14S (6)  SOP-14 This is a dual-function pin. In the CY Standard mode, the EF function is
14T (11)  MOT OO SOP-8 The M37273MFH-XXXSP is single-chip microcomputers designed with CMOS si
14W (5)  08+ When the VO2Cont terminal voltage is set to 0.5V or less, the output volt
14X (10)  N/A AMKOT 04+ The SP8480 Series are complete monolithic data acquisition systems, featu
14Y (1)  The MAX1698 EV kit contains a switching-regulator cur- rent-source circui
14Z (2)  VITEC DIP 0 Access Time Break-Before-Make Delay Time Enable Delay (On, Off) Settlin
1-5 (247)  AMP/TYCO 0734   MX7575KN0C to +70C18 Plastic DIP   MX7575JCWN0C to +70C18 Wi
15- (330)  00   The 33879 device is an 8-output hardware-configurable, high-side/l
15. (30)  KSS DIP-8 08+ The transceiver is fully compatible with the IEEE 802.3 standard for aut
15/ (1)  They are intended for applications in the RF front end, in wideband ap
150 (417)  VISHAY/IR 2007+   Blanking the noise pulse in this way is very effective, but some
151 (317)  ST 05+ SOP AHI,BHI,CHI - are the logic inputs for controlling the switching of the
152 (139)  PIC N/A  The Hynix HYM72V32M636T6M Series are Dual In-line Memory Modules su
153 (120)  SC SMD 05+ After Preset Mode inputs have been changed to one of the modes, the ne
154 (127)  TEMIC 00+ MQFP The Fairchild Switch FSTD16861 provides 20-bits of high- speed CMOS TTL
155 (134)  04+ QFN The SDRAM employs state-of-the-art technology for high performance, relia
156 (103)  TYCO 天线座 07+ This device provides 64 bytes of general-purpose flash memory, 8 bytes
157 (157)  MAT DIP 2006 Security functions Security functions implemented in the cabinet: -Mecha
158 (172)  100 天龙伟业 靳先生 Output power at 1dB compression for the 158RP80 is +30dBm when biased for
159 (67)  HIT SOP20M 2007+ NOTE: EP circuits are designed to meet the DC specifications shown in the
15A (13)  2000 LUCENT These octal buffers and line drivers are designed specifically to impro
15B (5)  To retain data, 2,048 refresh cycles are required in each 32 ms period,
15C (32)  IR TO-263 05+ Stresses beyond those listed under "absolute maximum ratings" m
15D (18)  原装无铅 07/08+ Notes: 1. All InGaN LEDs represented here are IEC825 Class 2. See Applic
15E (44)  N/A FUJ 04+ Forward Voltage Reverse Voltage Peak Wavelength Spectral Bandwidth Res
15F (62)  AMD PLCC Figure 6 on page 6 shows a correct trigger sequence. The positive edge of
15G (18)  SANYO SOt-523 05+ The Am79213/Am79C203/031 Advanced Subscriber Line Interface chip set im
15H (3)  DIP DIP Hynix HYMD264G726(L)4-K/H/L series incorporates SPD(serial presence detect
15J (13)  AMD PLCC 07+ The MAX1108/MAX1109 low-power, 8-bit, dual-channel, analog-to-digital con
15K (131)  Y5U 05+ The 15KV102M and 15KV102M are 37,748,736-bit Synchronous Static Random Ac
15L (5)  00+ PLCC Decrementer, time base, and real-time clock (RTC) from the PowerPC  
15M (14)  100 天龙伟业 靳先生 The FAN2500/01 allows the user to utilize a wide variety of capacitors c
15N (28)  PHILIPS QFN 03+ In addition to the column address, A10 (= AP) is used to invoke autoprec
15P (6)  2001   Pin(40-39)&,Pin(37-36)   Pin(1-2) : (40-39)   Pi
15Q (1)  TO-3P 02+ This IC is a voltage regulator IC developed using the CMOS process. Super
15R (1)  This specification contains ADVANCE INFORMATION data. ISSI reserves the r
15S (16)  The FR families are lines of standard single-chip microcontrollers each b
15T (20)  IR 07+ s GENERAL DESCRIPTION   The NJU7700/01 is a low quiescent current
15U (14)  PHI 03+ TSOP-3.9-8P The input/output pins (I/O 0 through I/O15) are placed in a high-impeda
15V (8)  TI 03+ Notes: 1. For Max. or Min. conditions, use appropriate value specified u
15W (28)  SHINDENGEN N/A The EL8300 is designed for a number of general purpose video, communicati
15X (2)  TOSHIBA 23-15V 05+ Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch 24 10/100 Mbps A
15Y (1)  TOSHIBA 23-15V 05+ controlled. A built-in level shifting is included to allow them an inpu
15Z (1)  台产 SOT89 • PNP Silicon Epitaxial Planar Transistors • Suited for low
1-6 (362)  AMP/TYCO N/A This family of differential line receivers offers improved performance
16- (93)  N/A TAMURA 04+ The PALCE29MA16 has 16 macrocells, one for each I/O pin. Each I/O macro
16. (72)  KSS DIP-8 08+   Protection diodes are employed at all pins except V+ and V- of th
160 (527)  QFP 06+ This family of fully featured hot swap power controllers targets applicat
161 (299)  N/A MAX 04+ The 1618MUB/1618MUB8/1618MUB9 use constant- frequency voltage-mode archit
162 (387)  IR TO-249AA Non-Isolated 00+ The small form factor and simple interface make the DataFlash Card ideal
163 (162)  AV QFP 01+ The CY7C245A has an asynchronous initialize function (INIT). This functi
164 (228)  LUCENT 9838 Each channel consists of an ultralow noise preamplifier (LNA), an X-AMP&
165 (321)  MOTOROLA Soft phase switching + direct PWM drive PWM control based on both a DC
166 (130)  SSOP 38503 AMKOR Active High Master Reset. When logic HIGH, the internal dividers are res
167 (132)  NS PLCC20 0014+ These transceivers typically draw 910µA of supply current when unlo
168 (98)  DIP 38503 N/A conversion efficiency. Additional features include an integrated input
169 (79)  In order to saturate the power switch and reduce conduction losses, ade
16A (46)  ST 9244 1.1 Greece has waited for long for character 10/14, which is the Greek Qu
16B (1)  EXPANSION IN (XI)   This input is a dual-purpose pin. Expansion In (
16C (245)  IR TO-257AA 00+ ON Semiconductor andare trademarks of Semiconductor Components Industries
16D (18)  N/A HIT 04+ current specifications. The correct current designation for a CSR part n
16E (3)  Description The HFBR-5710L optical transceiver is compliant with the
16F (188)  VISHAY/IR 2007+ HY5V16CF is offering fully synchronous operation referenced to a positive
16G (6)  TOSHIBA TO- * 3.2 Qualification. Devices furnished under this specification shall be
16H (2) 
16I (2)  NXP SSOP 06+ FEATURES Microprocessor Compatible (6800, 8085, Z80, Etc.) TTL/CMOS Com
16J (1)  The ICS91309 provides synchronization between the input and output. The
16K (5)  NEW AND ORIGINAL NEC 05+ The APL5523 is a dual low dropout regulator with output1 with 3.3V/0.5A a
16L (70)  01+ SSOP
16M (69)  MARCON 06+ The CMX866 Programming Register should only be written to when the Progra
16N (23)  ST TO-220 0728vgc+ The regulator voltage output used to power the load. A nominal output cap
16P (54)  0522+0525 DIP-10   The SOA curves combine the effect of these limits. For a given ap
16Q (1)  Stresses beyond those listed under Absolute Maximum Ratings may cause per
16R (58)  B DIP-16 00+   (Unless otherwise indicated, copies of the above specifications, s
16S (79)  IR TO-257AA 00+ Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group
16T (66)  IR TO- • Full Duplex Audio Signaling Processor   Single Tone   S
16V (122)  LAT PLCC 2001 † Stresses beyond those listed under absolute maximum ratings may c
16W (8)  RUBYCON N/A Each ACEX 1K device contains an embedded array and a logic array. The em
16X (17)  5000 04+ This device contains circuits to protect its inputs and outputs against d
16Y (34)  RUBYCON 0701 1,980 The EC4558 consists of two high performance opera- tional amplifiers. T
16Z (18)  TI 01+ Figure 1 illustrates the ISL6118 operational waveforms, showing the relat
1-7 (285)  AMP/TYCO N/A Testing of the switching parameters is modeled after testing methods spec
17- (60)  N/A 04+ TQFP64 † Stresses beyond those listed under absolute maximum ratings may c
17. (14)  KSS DIP-8 08+   Thaler Corporation has developed a nonlinear compensation network
170 (1542)  TSSOP 05+ I. Devices are 100% production tested at 25C and guaranteed   by de
171 (250)  MOT PLCC52 06+ These devices feature 3-state outputs designed specifically for driving h
172 (438)  PH 07+ If HIGH at reset, this pin operates as a second write enable. If LOW at r
173 (234)  OSEP 01+ TSSOP24   , LTC and LT are registered trademarks of Linear Technology Corpor
174 (126)  IC 集成电路 74HC10N,652 The receive FIFO consists of an 8 stage memory and 2 counters generating
175 (242)  MOT PLCC44 06+ use in common rectifier circuits, Table 1 indicates suggested factors fo
176 (199)  NS DIP8 07+ This MOSFET is designed to replace a single MOSFET and parallel Schottk
177 (132)  IC 集成电路 74HC132D,653 The TLE202x, TLE202xA, and TLE202xB devices are precision, high-speed, lo
178 (120)  INTERSIL PDIP16 02+
179 (122)  DIP 05+ FEATURES 1 pC Charge Injection   2.7 V to 5.5 V Dual Supply +2.7 V
17A (19)  TSSOP-8 07+
17B (3)  We constantly strive to improve the quality of all our products and docum
17C (17)  76 UNITRODE With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as t
17D (49)  ON SOP-8 04+   Operating temperature range is as follows: 0C to +50C.   Fre
17E (15)  Panasonic SOP14S 2007+ When the output load exceeds the current-limit threshold or a short is pr
17F (25)  ST Notes:  *All PIO signals are shared with other physical pins. See t
17G (3)  TOSHIBA CCD N/A Thus, the first step in designing the antenna circuit is to measure the
17H (6)  TI SOP20W 2007+ DIR input. The enable input G can be used to disable the device so that
17J (1)  At the high-impedance Bypass pin, care must be taken in the circuit layo
17L (14)  LEXMARK 02+   The ST92F124/F150/F250 microcontroller is de- veloped and manufa
17M (1)  FAI DIP 02+ A resistively-coupled lower-power complementary pair offers extremely l
17N (6)  FSC A 1% resistor must be connected between pin 4 and pin 7 to set the output
17P (4)  Supported by FPGA Foundation™ and Alliance Development Systems -
17R (4)  1. VDRM and VRRM for all types can be applied on a continuous basis. Rati
17S (88)  XILINX 01+ SOP18 The IGBT technology is the key to International Rectifier's advanced line
17T (17)  05+ SMD 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD
17V (15)  XILINX PLCC  Gallium arsenide (GaAs) is a substance used in the products describ
17W (2)  Both current generators may be driven using an on- board temperature se
17X (2)  NOTES: • Use a 0.1 µF capacitor on VDD to decouple the powe
17Y (1)  When the Deserializer synchronizes to the Serializer, the LOCK pin is l
1-8 (152)  HDK 原装 • Compact slim body saves space Thanks to the small surface area o
18- (29)  UTC SOT-23 07+ Introduction Safety Agency Approvals Emission Standards Input Specifica
18. (23)  KDS * Specifications will vary with foreign standards certificati
180 (329)  AVX 08+ The ADC122S051 is a low-power, two-channel CMOS 12-bit analog-to-digital
181 (1012)  AVX 08+ (Both segment mode and common mode) ! Supply voltage for LCD drive: 15.0
182 (1165)  NS SOP16W 2007+ The device contains an 8-bit instruction register that controls the ope
183 (52)  IR MODULE N/A ESD (electrostatic discharge) sensitive device. Electrostatic charges as
184 (69)  KSS 05+ High-speed ADC Family Companion Chip Selectable 1:2 or 1:4 DMUX Ratio Po
185 (163)  COPYRIGHT DIP-20 • 4 channels of 16-bit reload timer (including 1 channel for REALOS
186 (72)  N/A Bulk OK. This is a brownout protection feature. The pin moni- tors the b
187 (76)  SOP SOP The AD8021 is a very high performance, high speed voltage feedback ampli
188 (101)  KONG 798 The DSP includes a flexible, software-programmable phase-locked loop (PLL
189 (65)  IR SOP Data flow from A to Y is controlled by the output-enable (OE) input. Th
18A (6)  ON 02+ On the card-side the TRAKKER monitors two program- mable under-voltage
18B (5)  7 Data transfer starts with the falling edge of the CS signal. Data must ap
18C (44)  N/A N/A 03+ (Unless otherwise specified, all typical values are for 25C ambient tempe
18D (5)  KYOCERA 02+ The basic unit of logic on the ispLSI 1048 devices is the Generic Logic
18F (38)  The output capacitors must be located as close to the Vout terminal of th
18K (38)  MOT 04+   is a registered trademark of VIA Technologies, Incorporated. Wind
18L (13)  ICT 00+   LIFE SUPPORT POLICY Integrated Device Technology's products are
18M (9)  2008 The MAX1393/MAX1396 micropower, serial-output, 12- bit, analog-to-digital
18N (14)  PHILIPS QFN 03+ Note 2: Electrical Table values apply only for factory testing conditions
18P (23)  SIEMENS 00+ TO263-2脚半 The LT ®3027 is a dual, micropower, low noise, low drop- out regulat
18R (9)  A buffered output-enable (OE) input can be used to place the nine outpu
18S (4)  ZAPX 01+   Figure 4 illustrates the differential or gauge configuration in t
18T (22)  07+   These Darlington arrays are furnished in 18-pin dual in-line plas
18U (1)  MOT PLCC44 07+ Thermal Resistance (Typical, Note 2)JA (oC/W)   E (PDIP) Package .
18V (29)  PLCC 99+ 5V, 3V, and 3.3V versions available High accuracy output voltage Guara
18X (1)  TOSHIBA 23-18V 05+ High-power capability PowerSO-36; V cc /2 compatible inputs; Junction
18Y (1)  SANYO 06+ SOT-23 A capacitor is connected between AFSM (Pin 11) and GND for smoothing of
18Z (1)  This device has been designed to meet the increasing demand for white S
1-9 (54)  0 07+ 2180 Voltages (typically 1% of its specified value) while the Bipolar output
19- (165)  AMIS PQFP80 True Dual-Ported memory cells which allow simultaneous access of the same
19. (25)  Kyocera Short Circuit Current Output Current Transition Time Maximum Transmis
190 (352)  IC 集成电路 74HC245N Bus interface   • Maximum of 25 MHz internal operation rate
191 (176)  N/A 0603LED The 191NW Series (Secure FPSLIC family) shown in Table 1 is a combination
192 (197)  Molex connector 06+ Transmit Error Active high. When an error happened in the transmit data
193 (73)  N/A D C 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-   er (activa
194 (337)  VISHAY 06+   Switching behavior is most easily modeled and predicted by recogn
195 (379)  VISHAY 06+ The LM74As 4.5V to 5.5V or 3.0V to 3.6V supply voltage range, low suppl
196 (55)  FAI BGA 99 These devices contain up to 22 inputs and 10 outputs. They incorporate th
197 (68)  PHI SSOP-5.2-24P 6+ The LM2462 is an integrated high voltage CRT driver circuit designed fo
198 (34)  IC 集成电路 74HC4020D,652 Note 1: Dice are designed to operate with junction temperatures of -40C to
199 (136)  SP 05/06+
19A (7)  TSSOP 05+ The circuit uses state-of-the-art PHEMT technology with self- biasing cu
19C (44)  SENSYM 0243 Notes:  1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Dont
19D (2)  high-frequency tube USA 04+   This 32-bit buffer/driver is built using advanced dual metal CMOS
19E (1)  Panasonic SOP14S 2007+ • Undervoltage conditions on VREG (UVREG) or on the   interna
19F (15)  SMD-16 IBM 90+ Power   Supply: 2.5 V to 5.25 V operation   Normal mode: 75 &m
19G (11)  N/A DIP 2006 A temperature compensated comparator circuit monitors the level of VCC.
19H (2)  99+ 5 The HT71XX series is a set of three-terminal low power high voltage regu
19I (1)  LT
19J (2)    The MC623 consists of a positive temperature coefficient (PTC) te
19L (5)  The TAN 350 is a high power COMMON BASE bipolar transistor. It is desig
19M (3)  The 19MT050XF is a high-bandwidth FET bus switch utilizing a charge pump
19N (5)  ST 99+ TO-263 starts and the wiper voltage VFB of the feedback potentiometer moves in
19P (2)  ACE PLCC PLCC The ERAL instruction erases the entire 128´16 or 256´8 memory
19S (2)  ROSENBERGER N/A 06+ organized as 525,288 words by 16 bits. It is fabricated using ISSI's hi
19T (14)  IR 07+ Low Cost Complete H-Bridge 8 Amp Capability, 75 Volt Maximum Rating Sel
19U (4)  An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
19V (1)  ITT SOT23 G760 is a single chip solution for fan speed control, packaged in a space
19X (2)  The combination of low offsets, low noise, very low input bias currents,
19Y (1) 
1-A (1)  The clear function is synchronous. A low level at the clear (CLR) input s
1A/ (1)  n Sector Protection   C Any combination of sectors may be   l
1A0 (6)  N/A 二极 N/A Temporary Address Register (16 Bit Incremen- tor/Decrementor) Base on t
1A1 (33)  LITTER Data Outputs: A 4-bit parallel data word, forming a HEX character represen
1A2 (17)  † Stresses beyond those listed under absolute maximum ratings may c
1A3 (25)  MITEL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch
1A4 (4)  SOP24W 2007+ n Sector Group Protection   C Sectors may be locked in groups of tw
1A5 (9)  hit SOP14 Drain-to-Source Breakdown Voltage 100 Gate Threshold Voltage …2.0
1A6 (7)  93 SOP • Three video anti-aliasing or reconstruction filters •
1A7 (1)  IOR BGA 02+ • High efficient InGaN technology • Chromaticity Coordinate
1A9 (2)  wide variety of external capacitors, and the compact SOT23-5 surface-mou
1AA (5)  ALCATEL 93+ BGA As an alternative to a full chip erase or a plane erase, the device is or
1AB (383)  695 ALCATEL 00+ These N-Channel enhancement mode power field effect transistors are produ
1AC (3)  MODEL 模块5脚 08+ No products described or contained herein are intended for use in surgica
1AD (5)  AMBIT TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another
1AE (1)  n Multi-Input Wakeup (on the 8-bit Port L) n Analog comparator n Modula
1AG (2)  ICS USOP-8P 6+ Single Schottky rectifier suited to Switched Mode Power Supplies and hi
1AH (2)  N/A 741 • Fully Compliant to IrDA 1.0   Physical Layer Specifications
1AM (2)  N/A N/A N/A Note 3 The maximum power dissipation must be derated at elevated temperat
1AN (2)  99 Integrating Error Amplifier. The integrating error amplifier (Amp2) amp
1AS (9)  N/A Serialized data bits are output from the DO output, starting in ascending
1AT (5)  ATMEL 05/06+ 1) Skew is defined as the absolute value of the difference between the ac
1AV (98)  KYOCERA 2520 05+ Power Integrations may make changes to its products at any time. Power Int
1AX (1)  N/A TQFP 05+ TerminatorTM technology in StratixTM and Stratix GX devices helps prevent
1AZ (3)  TOSHIBA Data Polling bit (DQ7). During the internal write cycle, any attempt to
1B- (3)  The buried macrocell also supports input register capability. The buried
1B0 (7)  IR 1800 Line Drivers are available for the HEDS-55xx/56xx series and the HEDS-90
1B1 (8)  AMIS PLCC68 07+ The HSMS-270x series of clipping/clamping diodes are Schottky devices. A
1B2 (5)  AD DIP (MAX2338 EV kit, VCC = +2.7V to +3.3V, fPLNAIN = fPMIXIN = 1930MHz to 1990
1B3 (4)  AD DIP DIP (LSU), System Register Unit (SRU), and a Branch Processing Unit (BPU) 16-
1B4 (6)  FUJITSU TSSOP20 Modulator The modulator is a direct conversion double balanced quadratu
1B5 (2)  AD DIP 04+ The TLV320AIC2x implements an extensive power management; including devic
1B7 (1)  MX 00+ SOP44 XTAL1 and XTAL2 are the input and output, respectively, of an inverting a
1BA (2)  *2) Lamp frequency of inverter may produce interference with horizontal s
1BC (3)  • Avalanche rated parts available • Package with DCB cerami
1BE (6)  Testing of the switching parameters is modeled after testing methods spe
1BK (1)  These LCA functions are established by a configuration program which is
1BL (3)  MOT 015/ † Stresses beyond those listed under absolute maximum ratings may c
1BM (3)  ALCATEL 07+ Vishay Siliconix maintains worldwide manufacturing capability. Products ma
1BQ (2)  IR Throughout this document, the term 2.7 V refers to the full voltage ran
1BS (2)  There are two types of flash EEPROM data memory storage. The 2K bytes of
1BT (4)  TI 01+ CS to WR Setup time WR to Status delay WR pulse width CS to WR Hold
1BV (3)    Figure 4 illustrates the differential or gauge configuration in t
1BX (2)    Please be aware that an important notice concerning availability,
1C- (4)  2008 • Flame retardant encapsulant (UL 94V-0). • Completely encaps
1C0 (7)  IBM QFP 07+/08+ Figure 1 shows the waveforms associated with the commu- tation decoder lo
1C1 (15)  DL 05/06+   Designed with Motorolas advanced SMARTMOS, the 34923 is designed f
1C2 (15)  2008 RAC is an open drain output pin that marks the end of a row. At the 8 kH
1C3 (2)  DL 06+/07+ The UC1524, UC2524 and UC3524 incorporate on a single monolithic chip al
1C4 (1)  The phase detector and the M divider force the VCO output fre- quency to
1C5 (1)  DL 05/06+ • UltraFast: Optimized for high operating up to   80 kHz in h
1C8 (3)  3-A Low-Dropout Voltage Regulator Available in 1.5-V, 1.8-V, 2.5-V, and 3
1CA (8)  QFP44 The Hynix HYM7V65801B Q-Series are 8Mx64bits Synchronous DRAM Modules. The
1CB (1)  n CCITT G.726 compatible at 40, 32, 24, 16 kbps n ANSI T1.301 compatible
1CC (1)  滤波 04+ Total harmonic Distortion Second Order CCIF Intermodulation distortion
1CD (2)  9718   International standard packages   Low RDS (on) HDMOSTM proces
1CK (1)    AD5381-5 is calibrated using an external 2.5 V reference. Temperat
1CL (2)  EXPANSION OUT/HALF-FULL FLAG (XO/HF)   This is a dual-purpose output
1CM (11)  WORLD-CHIP NOTE 1 The maximum allowable change observed over the entire temperature
1CO (2)  SOP24W 2007+ GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling
1CP (5)  ROHM SOT-23 06+
1CQ (1)  TEXAS 96 S0 Pin   The S0 pin is used to select the mode of operation as sho
1CR (2)  Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PC
1CT (6)  TI 01+ There is an optional inverter that can be connected between the first a
1CU (1)  s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8
1CV (2)  INNOCHIPS 4(0603) 04+   4.4.2 Group B inspection. Group B inspection shall be conducted in
1CW (1)  The PGA is digitally controlled with 10-bit resolution on a dB scale, r
1CX (5)  08+ The only difference between the HC and HCT versions is the input level
1CY (2)  SHARP TO-263-5 Notes:  7. Part (a) of AC Test Loads and Waveforms is used for all
1CZ (9)  252 07+ The AHCT367 devices are designed specifically to improve both the perfo
1D- (1)  PLCC 00+ Notes: (1) Unit case mounted on Al plate heatsink (2) Units mounted on
1D/ (1)  The VCXO may be coarse tuned by a programmable ad- justment of the crys
1D0 (3)  FUJITSU 00+ TQFP-100 Transfect cells at high cell density. 90-95% confluence at the time of t
1D1 (33)  1735 • Molded construction provides superior strength and   moistur
1D2 (3)  FUJI SOP The VHC164 is an edge-triggered 8-bit shift register with serial data e
1D3 (6)  N/A A Additional design entry and simulation support provided by EDIF 2 0 0 an
1D4 (3)  The luma input is driven by either a low impedance source of 1VP-P or th
1D5 (6)  JAPAN QFP 01+ Upon power-up or reconfiguration, an FPGA enters the Master Serial mode
1D6 (4)  LSI 13. LOCAL/DISTANT SELECTOR (L/D)   Press this button to select local
1D7 (1)  N/A The clock is generated by a phase-locked oscillator (PLO). The PLO is loc
1D8 (3)  N/A If a system designer needs more than 16 outputs with the features just de
1DA (5)  95 • 2-Wire Interface interoperable with I2C.   400kHz data trans
1DC (1)  MODEL 模块 08+ While monitoring SR1 and SR2 for charge and discharge currents, the bq206
1DD (31)  CORPORATION 07+ Note 1: Absolute Maximum Ratings are those values beyond which the life
1DF (2)  100 天龙伟业 靳先生 track-and-hold input circuit. Selected by a high Write Enable input, the
1DG (2)  MICROCHIP QFN-8P小体 6+ Hynix HYMD132725B(L)8J-J series is unbuffered 184-pin double data rate Syn
1DH (2)  MRS initializes the read and write pointers to zero and sets the output re
1DI (244)  FUJI 741   The 33879 device is an 8-output hardware-configurable, high-side/l
1DK (1)  hp CDIP/28 98+ Note 5: TJ is calculated from the ambient TA and power dissipation PD acc
1DL (1)  Specifications to -40C are guaranteed by design and not production tested.
1DM (5)  N/A For the pre-recorded voice prompts, the Philips International Language
1DN (1)  Add to the Autovector Interrupt Acknowledge Cycle section on page 3-38: I
1DQ (2)  HP PGA-48 6+ The information provided herein is believed to be reliable at press time.
1DR (2)  HP MD_RDY is an output signal to the network processor, indicating a data pa
1DS (1)  Shift clock signal input for the PCMIN and PCMOUT signal. The frequency,
1DT (4)  STANDARD DEFINITION MODE   Hue Accuracy   Color Saturation Acc
1DX (1)  Agilent 2007 In all modes, this regulator is current-limited. When VBB < 8 V, the
1DY (3)  94 Xilinx development software supports XC7300 EPLD design using third-par
1E- (1)  memory system applications results in full-speed, error-free operation wi
1E/ (1)  Stresses above those listed under Absolute Maximum Ratings may cause perm
1E1 (4)  N/A N/A N/A The REC input is an active-HIGH record signal. The device records wheneve
1E2 (3)  MOT SOP-28 99+ The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low O
1E3 (2)  MOT • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) 
1E4 (3)  QFP 00+ VRI is reference voltage terminal for input signal.   If reference v
1E5 (2)  MOT SOP-28 99+ Any switching configuration that provides three or more timeslots between
1E9 (3)  Infineon 02-04+ Supports continuous mode transmission and reception on all serial channels
1EA (2)   SRAM • Power dissipation   Operating : 40 mA Max &n
1EC (2)  Note 1: INL and DNL is measured using a sine-histogram method. Note 2: In
1ED (1)  4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature
1EF (1)  For example, if the OTG Host were to turn off VBUS, and the USB20H04 were
1EK (12)  (1) VOS is defined as the average of the positive and the negative switch
1EN (1)  The Raytheon RM3183 line receiver is the companion chip to the RM3182 li
1EP (1)  N/A The ULN2001A, ULN2002A, ULN2003A, and ULN2004A are monolithic high-voltag
1ER (1)  Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem
1ES (1)  Panasonic 3*4 M/A-COM offers six unique PIN diodes in five industry standard, low cos
1ET (1)  An input capacitor of 1.0 µF (min) should be connected from VIN to
1EX (1)    Switching behavior is most easily modeled and predicted by recogn
1EZ (1)    The LM393 series are dual independent precision voltage comparator
1-F (1) 
1F/ (1) 
1F0 (3)  n/a n/a Stresses above those listed under Absolute Maximum Ratings may cause per
1F1 (9)  ANM 04+ The SX2 command interface is used to set up the SX2, read status, load d
1F2 (3)  The device offers access times of 65, 70, 90, and 120 ns, allowing high
1F5 (2)  MOT SOP-28 99+ All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output opera
1F6 (7)  FUJI 二极管模块 To transmit optical data via fiber cables, signals must be converted from
1F9 (1)  N/A N/A N/A The integrated low-power high-efficiency dc-dc con- verter is designed
1FA (5)  N/A N/A N/A C40 >Ta > +85 C Over Vin range Over Io range Includes set-point,
1FC (3)  HP QFP208 The attached spice model describes the typical electrical characteristics
1FD (1)  FSC O7+
1FE (5)  HP AICPGA5050-455 04+ Unless specifically noted all references to the 80C186EB apply to the 80
1FG (1)  Xilinx in-system programmable products provide a mini- mum endurance le
1FI (7)  FUJI SOP Operating and Storage temperature: -65ºC to +175ºC Thermal Resi
1FK (1)  SOT3 In addition, the device has on-chip error detection and correction circ
1FN (1)  ATMEL 89+ The offset voltage is trimmed on-chip to eliminate the need for external
1FQ (3)  AGILENT PBGA37.5*37.5 04+ Inductance Tolerance: 10% standard. 5% available. Insulation Resistanc
1FR (1)  ATMEL 07+ This evaluation kit being sold by TI is intended for use for ENGINEERING
1FS (3)  HP QFP128   The Toshiba 1FS1-0001 consists of a gallium arsenide infrared emit
1FT (6)  SEWON N/A Mon. : Oscillation frequency monitor terminal. The output is given from
1FU (2)  HP QFP N/A 5VSBY is the bias supply of the ISL6537A. It is typically connected to th
1FW (8)  HP QFP QFP * 3.4 Interface and physical dimensions. Interface and physical dimension
1FZ (2)  HP QFP100 The ICL8052 or ICL8068/lCL71C03 chip pairs with their multiplexed BCD o
1G- (1)  Digital multiplexed output data bus. ADC output data (d15:d0) is availabl
1G1 (1)  Collector-to-Emitter Breakdown Voltage Continuous Collector Current Co
1G2 (2)  N/A TQFP-64 00 The HYM72V64736(L)T8 Series are Dual In-line Memory Modules suitable for
1G3 (2)  MOT SOP-28 00+ • Burst mode operation • Auto & self refresh capability (
1G4 (1)  TOS 409  4.5.2 Group B inspection. Group B inspection shall be conducted in
1G6 (1)    Available in standoff voltage range of 6.5 to 200 V   Low ca
1GA (1)  Quasi Resonant Converter Controller Internal Burst Mode Controller for
1GB (1)  AMD PLCC The regulated voltage output. An output capacitor of 1µF is recomme
1GC (1)  SMD SMD Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee
1GG (1)  AGILENT 2001+ THSSOP The addition of a bias circuit in conjunction with this process results i
1GH (2)  东芝 Notes:  3. All input pulses are supplied by a frequency generator w
1GR (1)  FEATURES  HIGH SURGE CAPABILITY TRANSIL ARRAY  IPP = 40 A (8/
1GT (3)  QFN 38503 Agilent This pin adjusts the peak current limit of the Sense FET. The feedback 0.
1GU (1)  TOSHIBA   Figure 4 illustrates the differential or gauge configuration in t
1GV (2)  PALCE PLCC-20 96+ When battery charging is initiated, the charger enters the prequalificati
1GW (4)  The power input pin of the regulator. Typically a large storage capacitor
1H- (1)  The AD581 is a three-terminal, temperature compensated, monolithic bandg
1H0 (19)  N/A N/A 08+ Programming voltage. No overshoot above the specified max voltage is pe
1H1 (16)  N/A N/A N/A • NPT3 IGBT   - low saturation voltage   - positive temp
1H2 (3)  IR C Over 3,000 Gates of PLD with 16 macro cells C Use for peripheral glue
1H3 (5)  TI N/A 08+ FR CPU   • 32-bit RISC, load/store architecture, 5-stage pipe
1H4 (3)  TI N/A 08+ The 1H439-003U-368 uses advanced trench technology to provide excellent R
1H5 (2)  MAX SOP16W 2007+ Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR
1H6 (3)  TI N/A 08+ The bar antenna is a very critical device of the complete clock receiver
1H7 (2)  3. Hitachi makes every attempt to ensure that its products are of high qu
1H8 (3)  MOTO BGA N/A We constantly strive to improve the quality of all our products and docum
1H9 (4)  Stresses above the ratings listed below can cause permanent damage to the
1HA (2)  The 1HAW20005AAL is an 8051 compatible microcontroller based on the Dal
1HD (2)  The UCC3808 family offers a variety of package temperature range options,
1HF (1)  NS N/A 08+ The information contained herein is the exclusive property of Prime View
1HJ (3)  MIT Module 06+ All programmable elements, including the routing resources, are control
1HK (1)  • MII interface supports an additional 100FX or 100TX   connec
1HL (2)  N/A The Zarlink MT8816 is fabricated in Zarlinks ISO- CMOS technology providi
1HN (3)  ST SOT223 03+ FEATURES 12-Bit ADC with Fast Conversion Time: 2 µs Two Single-En
1HS (1)  Description The HYS 64V64220GU and HYS 72V64220GU are industry standard
1HX (2)  KDS SMD 2004   This is the inverting power amplifier output, which is used to pr
1I- (3)  HARRIS 2007 System timing is simplified in that the on-chip edge triggered register
1IA (1)  MICROCHIP QFN-8P小体 6+ • Power-save pull-up resistor built-in (AL series) Frequency divid
1IB (1)  Data Inputs/Outputs: Inputs array data during program operation, when CE
1IC (7)  NSC O7+ The F157A is a high-speed quad 2-input multiplexer Four bits of data fro
1IE (1)  The 5V device is fully accessible and data can be written or read only whe
1IG (2)  EUPEC 2007 Development software for the CY7C371i is available from Cy- presss Warp2
1IP (1)  The reconstruction filters provide a 5th order Butterworth response with
1-J (1)  Notes: 1. For Max. or Min. conditions, use appropriate value specified u
1J0 (1)  The device is organized as a 12-bit or 24-bit bus switch. When OE1 is LO
1J1 (3)  SmartVoltagetechnology provides a choice of Voc and V,, combinations,as s
1J4 (2)  TOSHIBA SIP4 98+ Bus timing data is shown in Figure 4 and Figure 5. Data transfer may be i
1J6 (2)  Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain
1JE (1)    The SY100EP57V is a high-speed, low-skew, fully differential PEC
1JU (2)  TOSHIBA The power good (PG) function serves as a reset for a USB hub controller.
1JV (1)  Figure 6a shows the control circuit for a typical downward expander whil
1-K (3)  1. One output at a time for a maximum duration of one second. VOUT = 0.5V
1K- (3)  Designed with an internal P-channel MOSFET pass transistor, the 1K-8 main
1K0 (5)  MOT 03+ VBIAS (VCC, VBS) = 12V, CL = 1000 pF, CT = 1 nF and TA = 25C unless othe
1K1 (4)  Hynix HYMD216726A(L)6-M/K/H/L series is designed for high speed of up to
1K2 (4)  05+ BGA The PI6C2308A provides 8 copies of a clock signal that has 150ps phase er
1K3 (6)  IBM QFP 90
1K5 (2)  2007 • High-speed access times:   8, 10, 12 and 15 ns • Hig
1K6 (2)  ST SOP-8 04+ Used as a high-side switch, a p-channel MOSFET in a totem-pole arrangem
1K8 (1)  In addition to the column address, A10(=AP) is used to invoke autoprechar
1KA (8)  DSI n/a Validation of a token first involves an authentication device sending a
1KC (7)  Note 6: The Absolute Maximum Ratings are those values beyond which the sa
1KD (1)  N/A True clock of differential pair CPU outputs. These are current mode outp
1KE (1)  SANYO SOP-36 04+ n LM78L05 in micro SMD package n Output voltage tolerances of 5% over
1KM (1)  Notes:  2. NC pins are not connected to the die.  3. E3 (DNU)
1KO (1)  2. The ALD1704 has complementary p-channel and n-channel input   di
1KR (1)  N/A 325 The KS8721BL/SL automatically configures itself for 100Mbps or 10Mbps a
1KS (7)  HUNTER 07+ Note : 1. Load and line regulation are specified at constant junction tem
1KV (36)  WM Y5P 05+ • Measures local and remote temperature • Highly accurate rem
1KW (1)  • RESET • Watchdog • External 0 • External 1 R
1L0 (18)  FSC TO-220 06+ GND (Pin 5): Device Ground Pin. This pin is ground for the boost switch,
1L2 (3)  WFP8S 2007+ Input to the PWM comparator. The current flowing in the MOSFET is sensed
1L3 (2)  • OUTE function*1 (fail-safe function)   Outputs a signal used
1L4 (1)  The CMX866 has the capability to generate single or dual user-defined tone
1L5 (1)  Thermal Resistance (Typical, Note 5)JA (oC/W)   PDIP Package . . .
1L7 (1)  NVE DIP8 00+ The basic unit of logic on the ispLSI and pLSI 1032E devices is the Gen
1L9 (1)  Peak amplifier dissipation occurs at an output voltage of (V+)/2, or 50%
1LB (1)  SANYO DIP Intel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or Inte
1LC (1)  SIMENS 18 tively near distance as shown in Fig. 1, a spot is produced at (a). Whe
1LD (2)  SIEMENS Stresses in excess of the absolute maximum ratings can permanently damage
1LE (2)  • Single supply with operation down to 1.8V • Low-power CMO
1LF (1)  The OPA680 represents a major step forward in unity gain stable, voltage
1LG (2)  Track: This is an analog control input that enables the output voltage t
1LH (1)  Notes: 1. Test conditions assume signal transition times of 3 ns or less
1LJ (2)  The serial circuit and primary winding of the flyback transformer are con
1LK (1)  Notes: 1. See test circuit and waveforms. 2. This parameter is guarant
1LO (5)  The voltage and current amplifiers have a 3MHz gain bandwidth product t
1LP (3)  HP DIP16 (1) MTTF calculator available at http://www.motorola.com/semiconductors/r
1LQ (8)  SIEMENS Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and per
1LR (3)  HP DIP Stresses above those listed under Absolute Maximum Ratings may cause perm
1LS (3)  25 Agilent When a sync pulse is detected on channel A (CVBS), the DC restore loop is
1LT (2)  HP O7+ This formula guarantees that Q2 and Q4 will always have suf- ficient bas
1LU (3)  hp DIP/20   VOLTAGE OUTPUT versus APPLIED DIFFERENTIAL PRESSURE   The di
1LV (1)  HP DIP 07+ A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port
1LX (1)  Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserv
1LY (1)  HP QFP100 DMS (Data Management Software) allows systems to easily take advantage o
1M (1)  The LM123 is a three-terminal positive regulator with a pre- set 5V outp
1-M (1)  N/A N/A N/A Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds300C (1) Str
1M0 (34)  FAIRCHILD SOP/DIP 08+ NOTES: 1. There are four mailbox locations per port written to and read f
1M1 (6)  DL 05/06+ 3.3V power supply LVTTL compatible with multiplexed address Dual bank op
1M2 (3)  Fuji 03+ Data is parallel loaded into the SN65LVDS151 input latches on the first r
1M3 (2)  The 1M3416P1 COM Port Adapter is a simple, low-cost passive adapter which
1M4 (10)  LATTICE QFP-48 04 • Power-on Reset (POR), Power-up Timer (PWRT),   and Oscillat
1M5 (6)  The Rambus RIMM modules are offered in a 184-pad 1mm edge connector pad p
1M6 (4)  The HPMD-7905 enhances the sensitivity and dynamic range of CDMA receive
1M8 (2)  Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
1MA (4)  Each device requires only a single 3.0 volt power supply for both read a
1MB (299)  FUJI TO-220 04+ Split power: Core VCC (3.0C3.6 V currently) I/O VCC (3.0C3.6 V current
1MC (3)  hp DIP/20 Solderability: 90% coverage after 5 second dip in 235C solder following
1MD (6)  HP PLCC 03+/04+ • IEEE 802.3u D5 repeater and management compatible • Suppor
1ME (2)  Hp 798 Sleep Mode. Control input SLEEP is used to minimize power consumption w
1MF (4) 
1MG (3)  Agilent 2007 plex Instruction Set Computer (CISC): compact code, on- chip memory and I
1MH (16)  ROHM H9 The OPA689 is a wideband, voltage feedback op amp that offers bipolar ou
1MI (3)  100 天龙伟业 靳先生 Thispreliminarydatasheetcontainsthe specifications for the Advanced Boot
1MJ (3)  hp plcc plcc The 1MJ2-0201 is a high-performance electrically erasable programmable re
1MK (6)  hp 2007 Limits in standard typeface are for TJ = 25˚C and limits in boldfac
1ML (10)  hp 2007 n 9-bit Inverting BTL transceiver meets IEEE 1194.1   standard on B
1MM (1)  HP QFP QFP RS is perhaps the easiest to measure accurately. The V-I curve is measur
1MN (8)  ROHM SOT-163 The internal VCO is based on the TLC2932 and TLC2933s ring oscillator. It
1MO (2)  The DTMF generator will output one of 16 standard tone pairs determined b
1MP (2)  N/A 97+ Note A. Junction Temperature Calculation: TJ = TA + (PD x JA). Note B. T
1MQ (3)  HP QFP QFP IE is used to enable/disable writing into memory. IE high level enables wr
1MS (5)  HP 9734
1MT (4)  ROHM 96+ Note: 1. Commercial Product: TA=0 to 70C, otherwise specified.   In
1MU (2)  HP QFP160 DATA MEMORY Data memory consists of a 512-bit RAM organized as 8 data r
1MV (11)  HP QFP100   Improved Sensitivity Due to the reduction in size of the optical
1MW (2)  HP 2008 The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed ba
1MX (14)  2000 HY 94+ The standard device offers access times of 90, 100, 120, and 150 ns, al
1MY (1)  AGILENT BGA Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On This i
1MZ (5)  is held high, the decoding function is inhibited and all the 8 outputs
1N0 (8)  CAN CAN
1N1 (578)  IR DO-5 † Stresses above those listed under Absolute Maximum Ratings may c
1N2 (504)  DSI n/a SG1 applied to TP29 ,TP31 and TP33,SG10 applied to TP41,SG2 applied to T
1N3 (965)  IR DO-205AB (DO-9) 00+ Maximum ratings are those values beyond which device damage can occur. M
1N4 (1851)  S 金属帽 8836 Differential LO input with high input impedance. This pin requires extern
1N5 (2066)  VISHAY 07+ Ground reference to LVDS and CMOS circuitry. For the LLP package, the D
1N6 (550)  MICROSEMI Note 1) The specified condition Tj = 25C means that the test should be ca
1N7 (204)  ST 06+HOT Spartan series devices achieve high-performance, low-cost operation thr
1N8 (56)  csf n/a   A gear-tooth sensing system consists of the sensor IC, a back- bi
1N9 (261)  FAIRCHILD 03+ The transmit section of the CY7C9689 HOTLink can be con- figured to acc
1NA (5)  ALLEGRO 04+ (5) When designing your equipment, comply with the guaranteed values, in
1NB (8)  52   These devices are a synchronous (clocked) FIFO, meaning each port
1NC (1)    All values at 20C (68F).   Relay has fixed coil polarity. &n
1ND (1)  • Ensure that the control loop has enough phase margin   at t
1NE (1)  N/A N/A N/A These dual N- and P-Channel enhancement mode power field effect transisto
1NF (7)  The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC availabl
1NK (4)  Enables the associated DDR2 SDRAM command decoder when low and disables th
1NO (1)  All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold m
1NP (1)  Notes: 1. For Max. or Min. conditions, use appropriate value specified u
1NQ (2)  BI SSOP24 UL Recognized File # E-96005 Plastic package has Underwriters Laborator
1NR (2) 
1NT (22)  ALCATEL 07+ ‡ Stresses beyond those listed under absolute maximum ratings may c
1NU (3)  2537 NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale
1NV (4)  IR SOT-223 05+   The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Mega- bi
1NY (1)    High input sensitivity IFT = 2.0 mA   600/800 V blocking volt
1O2 (1)  Stresses beyond those listed under "absolute maximum ratings may cau
1O7 (1)  SOD 95+ The Hyundai HYM71V633201 H-Series are 32Mx64bits Synchronous DRAM Modules.
1OE (1)  Panasonic SOP14S 2007+ To overcome this limitation, TI design engineers developed the patented E
1OM (1)  POWER-ON INITIALIZATION When power is first applied, power-on reset circ
1P- (1)  Direct Interface to ISA and PCMCIA with No Wait States Flexible Bus Inte
1P0 (21)  SIEMENS 0805 01+ If after 480 µs of low time the I/O line did not return high, eit
1P1 (11)  APOLLO SOP 2000   Wide inductance range in small package.   Flame retardant coa
1P2 (1)  A thermal warning indicator is activated by the DDX-2100 when its junctio
1P3 (3)  SOP 01+ The M41T315Y/V/W is supplied in a 28-lead SOIC SNAPHAT® package (whi
1P4 (1)  PHILILPS 04+PB A FIFO memory is a storage device that allows data to be written into a
1P5 (6)  ANAREN The MAX2602 includes a high-performance silicon bipolar RF power transist
1P6 (1)  Generating A Voltage Output Signal C The 0 to 20 mA output of the 5B39-
1P8 (5)  PHILIPS • An accelerated 80C51 CPU provides instruction cycle   times
1P9 (1)  When ACK is asserted and JAM is HIGH, an active IMR+ device is in a col
1PA (5)  PH I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim
1PB (5)  The PI5A317A is a single-pole single-throw (SPST), normally closed (NC)
1PC (3)  03+ DIP Load Regulation Since the IRU1010 is only a three-terminal device, it is
1PD (2)  MICROCHIP QFN-8P小体 6+ Each port contains a burst counter on the input address regis- ter. The
1PF (4)  MICROCHIP QFN-8P小体 6+   The device has several operating modes dependent on the applied
1PG (1)  Absolute Maximum Ratings (If not specified Tl=25)   ItemSymbolCond
1PH (1)  Discription Data bit 0 of Transmit Symbol, true data Data bit 1 of Tra
1PI (3)  The device is enabled when the EN pin is connected to a low-level input v
1PL (2)  Built-in H and V driving circuit (built-in input level conversion circuit
1PM (63)  850 07+ The circuit board used in the final application should use RF circuit des
1PN (2)  Benchmark Class 2 C General purpose ceramic capacitors are called Class 2 capacitor
1PR (6)  RF 99 NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected w
1PS (147)  PHILIPS 08+PBF current requirement makes the usage of MAS9162 easier and low in cost.
1PT (1)  NAVMAN 05+ Notes:  1. Minimum DC input is C0.3V. During transactions, input ma
1PV (1)  q GUARANTEED SPECIFICATIONS WITH   12V AND 15V SUPPLIES q 1/2LSB M
1PX (1)    Please be aware that an important notice concerning availability,
1Q0 (3)  DIP-36 99+ 29 (leap year - valid until year 2100), 30 and 31 day months are made a
1Q1 (1)    The PT5810 Excalibur™ series of integrated switching regula
1QC (1)  The HC688 and HCT688 are 8-bit magnitude comparators designed for use i
1QL (3)  HP QFP 99+Original Note: 1. Commercial Product : TA=0 to 70C, unless otherwise specified &n
1QM (8)  HP 9949+ I/ODescription  Data inputs for an 18-bit bus.  When RS is se
1QP (2)  AGILENT BGA2727 00+/04+ Note A: Characteristic data has been developed from actual products teste
1QQ (7)  HP BGA AM26LS32A Devices Meet or Exceed the Requirements of ANSI TIA/EIA-422-B,
1QS (8)  50 Infineon These devices consist of four independent voltage comparators that are
1QU (6)  AGILENT QFP-100P 07+ m1: arrangement number of special module. The number of special module &n
1QX (2)  Testing of the switching parameters is modeled after testing methods spec
1QZ (2)  hp 2007
1-R (1)  This demonstrates that with more complex devices the con- cept of CPD gr
1R0 (1)    The Pm29F002 is a 2 Megabit, 5.0 Volt-only Flash Memory organized
1R1 (1)  Integrated 4-band Graphic Equaliser Adjustable output stage filter compen
1R2 (2)  SOP6 02+ n No special start-up sequence required between   clock/data and /P
1R3 (2)  04+ SMD Broadcom®, the pulse logo, ContentAwareTM, and Connecting everything&r
1R5 (18)  东芝 2. Characteristics in microcontroller interface mode • 3-bit/4-bit
1R7 (2)  1.2 ARCHITECTURE The COP8SAx family is based on a modified Harvard archi
1R8 (2)  The ISAnet evaluation kit meets the needs of custom- ers working with e
1R9 (1)  The write operation is initiated by forcing #CE and #WE low and #OE high.
1RA (5)  TOKO SMD 04+ NOTES: (1) All devices receive a 1s test. Failure criterion is > 5 pul
1RB (5)  HP PLCC68 03/+04+ No Connection. PWM2 output (10V open-drain). PWM1 output (5V open-drain)
1RC (1)  HP DIP16 07+ ∙ 2,097,152-word 8-bit configuration ∙ Single 5V power su
1RD (6)  MICROCHIP QFN-8P小体 6+ Hardware data protection measures include a low VCC detector that automa
1RE (1)  ‧Telecommunications (PC, Electronic notepad) ‧Measuring and T
1RF (6)  MOT DIP 91+ These LCA functions are established by a configuration program which is
1RG (2)  HP PLCC84 03/+04+ Active Voltage Programming: Special precautions should be taken when mak
1RH (3)  HP QFP100 Cell balancing of each cell is performed via a cell bypass path, which is
1RJ (3)  HP This chip, when properly assembled, displays characteristics similar to t
1RL (2)  HP QFP100 Note 6: Limits are 100% production tested at 25˚C. Limits over the o
1RM (2)  HP QFP160 5V TOLERANT INPUTS HIGH SPEED: tPD = 5.2ns (MAX.) at VCC = 3V POWER D
1RN (2)  HP QFP100 The MT88E45B contains a 1200 baud Bell 202/CCITT V.23 FSK demodulator and
1RO (3)  1000 INTEL board, minimum creepage and clearance requirements must be met as specif
1RR (3)  7 NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the
1RS (5)  AGILENT QFP 04+ The M59PW064 is a 64Mbit (4Mbx16), Mask- ROM pin-out compatible, non-vo
1RT (14)  QFP32 The ThinPakTM Package is a perforated, metalized ceramic substrate attac
1RU (3)  AGILENT 0144+ RC: RC is the oscillator timing pin. For fixed frequency operation, set
1RV (6)  AGILENT BGA 05 D Operating Power Supply Range 6 V v VBAT v 36 V D Reverse Battery Prote
1RW (1)  HP CBGA 00+ Parameter Supply Voltage VDD to Ground Data Input, Data Output, VB Colu
1RX (4)  1000 The CMOS PLD devices feature variable product terms, flexible outputs, an
1RY (4)  AGILENT CGA3535 03+/04+ 3. Processing before Initialization Note: When power is first supplied,
1RZ (2)  AGILENT 00+ PLCC-84 Use NC Relays for power control up to 5 A or Tape recorders, temperatu
1S1 (34)  DSI n/a Multiplexed PCI address/data bus. A bus transaction consists of an addres
1S2 (86)  NEC 金属帽 49 hold the output low (Figure 2). This resistor value, though not critical
1S3 (3)  EP 06+ whichever occurs first. During the Erase operation, the only valid reads
1S4 (9)  AD DIP Caution: Stresses beyond those listed under Absolute Maximum Ratings may
1S5 (2) 
1S6 (5)  AD AUCDIP System address / data bus low byte. These lines make up the least signif
1S7 (1)  DIP 04+ Signals an interrupt when overflowing Supports Timer Clear when a match
1S8 (1)  Notes: 5. Distribution data sample size is 450 samples   taken fro
1S9 (7)  NEC The AVR core combines a rich instruction set with 32 general purpose work
1SA (2)  AUK SOT-23 05+ Information in this document is provided in connection with Skyworks Solut
1SB (7)  5 QFN This device is a low-cost, high-speed, JFET-input operational amplifier w
1SC (2)  TOSHIBA SOD-323 Accesses to the MBAR register at long word $3FF00 are internal only, and
1SD (11)  N/A N/A N/A NanoStar and NanoFree Packages Supports 5-V VCC Operation
1SE (3)  The autostore configuration is designed to provide wiper position storage
1SF (1)  GaAs powder and vapor are hazardous to human health if inhaled or ingest
1SG (12)  The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 9
1SH (4)  HP PLCC68 03/+04+ Stresses above those listed under Absolute Maximum Ratings may cause perm
1SI (9)  N/A All Rights Reserved. Circuit diagrams utilizing Fujitsu products are inc
1SJ (3)  25 HP For applications requiring powerful I/O capabilities, the Z86319 provide
1SK (3)  ELNA NanoStar and NanoFree Packages Optimized for 1.8-V Operat
1SL (3)  17 HP This document is a general product description and is subject to change wi
1SM (966)  ON DO-214AC 05 On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System D
1SP (17)  HP QFP100   The JEDEC MO-127 12-pin Power Dip™ package (see Package Out
1SR (83)  ROHM   (Unless otherwise indicated, copies of the above specifications, s
1SS (623)  国产KEC SOT-323 Data bits to be transmitted through the cable ports are received from the
1ST (5)  Following qualification, the bq2000 fast-charges NiCd or NiMH batteries u
1SV (423)  TOSHIBA An HR700 Series converter in still air (other than convective currents)
1SX (2)  VBB is an analog input which establishes the threshold for all single end
1SY (1)  The LTC6101 monitors current via the voltage across an external sense res
1-T (1) 
1T0 (2)  2150 Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output
1T2 (2)  These PIN / Preamplifier combinations are coupled into a custom quantizer
1T3 (81)  SONY 1206 Note: These are stress ratings only. Stresses exceeding the range specifi
1T4 (41)  SONY SOD-523 05+ 15 kV Using Human-Body Model (HBM) Meets or Exceeds the Requirements of
1T5 (1) 
1T6 (3)  ST QFN 06+ The RC2207 has a typical drift specification of 20 ppm/C. The osci
1T9 (1)  Enhanced 2D Graphics Controller Supports pixel depths of 8, 16, 24 and 3
1TA (2)  All formulas are simplified. Refer to the last paragraph of this subsect
1TB (1)    This device employs the Schottky Barrier principle in a large area
1TC (4)  CLARE SOP16P 04+ The RTC provides a set of continuously running counters driven by separat
1TE (1)  Digital Filter, DAC and Analog Low-Pass Filter Blocks • Digital de
1TF (12)  INT SOP-8 05+
1TH (2)  HITACHI stock DESCRIPTION The 1THY400A1200V is a multichip memory device con- taining
1TJ (2)  The ISL9V2040D3S, ISL9V2040S3S, and ISL9V2040P3 are the next generation
1TL (4)  To successfully enter the low-power mode, the MC68SEC000 must first be in
1TM (2)  INTEGRANT 5650 04+ The 16-bit control-data input implements the device-control functions. Th
1TN (1)  FUJI GTR PMD assumes no liability for applications assistance or customer product
1TP (1)  HP PLCC44 03/+04+ A six-byte command (Enter Single Pulse Program Mode) sequence to remove t
1TQ (2)  HP PLCC 00+ A logic input control to enable the regulator output. When EN is asserted
1TR (1)  MURATA N/A 3,000 The PLCC-2 SMT LED products with a viewing angle of 120 is ideal for ins
1TS (2)  SGS DIP 87 Note 3 The HALT mode will stop CKI from oscillating in the RC and the cry
1TT (2)  DIODES SOT-23 • Bidirectional data strobe(DQS) • Differential clock inputs(
1TU (4)  7 Notes: 1. Unused inputs must be held high or low to prevent them from fl
1TV (10)  The signal input can be directly coupled to large voltage signals, or i
1TW (1)  HP QFP160 The FCT240T devices are octal buffers and line drivers designed to be e
1TX (3)  HP QFP QFP NOTES:  1. Dimension are in inches.  2. Metric equivalents are
1TY (1)  19   Specification is not production tested, but is supported by charac
1TZ (9)  HP 798 High Efficiency Over Wide Load Current Range 0.8% Output Voltage Accuracy
1U- (1)  This Power MOSFET is the latest development of STMicroelectronis unique
1U/ (1)  The 1U/35V provides 2,048 bits of serial EEPROM memory organized as one
1U2 (1)  Note 13: Skew is defined as the absolute value of the difference between
1U5 (3)  IC. Each display can be directly interfaced with a microprocessor, thu
1U7 (1)    Technology • Positive VCE(ON)Temperature Coefficient ̶
1UF (38)  N/A 3525B型钽电容 00+   The RC4700 also incorporates a two-entry instruction TLB. Each en
1V0 (1)  04+ Note 10: This specification is guaranteed but not tested. The limits repr
1V1 (1)  29 XINGER O1 CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL R
1V5 (30)  FS 07+ n 1 µs instruction cycle time n Three multi-source interrupts ser
1VA (5)  ICOMPRESSION BGA 99 Theory of Operation The AEDR-8300 series combines an emitter and a detec
1VB (2)  The potentiometers of the DS1267 can be connected in series as shown in Fi
1VK (1)  ! Fixed 175kHz Switching   Frequency ! Constant Frequency Voltage
1W0 (3)  MOTO SMD SMD Working Peak Reverse Voltage Range C 5.8 to 171 V Standard Zener Breakdo
1W1 (20)  HITACHI Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation
1W2 (12)  The AH342 is a bipolar latching hall IC with a pair of complementary push
1W3 (38)  ST 2007 DO-35   The AP2011 integrates Pulse-width-Modulation (PWM) control circuit
1W4 (33)  PYUNG CHANG The ispLSI 2096 and 2096A are High Density Program- mable Logic Devices
1W5 (8) 
1W6 (6)  Topic Section 1, Overview Section 2, Features Section 3, Maximum Tolera
1W7 (4)  ROHM 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATING may ca
1W8 (9)  n Complete specifications at 1A load n Output voltage tolerances of 2%
1W9 (2)  • Plastic package has Underwriters Laboratories   Flammabilit
1WB (1)   tsk(p)See Figure 350 † All typical values are at VCC = 3.3 V
1WI (1)  N/ 05+ This IC functions in a variety of CPU systems and other logic systems, to
1WY (1)  • RKE - Remote Keyless Entry • Button Status - Indicates what
1X0 (8)  Notes: 5. Distribution data sample size is 500 samples taken from 5 diffe
1X1 (34)  SHARP SOP 97 Edition 16.3.99 Published by Siemens AG, Bereich Halbleiter, Marketing-
1X2 (17)  SHARP sop16
1X3 (18)  SOP SHARP 00+ multiplier. This is analogous to using an elephant to carry a twig. It m
1X4 (6) 
1X5 (12)  Xinger 2008 Hynix HYMD216646A(L)6J-J series is unbuffered 184-pin double data rate Syn
1X6 (6)  ANM 04+ Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause perm
1X7 (3)  N/A N/A N/A Figure 2 combines the MAX6160 with the MAX5462 (a 100-kilohm, 32-tap digi
1X8 (4) 
1X9 (4) 
1XA (3)  SHARP . 05+   Pin Function PWM block control power supply Focus control inpu
1XB (6)  49 DC Tests  TC = +250C, 1 Cycle, t = 1.0 s Test 1  VCE = 7.8 V
1XF (4)  † Stresses beyond those listed under absolute maximum ratings may c
1XJ (2)  Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current
1XK (1)  HP QFP160 Pins 5, 6, 7, 8, 11, 12, 13: SCK, DATA1, BCK, LRCK, DATA2, DATA3, DATA4
1XN (2)  AHA 05+ QFP This bit is a volatile latch that powers up in the LOW (disabled) state
1XP (1)  Use of the H8S/2149 and H8S/2169 F-ZTAT™ enables compact, high-perf
1XR (1)  1) Anti-shock memory controller corresponds to EDRAM,   and SDRAM.
1XS (2)  PARAMETER Reference Voltage VREF Voltage Fb Voltage Line Regulation UV
1XX (2)  hp QFP 03/+04+ AC97 3D audio controller Supports Serial ATA controller Fast PCI ATA/33/
1XY (3)  The FDC10 and FDC10-W series offer 10 watts of output power from a 2 x 1
1XZ (1)  95 The receive section of the CY7C9689 HOTLink accepts a se- rial bit-strea
1Y7 (2)  QFP- It is possible to connect the Data In and Data Out pins together. Howev
1YA (4)  Digital common or ground. This separate ground carries currents from the
1Z0 (1)  Protection features of this controller IC include a set of sophisticated
1Z1 (10)  TOSHIBA CAOUT: This is the output of the wide bandwidth current amplifier and on
1Z2 (5)  SANKEN ♦ Available to MIL-STD - 883 ♦ MIL-M38510/11501BXA - JAN790
1Z3 (2) 
1Z5 (2)  TOSHIBA   The ITI7004G2-LC hosts two of LSI Logics LSIFC929, 2 Gbit controll
1Z6 (1)  256K x 4 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (
1Z7 (1)  TOSHIBA The SPS product family is specially designed for an off-line SMPS with
1Z8 (1)  Data on the Qs output is transferred to a second out- put (Qs) on the f
1ZA (2)  MICROCHIP QFN-8P小体 6+ < Notice > 1. When power supply of S1T8825B is disconnected, CLK,
1ZB (25)  TOSHIBA Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserv
1ZC (5)  TOSHIBA 04+ DIP   For propagation delays, tpdh refers to the specified signal going
1ZE (2)  The output at pin 5 is at a ÒhighÓ state when the PLL is ou
1ZG (1)  MICROCHIP QFN-8P小体 6+ The high-side driver is designed to drive low rDS(on) N-channel MOSFETs.
1ZI (1)  MICROCHIP QFN-8P小体 6+ The W29EE512 includes a data polling feature to indicate the end of a prog
1ZP (1)  MICROCHIP QFN-8P小体 6+ The AD7683 is a 16-bit, charge redistribution, successive approximation,
1ZS (3)  SOP 05+
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