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EMPTY FLAG (EF)   The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty.   The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK).
Write (WRITE) The WRITE instruction includes 8-bit or 16-bit of data to be written into the specified register. After the last data bit has been applied to DI, and before the next rising edge of SK, CS must be brought low. The falling edge of CS initiates the self-timed programming cycle. After a minimum wait of 250ns (5V operation) from the falling edge of CS (tcs), DO will indicate the READY/BUSY status of the chip if CS is brought HIGH. This means that logical "0" implies the programming is still in progress while logical "1" indicates the selected register has been written, and the part is ready for another instruction. (shown in figure 6)
Reducing Noise Through Signal Processing A/D converter outputs contain noise that has as its origins quantization noise, noise that comes from aperture related effects and noise from other sources. Often it is desirable to lump all of these together and just treat them as noise and work towards reducing them. One technique that can be used for this is simply to over- sample the input then digitally low pass filter the output. If we take the example above, where we have a 100MHz carrier modulated with a 100kHz signal, if we sample at a rate of 2MHz instead of a rate of 1 MHz, the noise is distributed over a band that is twice as wide. If the digital signal is then filtered, and the half of the band that does not contain the signal of interest is thrown away, the result is a 3dB improvement in the signal to noise level. This could be carried on as far as the speed of the converter permits with the cost being carried mainly in the power and complexity of the digital filtering hardware. Imagine sampling the signal at 1GHz, then filtering out all but the lowest 500kHz band to obtain the equivalent of 1MHz sampling: we would be able to obtain a 30dB improvement in SNR over what we would have sampling at 1MHz.
Parr number/PDF Mfg Pack D/C Descrpion
Y010   Y010 Y010 PDF Download TSOP8S 2007+ Description The HCPL-90xx and HCPL-09xx CMOS di
Y011   Y011 Y011 PDF Download 01+ lated from: f = fO [1 - FTC (TO -TC)2]. Typically
Y014   Y014 Y014 PDF Download ALPHA SOP-6 High Capacitive-Drive Capability Typical Delay T
Y017   Y017 Y017 PDF Download The LPV511 is a micropower operational amplifier
Y01878   Y01878 Y01878 PDF Download Small 10-Lead MSOP or DFN Package Uses Tiny Capa
Y01886   Y01886 Y01886 PDF Download 1. The VCC supply to each optoisolator must be b
Y0001   Y0001 Y0001 PDF Download I Embedded 16 bit CompactRISCTM Micro Controlle
Y001   Y001 Y001 PDF Download The programmable features of the ICS8430I-61 sup
Y002   Y002 Y002 PDF Download SMD OSC1 and OSC2 are connected to an RC network or a
Y005   Y005 Y005 PDF Download 9745 Normally the PWM comparator will sense a ramp c
Y006   Y006 Y006 PDF Download 07+ The thermally efficient package mea- sures only
Y007   Y007 Y007 PDF Download 9801 Therefore, do not burn, destroy, cut, crush, or c
Y010   Y010 Y010 PDF Download TSOP8S 2007+ Description The HCPL-90xx and HCPL-09xx CMOS di
Y011   Y011 Y011 PDF Download 01+ lated from: f = fO [1 - FTC (TO -TC)2]. Typically
Y014   Y014 Y014 PDF Download ALPHA SOP-6 High Capacitive-Drive Capability Typical Delay T
Y017   Y017 Y017 PDF Download The LPV511 is a micropower operational amplifier
Y01878   Y01878 Y01878 PDF Download Small 10-Lead MSOP or DFN Package Uses Tiny Capa
Y01886   Y01886 Y01886 PDF Download 1. The VCC supply to each optoisolator must be b
Y020   Y020 Y020 PDF Download 00+ 20000 TSSOP-8   A word-width-select option is provided on
Y026   Y026 Y026 PDF Download CAUTION: Stresses above those listed in Absolute
Y030   Y030 Y030 PDF Download 2008 Hynix HYMD216M726(L)6-K/H/L series is unbuffered
Y05392   Y05392 Y05392 PDF Download   The PTH05060W non-isolated power module i
Y0545S   Y0545S Y0545S PDF Download FAIRCHLD TO-220 05+ All of the Ultra37000 devices are electrically e
Y05661   Y05661 Y05661 PDF Download The AC280 and ACT280 are 9-bit odd/even parity g
Y076054   Y076054 Y076054 PDF Download MOT PLCC44 03/05+ FEATURES 1 A Output Current at 2.5 V 0.6 V Ma
Y0778703   Y0778703 Y0778703 PDF Download  with a single bar completely filling the p
Y08-242B   Y08-242B Y08-242B PDF Download   PAGE operations allow faster data operati
Y08SV-272B   Y08SV-272B Y08SV-272B PDF Download N/A SANKOSHA 05+ Pin Description Address 0-2. These pins are use
Y08SV-312B   Y08SV-312B Y08SV-312B PDF Download SANKOSHA The average output from PC3, fed to the VCO via
Y1000042(ISSUEC)   Y1000042(ISSUEC) Y1000042(ISSUEC) PDF Download Note: Stresses greater than those listed under
Y1004DN   Y1004DN Y1004DN PDF Download FAIRCHLD TO-220 05+ While P0.0 anbd P0.1 differ from standard TTL ch
Y1006DN   Y1006DN Y1006DN PDF Download FAIRCHILD TO-220 01+   GENERAL DESCRIPTION   The NJM78M00
Y100822C203DQE   Y100822C203DQE Y100822C203DQE PDF Download Frequency select latch input pin / 14.318 MHz re
Y100822R401RG   Y100822R401RG Y100822R401RG PDF Download THESE MATERIALS ARE PROVIDED "AS IS" W
Y100AA2C802RB   Y100AA2C802RB Y100AA2C802RB PDF Download Warning: Stresses beyond those listed under Absol
Y100N10E   Y100N10E Y100N10E PDF Download MOTOROLA 2007 The incoming bipolar PCM signal which is attenua
Y101   Y101 Y101 PDF Download ST SOT223 Up to 9.45Gbit/s data throughput 8 MHz to 135
Y1010   Y1010 Y1010 PDF Download FAIRCHLD TO-220 05+ NOTES 1Full Scale Range (FSR) is 3V. 2Guarante
Y1010DN   Y1010DN Y1010DN PDF Download FSC TO-220 06+ • Serial Presence Detect with Serial E2PROM
Y1010N   Y1010N Y1010N PDF Download FSC TO-220 06+ NOTES:  1. Dimensions are in inches. Lead 1
Y1011   Y1011 Y1011 PDF Download
Y101132C102RQ   Y101132C102RQ Y101132C102RQ PDF Download Input Channels 0-3 PECL/ECL differential signal
Y101132C203NQ   Y101132C203NQ Y101132C203NQ PDF Download C&K Components To facilitate motherboard development, the ISP15
Y1011U2C203NQ   Y1011U2C203NQ Y1011U2C203NQ PDF Download C&K Components From this point of view, this architecture looks
Y1011U2R401RG   Y1011U2R401RG Y1011U2R401RG PDF Download • Tri-State-Receiver Output, Weak Pull-up
Y1016   Y1016 Y1016 PDF Download The ADSP-21991 instruction set provides flexible
Y104   Y104 Y104 PDF Download ST SOT223
Y1045DN   Y1045DN Y1045DN PDF Download FAIRCHLD TO-220 05+ • JEDEC registered 1N5985 to 1N6031 ̶
Y11077   Y11077 Y11077 PDF Download Requiring 15V and +5V supplies, the ADS-930 typi
Y111122251ALFT   Y111122251ALFT Y111122251ALFT PDF Download tors. The PO+ amplifier has a gain of minus one,
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