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 All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Notes:1. IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC   2. VH=(VT+)-(VT-)
  This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.   The ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.   The ALVCH16901 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.   The ALVCH16901 has bus-hold which retains the inputs last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
The E0C33204F provides two downstream ports for the USB HC and one upstream port for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has a VBUS detection input pin.The E0C33204F also provides separate wake-up input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power management flexible. The downstream ports for the HC can be connected with any USB compliant devices and hubs that have USB upstream ports. The upstream port for the DC can be connected to any USB compliant USB host and USB hubs that have USB downstream ports.
Parr number/PDF Mfg Pack D/C Descrpion
E0C33204F   E0C33204F E0C33204F PDF Download EPSON 01+ Address Inputs Byte Enable Data In / Out Dat
E0C33208F1E   E0C33208F1E E0C33208F1E PDF Download EPSON LQFP128 2000   (ang) -112.66 -126.47 -132.57 -135.16
E0C63404D1G   E0C63404D1G E0C63404D1G PDF Download 00+ Table 1 provides an overview of the C6711/C6711B
E0C88104F0M   E0C88104F0M E0C88104F0M PDF Download EPSON 2000 THESE MATERIALS ARE PROVIDED AS IS WITHOUT WARRA
E0C88112F1R   E0C88112F1R E0C88112F1R PDF Download The information in this publication has been care
E0C88F360F   E0C88F360F E0C88F360F PDF Download EPSON Synchronous Clock Enable Input. When CEN is sampl
E0C88V01F0A   E0C88V01F0A E0C88V01F0A PDF Download EPSON TQFP DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
E0CQ105095001   E0CQ105095001 E0CQ105095001 PDF Download 1.6 µA Typical Quiescent Current Input Ope
E.B-VERS1.0   E.B-VERS1.0 E.B-VERS1.0 PDF Download 79 99+   1.1 Scope. This specification covers the
E.FL-R-SMT10   E.FL-R-SMT10 E.FL-R-SMT10 PDF Download N/A The VHC164 is an advanced high-speed CMOS device
E/1845   E/1845 E/1845 PDF Download Adjustage of stand-by SW (1) Since VCC can direc
E/P87   E/P87 E/P87 PDF Download * 1.1 Scope. This specification covers the perfo
E/P94   E/P94 E/P94 PDF Download Single-phase rectifier bridge 3-phase short ci
E00061L03F1043   E00061L03F1043 E00061L03F1043 PDF Download TOS SOP 08+ Note 1: Absolute Maximum Ratings are those values
E001   E001 E001 PDF Download NS The M48T128Y/V TIMEKEEPER® RAM is a 128Kb x
E001418140   E001418140 E001418140 PDF Download Sangshin 01+ NOTE: 1. Stresses greater than those listed und
E0021553101   E0021553101 E0021553101 PDF Download NULL 08+ Timer counter 0 : 8-bit 1  (square-wave/8-
E002P010SC   E002P010SC E002P010SC PDF Download ZILOG DIP 03+ Low-power dissipation Operating: 10.8 mW/MHz (ty
E002PZ0101SC   E002PZ0101SC E002PZ0101SC PDF Download ZILOG 00+ DIP-18 Bursts can be initiated with either ADSP (Addres
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E002SZ010SC   E002SZ010SC E002SZ010SC PDF Download ZILOG SOP 03+ 1. This device series contains ESD protection an
E003   E003 E003 PDF Download SOT-89 3. The SI-8300L series may not start up if the i
E003P8010SC   E003P8010SC E003P8010SC PDF Download • 3.3V LOW VOLTAGE, ZERO POWER OPERATION &
E003PE010SC   E003PE010SC E003PE010SC PDF Download ZiLOG O7+ NOTES: 1. Stresses above the absolute maximum ra
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E003S010SC   E003S010SC E003S010SC PDF Download ZIOLG 01+ SOP18 Before the A/D digitizing the voice-band analog
E003S2010SC   E003S2010SC E003S2010SC PDF Download 00   MPX2050 series pressure sensors are availa
E003SZ010SC   E003SZ010SC E003SZ010SC PDF Download ZIOLG SMD The SRAM will meet all stated functional and ele
E003SZ010SC-Z8P   E003SZ010SC-Z8P E003SZ010SC-Z8P PDF Download Shunt protection devices clamp voltage peaks at
E004   E004 E004 PDF Download   As the beams attached to the central mass
E0041AR64A1C   E0041AR64A1C E0041AR64A1C PDF Download ActiveThe device operates at full speed using the
E005421M   E005421M E005421M PDF Download ARCHITECTURAL ADVANTAGES   Simultaneous Re
E006047S   E006047S E006047S PDF Download Protection from switching transients and induced
E007   E007 E007 PDF Download Figure 1-2 shows how the key values in EEPROM ar
E008   E008 E008 PDF Download 7500 06+ 5.2.1 Discrete Multi Tone (DMT) Modulation and De
E009   E009 E009 PDF Download 7500 06+ Permanent device damage may occur if ABSOLUTE MA
E009UN   E009UN E009UN PDF Download FAIRCHIL QFP 07+ Memories C 8K dual voltage High Density Flash (
E00X   E00X E00X PDF Download NOTES: 1. Stresses beyond those listed may caus
E010   E010 E010 PDF Download FAIRCHILD QFN 05+ When the host detects that one or both of the bu
E01011BA   E01011BA E01011BA PDF Download N/A N/A N/A The CY7C53150L incorporates an external memory in
E0102AA2   E0102AA2 E0102AA2 PDF Download sgs sgs dc94 Although the discrete ORing diode solution has b
E0102AA2AL2   E0102AA2AL2 E0102AA2AL2 PDF Download Third Order Intermodulation Distortion   (
E0102FB   E0102FB E0102FB PDF Download tag n/a 1. Corrected the errata 2. Updated DC parameters
E01030EA   E01030EA E01030EA PDF Download
E01030FOA   E01030FOA E01030FOA PDF Download Building on experience gained from previous gene
E01031F0A   E01031F0A E01031F0A PDF Download An important feature of the E01031F0A is its abil
E01031FOA   E01031FOA E01031FOA PDF Download Active high (PFET), active low (NFET) 25mA max.
E01040FOA   E01040FOA E01040FOA PDF Download 2. A variety of power saving modes   Attach
E01040FOA(E01040F0P)   E01040FOA(E01040F0P) E01040FOA(E01040F0P) PDF Download E 0322+ contains an Erase Suspend feature. This feature
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