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Notes:  2. TA is the instant on case temperature.  3. See the last page of this specification for Group A subgroup testing information.  4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.  5. IOH = C2 mA, I OL = 2 mA for SDO.  6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly   by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note Understanding Bus Hold for additional   information.  7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.  8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test   problems caused by tester ground degradation.  9. Tested initially and after any design or process changes that may affect these parameters. 10. Measured with 16-bit counter programmed into each logic block.
It contains 6 bidirectional and digitally controlled analog switches. A built-in level shifting is included to allow an input range up to 6V (peak) for an analog signal with digital control signal of 0 to 6V. VEE supply pin is provided for analog input signals. It has an inhibit (INH) input terminal to disable all the switches when high. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND. A, B and C control inputs select one of a pair of channels. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
The C052K101K2X5CA7301 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is opti- mized for low power consumption. The AMBA Bridge pro- vides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling over- head and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contig- uous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The C052K101K2X5CA7301 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16K-byte address space allocated in the upper 3M bytes of the 4G byte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently- written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writ- ing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify- write and complex bit manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O controller. The PIO controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off-chip logic.
Parr number/PDF Mfg Pack D/C Descrpion
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