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Stereo 16-Bit Oversampling Sigma-Delta A/D Converter Stereo 16-Bit Oversampling Sigma-Delta D/A Converter Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock Selectable FIR/IIR Filter With Bypassing Option Programmable Sampling Rate up to: C Max 26 Ksps With On-Chip IIR/FIR Filter C Max 104 Ksps With IIR/FIR Bypassed On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC over 13-Khz BW Smart Time Division Multiplexed (SMARTDM®) Serial Port C Glueless 4-Wire Interface to DSP C Automatic Cascade Detection (ACD)   Self-Generates Master/Slave Device   Addresses C Programming Mode to Allow On-The-Fly   Reconfiguration C Continuous Data Transfer Mode to Minimize   Bit Clock Speed C Support Different Sampling Rate for Each   Device C Turbo Mode to Maximize Bit Clock For   Faster Data Transfer and Allow Multiple   Serial Devices to Share the Same Bus C Allows up to Eight Devices to be Connected   to a Single Serial Port Host port C 2-Wire Interface C Selectable I2C or S2C
All tests are made with 0.7ms integration time, at 10mW/cm² light = 100% at 25C at 880nm and with a clock speed of 500kHz in, 250kHz out, and 500kHz, unless otherwise specified in the Test Conditions. 100 % light under Test Conditions means that the light is set in such a way that there is 2.4V at the output of the chip. ParameterSymbol Test ConditionsMinTypMaxUnits
Single rectifier suited for switchmode power supply and high frequency DC to DC converters. Packaged in a surface mount packageD2PAK, this device is intended for use in high frequency in- verters, free wheeling and polarity protection appli- cations.
Parr number/PDF Mfg Pack D/C Descrpion
4.500M   4.500M 4.500M PDF Download KDS 12.6×12.6 DIP 4P The SMJ320C67x DSPs are the floating-point DSP f
4.500MHZ   4.500MHZ 4.500MHZ PDF Download 3 07+ • 14-Bit (XRD9814) or 16-Bit (XRD9816) &nb
4.500-X   4.500-X 4.500-X PDF Download Under-Voltage Lockout An Under-Voltage Lock-Out
4.502.7711.0   4.502.7711.0 4.502.7711.0 PDF Download Master reset for device. When active TX and RX f
4.50221E12   4.50221E12 4.50221E12 PDF Download Operating Temperature: - 55C to + 85C. (To + 125C
4.50E12   4.50E12 4.50E12 PDF Download controller/timers, a message unit with an Intell
4.50E13   4.50E13 4.50E13 PDF Download Line sensitive electronics cause an instantaneous
4.50M-OMT   4.50M-OMT 4.50M-OMT PDF Download Note: 10. All the internal timing is referenced
4.5MHZ   4.5MHZ 4.5MHZ PDF Download † For execution of these commands on cycle
4.5V   4.5V 4.5V PDF Download n/a N/A 20 Control of the device is via a simple high speed
4.000000MHZ   4.000000MHZ 4.000000MHZ PDF Download In North America, Caller ID uses the voiceband da
4.000000MZH   4.000000MZH 4.000000MZH PDF Download Revision PrI: Edits for readability and clarity,
4.0000MHZ   4.0000MHZ 4.0000MHZ PDF Download VI qualification includes aging at various extrem
4.0000MHZIQXO22CF   4.0000MHZIQXO22CF 4.0000MHZIQXO22CF PDF Download A loopback function is provided by the LBE input
4.000KSS1D   4.000KSS1D 4.000KSS1D PDF Download THE Hyundai HY57V161610D is a 16,777,216-bits CMO
4.000M   4.000M 4.000M PDF Download NO   This performance over temperature is achi
4.000MHZ   4.000MHZ 4.000MHZ PDF Download SII The Hyundai HYM72V64736AT8 Series are 64Mx72bits
4.000MHZ(20PF)   4.000MHZ(20PF) 4.000MHZ(20PF) PDF Download The TLC3541 and TLC3545 are designed to operate
4.00-20   4.00-20 4.00-20 PDF Download Unless otherwise specified, the following specif
4.00E01   4.00E01 4.00E01 PDF Download The Clock and Data Recovery stage was designed to
4.00E12   4.00E12 4.00E12 PDF Download The 4.00E12 is a miniature transmitter module tha
4.00E15   4.00E15 4.00E15 PDF Download HIGH SPEED: tPD = 5.5ns (TYP.) at VCC = 5V LOW
4.00JN   4.00JN 4.00JN PDF Download PMD warrants performance of its products to the
4.00M   4.00M 4.00M PDF Download Notes:  1. H = HIGH Voltage Level   L
4.00MHZ   4.00MHZ 4.00MHZ PDF Download 5X12 07+ Outputs from the GLBs drive the Global Routing P
4.02E11   4.02E11 4.02E11 PDF Download † Notice: Stresses above those listed under
4.032MHZ   4.032MHZ 4.032MHZ PDF Download Luminance bandwidth Chrominance bandwidth (Ext
4.032MHZ100W   4.032MHZ100W 4.032MHZ100W PDF Download Note 1: All parameters specified over standard o
4.03E11   4.03E11 4.03E11 PDF Download In conjunction with monitoring VSR for charge/dis
4.048MHZ   4.048MHZ 4.048MHZ PDF Download NO The Hitachi HN58C256A and HN58C257A are electric
4.05E11   4.05E11 4.05E11 PDF Download Mega-pixel class image quality is achieved by int
4.061-7006-0001   4.061-7006-0001 4.061-7006-0001 PDF Download The digital control section is built around the
4.06E11   4.06E11 4.06E11 PDF Download Write accesses are initiated when the following c
4.07092E12   4.07092E12 4.07092E12 PDF Download After the erase instruction is entered, CS must
4.07E20   4.07E20 4.07E20 PDF Download Note: 1. Agilents enhancement mode E-pHEMT &nbs
4.08767H3   4.08767H3 4.08767H3 PDF Download ZILOG SOP18W 2007+
4.09-20   4.09-20 4.09-20 PDF Download This power MOSFET is manufactured using an innov
4.096000MHZ   4.096000MHZ 4.096000MHZ PDF Download Typical represent average readings at +25C, VDD
4.0960MHZ   4.0960MHZ 4.0960MHZ PDF Download 8-bit A/D Converter (ADC) with 8 channels Fully
4.096AT49   4.096AT49 4.096AT49 PDF Download BVDSSDrain-to-Source Breakdown Voltage-100 W
4.096MHZ   4.096MHZ 4.096MHZ PDF Download KSS 3 07+ Positive digital supply pin for the ADC11DL066s
4.096MHZATS-49/U   4.096MHZATS-49/U 4.096MHZATS-49/U PDF Download Internal biasing controls the differential input
4.0MC   4.0MC 4.0MC PDF Download TDK 3P 2001 Analog Overvoltage input. When OV is pulled above
4.0MHZ   4.0MHZ 4.0MHZ PDF Download Flow-Through Architecture Optimizes PCB Layout
4.0MHZHC-49/U   4.0MHZHC-49/U 4.0MHZHC-49/U PDF Download The LTC®6101/LTC6101HV are versatile, high vo
4.0MHZSX-1   4.0MHZSX-1 4.0MHZSX-1 PDF Download - 4 external and 8 internal interrupt request so
4.0RXTBU65   4.0RXTBU65 4.0RXTBU65 PDF Download The WP pin, in conjuction with a WPEN bit progra
4.11E11   4.11E11 4.11E11 PDF Download Port 3 Port 3 is an 8-bit bidirectional I O port
4.11E23   4.11E23 4.11E23 PDF Download The SSRs feature a monolithic output die that min
4.12069E12   4.12069E12 4.12069E12 PDF Download The 4.12069E12 is pin compatible with the TL16C7
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